several fixes

Modules/001-CPU Board V2/PLD/Z8C-CPU-Board-U11/XXXXX.jed

@@ -0,0 +1,27 @@
+
+CUPL(WM)        5.0a  Serial# 60008009
+Device          g16v8as  Library DLIB-h-40-2
+Created         Thu Oct 20 08:10:08 2022
+Name            XXXXX
+Partno          XXXXX
+Revision        XX
+Date            XX/XX/XX
+Designer        XXXXX
+Company         XXXXX
+Assembly        XXXXX
+Location        XXXXX
+*QP20 
+*QF2194 
+*G0 
+*F0 
+*L00000 10011011101110111011101110111010
+*L00512 11110111101110111011101110111011
+*L00768 11111011011110111011101110111011
+*L01024 10101011101110111011101110101011
+*L02048 00000000010110000101100001011000
+*L02080 01011000010110000000000000000000
+*L02112 00000000010001111111111111111111
+*L02144 11111111111111111111111111111111
+*L02176 111111111111111110
+*C16AE
+*945C

Modules/001-CPU Board V2/PLD/Z8C-CPU-Board-U11/Z8C-MAINBOARD.pdf

@@ -0,0 +1,175 @@
+{COMPONENT C:\USERS\DG\DOCUMENTS\Z80\Z8C-MAINBOARD.SYM
+
+ {ENVIRONMENT
+  {PDIFvrev 3.00}
+  {Program "CUPL(WM) Version 5.0a"}
+  {DBtype "Schematic"}
+  {DBvrev 1.01}
+  {DBtime "Thu Oct 20 08:10:08 2022 "}
+  {DBunit "MIL"}
+  {DBgrid 10}
+  {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1 
+          "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1 
+          "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4 
+          "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+  {VIEW
+   {Mode SYMB}
+   {Nlst OPEN}
+   {Vw 0 0 2}
+   {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+   {Gs 10 10}
+  }
+ }
+
+ {DISPLAY
+  [Ly "PINNUM"]
+  [Ls "SOLID"][Wd 0]
+  [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+  {PIN_DEF
+   [Ly "PINCON"]
+   {P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 220}}
+   {P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
+   {P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
+   {P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+   {P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+   {P A5 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+   {P A6 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+   {P A7 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+   {P IOREQ {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+   {P RD {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+   {P WR {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+   {P CS_BANK {Pt "I/O"}{Lq 0}{Ploc 320 20}}
+   {P CS_SIO {Pt "I/O"}{Lq 0}{Ploc 320 40}}
+   {P CS_CTC {Pt "I/O"}{Lq 0}{Ploc 320 60}}
+   {P CS_DIP {Pt "I/O"}{Lq 0}{Ploc 320 80}}
+  }
+
+  {PKG
+   [Ly "REFDES"]
+   [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+   {Rdl 210 250}
+
+   [Ly "PINNUM"]
+   [Ts 15][Tj "RC"]
+   {Pnl 120 230}
+   {Pnl 120 210}
+   {Pnl 120 190}
+   {Pnl 120 170}
+   {Pnl 120 150}
+   {Pnl 120 130}
+   {Pnl 120 110}
+   {Pnl 120 90}
+   {Pnl 120 70}
+   {Pnl 120 50}
+   {Pnl 120 30}
+   [Ts 15][Tj "LC"]
+   {Pnl 300 30}
+   {Pnl 300 50}
+   {Pnl 300 70}
+   {Pnl 300 90}
+
+   {Sd A 1 2 3 4 5 6 7 8 9 11 12 15 16 17 19}
+  }
+
+  {PIC
+   [Ly "GATE"]
+   [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+   {R 130 240 290 0}
+   {L 130 220 100 220}
+   {L 130 200 100 200}
+   {L 130 180 100 180}
+   {L 130 160 100 160}
+   {L 130 140 100 140}
+   {L 130 120 100 120}
+   {L 130 100 100 100}
+   {L 130 80 100 80}
+   {L 130 60 100 60}
+   {L 130 40 100 40}
+   {L 130 20 100 20}
+   {L 290 20 320 20}
+   {L 290 40 320 40}
+   {L 290 60 320 60}
+   {L 290 80 320 80}
+   [Ly "PINNAM"]
+   [Tj "LC"]
+   {T "A0" 140 220}
+   {T "A1" 140 200}
+   {T "A2" 140 180}
+   {T "A3" 140 160}
+   {T "A4" 140 140}
+   {T "A5" 140 120}
+   {T "A6" 140 100}
+   {T "A7" 140 80}
+   {T "IOREQ" 140 60}
+   {T "RD" 140 40}
+   {T "WR" 140 20}
+   [Tj "RC"]
+   {T "CS_BANK" 280 20}
+   {T "CS_SIO" 280 40}
+   {T "CS_CTC" 280 60}
+   {T "CS_DIP" 280 80}
+   [Ly "DEVICE"]
+   [Tj "CT"]
+   {T "G16V8AS" 210 -10}
+  }
+
+  {ATR
+   {IN
+    {Org 100 20}
+    {Ty 255}
+   }
+   {EX
+    [Ly "ATTR2"]
+    [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+    {At PLD C:\USERS\DG\DOCUMENTS\Z80\Z8C-MAINBOARD 210 240}
+   }
+  }
+ }
+
+ {DETAIL
+  {ANNOTATE
+  }
+
+  {NET_DEF
+   {N A0
+   }
+   {N A1
+   }
+   {N A2
+   }
+   {N A3
+   }
+   {N A4
+   }
+   {N A5
+   }
+   {N A6
+   }
+   {N A7
+   }
+   {N IOREQ
+   }
+   {N RD
+   }
+   {N WR
+   }
+   {N CS_BANK
+   }
+   {N CS_SIO
+   }
+   {N CS_CTC
+   }
+   {N CS_DIP
+   }
+  }
+
+  {SUBCOMP
+  }
+ }
+}

Modules/001-CPU Board V2/PLD/Z8C-CPU-Board-U11/Z8C-MAINBOARD.pla

@@ -0,0 +1,27 @@
+# Berkeley PLA format generated using
+#
+# CUPL(WM)        5.0a Serial# 60008009
+# Device          g16v8as  Library DLIB-h-40-2
+# Created         Thu Oct 20 08:10:08 2022
+# Name            XXXXX
+# Partno          XXXXX
+# Revision        XX
+# Date            XX/XX/XX
+# Designer        XXXXX
+# Company         XXXXX
+# Assembly        XXXXX
+# Location        XXXXX
+#
+# Inputs  A0 A1 A2 A3 
+#         A4 A5 A6 A7 
+#         CS_BANK CS_CTC CS_DIP CS_SIO 
+#         IOREQ RD WR 
+# Outputs !CS_BANK !CS_CTC !CS_DIP !CS_SIO 
+.i 15
+.o 4
+.p 4
+00000000----0-0 1~~~
+--100000----0-- ~1~~
+10000000----00- ~~1~
+--010000----0-- ~~~1
+.end

Modules/001-CPU Board V2/PLD/Z8C-CPU-Board-U11/Z8C-MAINBOARD.sim

@@ -0,0 +1,35 @@
+%SIGNAL
+PIN   1 =  A0 
+PIN   2 =  A1 
+PIN   3 =  A2 
+PIN   4 =  A3 
+PIN   5 =  A4 
+PIN   6 =  A5 
+PIN   7 =  A6 
+PIN   8 =  A7 
+PIN  15 =  CS_BANK 
+PIN  17 =  CS_CTC 
+PIN  19 =  CS_DIP 
+PIN  16 =  CS_SIO 
+PIN   9 =  IOREQ 
+PIN  11 =  RD 
+PIN  12 =  WR 
+%END
+
+%FIELD
+%END
+
+%EQUATION
+CS_BANK =>
+    !A0 & !A1 & !A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ & !WR
+
+CS_CTC =>
+    A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ
+
+CS_DIP =>
+    A0 & !A1 & !A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ & !RD
+
+CS_SIO =>
+    !A2 & A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ
+
+%END

Modules/001-CPU Board V2/PLD/Z8C-CPU-Board-U11/Z8C-Mainboard.pld

@@ -0,0 +1,32 @@
+Name       XXXXX;
+Partno     XXXXX;
+Date       XX/XX/XX;
+Revision   XX;
+Designer   XXXXX;
+Company    XXXXX;
+Assembly   XXXXX;
+Location   XXXXX;
+DEVICE g16v8a;
+
+Pin 1 = A0;
+Pin 2 = A1;
+Pin 3 = A2;
+Pin 4 = A3;
+Pin 5 = A4;
+Pin 6 = A5;
+Pin 7 = A6;
+Pin 8 = A7;
+Pin 9 = IOREQ;
+Pin 11 = RD;
+Pin 12 = WR;
+
+Pin 15 = CS_BANK;
+Pin 16 = CS_SIO;
+Pin 17 = CS_CTC;
+Pin 19 = CS_DIP;
+
+
+CS_BANK = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & !A3 & !A2 & !A1 & !A0 & !WR);
+CS_DIP = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & !A3 & !A2 & !A1 & A0 & !RD);
+CS_CTC = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & !A3 & A2);
+CS_SIO = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & A3 & !A2);

Modules/001-CPU Board V2/Schematics/GBR/Z80-B_Mask.gbr

@@ -0,0 +1,843 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,(6.0.4)*%
+%TF.CreationDate,2022-09-27T18:30:23+02:00*%
+%TF.ProjectId,Z80,5a38302e-6b69-4636-9164-5f7063625858,rev?*%
+%TF.SameCoordinates,Original*%
+%TF.FileFunction,Soldermask,Bot*%
+%TF.FilePolarity,Negative*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (6.0.4)) date 2022-09-27 18:30:23*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
+%AMRoundRect*
+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
+20,1,$1+$1,$2,$3,$4,$5,0*
+20,1,$1+$1,$4,$5,$6,$7,0*
+20,1,$1+$1,$6,$7,$8,$9,0*
+20,1,$1+$1,$8,$9,$2,$3,0*%
+G04 Aperture macros list end*
+%ADD10C,1.400000*%
+%ADD11O,1.400000X1.400000*%
+%ADD12C,1.600000*%
+%ADD13R,1.600000X1.600000*%
+%ADD14R,2.400000X1.600000*%
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+%ADD17O,1.700000X1.700000*%
+%ADD18C,2.850000*%
+%ADD19RoundRect,0.249999X-0.525001X0.525001X-0.525001X-0.525001X0.525001X-0.525001X0.525001X0.525001X0*%
+%ADD20C,1.550000*%
+%ADD21O,1.600000X1.600000*%
+%ADD22C,4.000000*%
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+%ADD24O,1.050000X1.500000*%
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+%ADD27C,1.524000*%
+%ADD28R,4.500000X2.000000*%
+%ADD29R,2.000000X4.500000*%
+%ADD30R,2.850000X2.850000*%
+G04 APERTURE END LIST*
+D10*
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+G04 Aperture macros list end*
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Modules/001-CPU Board V2/Schematics/GBR/Z80-job.gbrjob

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+{
+  "Header": {
+    "GenerationSoftware": {
+      "Vendor": "KiCad",
+      "Application": "Pcbnew",
+      "Version": "(6.0.4)"
+    },
+    "CreationDate": "2022-09-27T18:30:23+02:00"
+  },
+  "GeneralSpecs": {
+    "ProjectId": {
+      "Name": "Z80",
+      "GUID": "5a38302e-6b69-4636-9164-5f7063625858",
+      "Revision": "rev?"
+    },
+    "Size": {
+      "X": 160.12,
+      "Y": 100.43
+    },
+    "LayerNumber": 2,
+    "BoardThickness": 1.6,
+    "Finish": "None"
+  },
+  "DesignRules": [
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+      "Layers": "Outer",
+      "PadToPad": 0.1524,
+      "PadToTrack": 0.1524,
+      "TrackToTrack": 0.1524,
+      "MinLineWidth": 0.1519,
+      "TrackToRegion": 0.508,
+      "RegionToRegion": 0.508
+    }
+  ],
+  "FilesAttributes": [
+    {
+      "Path": "Z80-F_Cu.gbr",
+      "FileFunction": "Copper,L1,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-B_Cu.gbr",
+      "FileFunction": "Copper,L2,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-F_Paste.gbr",
+      "FileFunction": "SolderPaste,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-B_Paste.gbr",
+      "FileFunction": "SolderPaste,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-F_Silkscreen.gbr",
+      "FileFunction": "Legend,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-B_Silkscreen.gbr",
+      "FileFunction": "Legend,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-F_Mask.gbr",
+      "FileFunction": "SolderMask,Top",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "Z80-B_Mask.gbr",
+      "FileFunction": "SolderMask,Bot",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "Z80-Edge_Cuts.gbr",
+      "FileFunction": "Profile",
+      "FilePolarity": "Positive"
+    }
+  ],
+  "MaterialStackup": [
+    {
+      "Type": "Legend",
+      "Name": "Top Silk Screen"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Top Solder Paste"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Top Solder Mask"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "F.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 1.51,
+      "Material": "FR4",
+      "Name": "F.Cu/B.Cu",
+      "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "B.Cu"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Bottom Solder Mask"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Bottom Solder Paste"
+    },
+    {
+      "Type": "Legend",
+      "Name": "Bottom Silk Screen"
+    }
+  ]
+}

Modules/001-CPU Board V2/Schematics/Z80.kicad_prl

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+{
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+    "active_layer_preset": "",
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+    "hidden_nets": [],
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+      "pads": 1.0,
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+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
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+      1,
+      2,
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+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 1
+  },
+  "git": {
+    "repo_password": "",
+    "repo_type": "",
+    "repo_username": "",
+    "ssh_key": ""
+  },
+  "meta": {
+    "filename": "Z80.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

Modules/001-CPU Board V2/Schematics/Z80.kicad_pro

@@ -0,0 +1,546 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [
+        {
+          "gap": 0.0,
+          "via_gap": 0.0,
+          "width": 0.0
+        }
+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "copper_edge_clearance": "error",
+        "courtyards_overlap": "ignore",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "malformed_courtyard": "ignore",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_over_copper": "ignore",
+        "silk_overlap": "ignore",
+        "skew_out_of_range": "error",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zone_has_empty_net": "error",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.15189999999999998,
+        "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.153,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_silk_clearance": 0.0,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.15189999999999998,
+        "min_via_annular_width": 0.049999999999999996,
+        "min_via_diameter": 0.39999999999999997,
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "track_widths": [
+        0.0,
+        0.1,
+        0.25,
+        0.4,
+        2.0
+      ],
+      "via_dimensions": [
+        {
+          "diameter": 0.0,
+          "drill": 0.0
+        }
+      ],
+      "zones_allow_external_fillets": false,
+      "zones_use_no_outline": true
+    },
+    "ipc2581": {
+      "dist": "",
+      "distpn": "",
+      "internal_id": "",
+      "mfg": "",
+      "mpn": ""
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
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+        0,
+        0,
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+        2,
+        2,
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+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_label_syntax": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "simulation_model_issue": "ignore",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "Z80.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.1524,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "DATA",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.1524,
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
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+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "plot": "",
+      "pos_files": "",
+      "specctra_dsn": "",
+      "step": "",
+      "svg": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "annotate_start_num": 0,
+    "bom_export_filename": "",
+    "bom_fmt_presets": [],
+    "bom_fmt_settings": {
+      "field_delimiter": ",",
+      "keep_line_breaks": false,
+      "keep_tabs": false,
+      "name": "CSV",
+      "ref_delimiter": ",",
+      "ref_range_delimiter": "",
+      "string_delimiter": "\""
+    },
+    "bom_presets": [],
+    "bom_settings": {
+      "exclude_dnp": false,
+      "fields_ordered": [
+        {
+          "group_by": false,
+          "label": "Reference",
+          "name": "Reference",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "Value",
+          "name": "Value",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Datasheet",
+          "name": "Datasheet",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Footprint",
+          "name": "Footprint",
+          "show": true
+        },
+        {
+          "group_by": false,
+          "label": "Qty",
+          "name": "${QUANTITY}",
+          "show": true
+        },
+        {
+          "group_by": true,
+          "label": "DNP",
+          "name": "${DNP}",
+          "show": true
+        }
+      ],
+      "filter_string": "",
+      "group_symbols": true,
+      "name": "Grouped By Value",
+      "sort_asc": true,
+      "sort_field": "Reference"
+    },
+    "connection_grid_size": 50.0,
+    "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.375,
+      "operating_point_overlay_i_precision": 3,
+      "operating_point_overlay_i_range": "~A",
+      "operating_point_overlay_v_precision": 3,
+      "operating_point_overlay_v_range": "~V",
+      "overbar_offset_ratio": 1.23,
+      "pin_symbol_size": 25.0,
+      "text_offset_ratio": 0.15
+    },
+    "legacy_lib_dir": "",
+    "legacy_lib_list": [],
+    "meta": {
+      "version": 1
+    },
+    "net_format_name": "",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "/nfs_rescources/Software_NEW/KiCad/GuniaLabs-sheet.kicad_wks",
+    "plot_directory": "./",
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_dissipations": false,
+    "spice_save_all_voltages": false,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
+  },
+  "sheets": [
+    [
+      "9538e4ed-27e6-4c37-b989-9859dc0d49e8",
+      "Root"
+    ]
+  ],
+  "text_variables": {}
+}

Modules/001-CPU Board V2_old/PLD/Z8C-CPU-Board-U11/XXXXX.jed

@@ -0,0 +1,27 @@
+
+CUPL(WM)        5.0a  Serial# 60008009
+Device          g16v8as  Library DLIB-h-40-2
+Created         Thu Oct 20 08:10:08 2022
+Name            XXXXX
+Partno          XXXXX
+Revision        XX
+Date            XX/XX/XX
+Designer        XXXXX
+Company         XXXXX
+Assembly        XXXXX
+Location        XXXXX
+*QP20 
+*QF2194 
+*G0 
+*F0 
+*L00000 10011011101110111011101110111010
+*L00512 11110111101110111011101110111011
+*L00768 11111011011110111011101110111011
+*L01024 10101011101110111011101110101011
+*L02048 00000000010110000101100001011000
+*L02080 01011000010110000000000000000000
+*L02112 00000000010001111111111111111111
+*L02144 11111111111111111111111111111111
+*L02176 111111111111111110
+*C16AE
+*945C

Modules/001-CPU Board V2_old/PLD/Z8C-CPU-Board-U11/Z8C-MAINBOARD.pdf

@@ -0,0 +1,175 @@
+{COMPONENT C:\USERS\DG\DOCUMENTS\Z80\Z8C-MAINBOARD.SYM
+
+ {ENVIRONMENT
+  {PDIFvrev 3.00}
+  {Program "CUPL(WM) Version 5.0a"}
+  {DBtype "Schematic"}
+  {DBvrev 1.01}
+  {DBtime "Thu Oct 20 08:10:08 2022 "}
+  {DBunit "MIL"}
+  {DBgrid 10}
+  {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1 
+          "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1 
+          "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4 
+          "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+  {VIEW
+   {Mode SYMB}
+   {Nlst OPEN}
+   {Vw 0 0 2}
+   {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+   {Gs 10 10}
+  }
+ }
+
+ {DISPLAY
+  [Ly "PINNUM"]
+  [Ls "SOLID"][Wd 0]
+  [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+  {PIN_DEF
+   [Ly "PINCON"]
+   {P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 220}}
+   {P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
+   {P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
+   {P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+   {P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+   {P A5 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+   {P A6 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+   {P A7 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+   {P IOREQ {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+   {P RD {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+   {P WR {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+   {P CS_BANK {Pt "I/O"}{Lq 0}{Ploc 320 20}}
+   {P CS_SIO {Pt "I/O"}{Lq 0}{Ploc 320 40}}
+   {P CS_CTC {Pt "I/O"}{Lq 0}{Ploc 320 60}}
+   {P CS_DIP {Pt "I/O"}{Lq 0}{Ploc 320 80}}
+  }
+
+  {PKG
+   [Ly "REFDES"]
+   [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+   {Rdl 210 250}
+
+   [Ly "PINNUM"]
+   [Ts 15][Tj "RC"]
+   {Pnl 120 230}
+   {Pnl 120 210}
+   {Pnl 120 190}
+   {Pnl 120 170}
+   {Pnl 120 150}
+   {Pnl 120 130}
+   {Pnl 120 110}
+   {Pnl 120 90}
+   {Pnl 120 70}
+   {Pnl 120 50}
+   {Pnl 120 30}
+   [Ts 15][Tj "LC"]
+   {Pnl 300 30}
+   {Pnl 300 50}
+   {Pnl 300 70}
+   {Pnl 300 90}
+
+   {Sd A 1 2 3 4 5 6 7 8 9 11 12 15 16 17 19}
+  }
+
+  {PIC
+   [Ly "GATE"]
+   [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+   {R 130 240 290 0}
+   {L 130 220 100 220}
+   {L 130 200 100 200}
+   {L 130 180 100 180}
+   {L 130 160 100 160}
+   {L 130 140 100 140}
+   {L 130 120 100 120}
+   {L 130 100 100 100}
+   {L 130 80 100 80}
+   {L 130 60 100 60}
+   {L 130 40 100 40}
+   {L 130 20 100 20}
+   {L 290 20 320 20}
+   {L 290 40 320 40}
+   {L 290 60 320 60}
+   {L 290 80 320 80}
+   [Ly "PINNAM"]
+   [Tj "LC"]
+   {T "A0" 140 220}
+   {T "A1" 140 200}
+   {T "A2" 140 180}
+   {T "A3" 140 160}
+   {T "A4" 140 140}
+   {T "A5" 140 120}
+   {T "A6" 140 100}
+   {T "A7" 140 80}
+   {T "IOREQ" 140 60}
+   {T "RD" 140 40}
+   {T "WR" 140 20}
+   [Tj "RC"]
+   {T "CS_BANK" 280 20}
+   {T "CS_SIO" 280 40}
+   {T "CS_CTC" 280 60}
+   {T "CS_DIP" 280 80}
+   [Ly "DEVICE"]
+   [Tj "CT"]
+   {T "G16V8AS" 210 -10}
+  }
+
+  {ATR
+   {IN
+    {Org 100 20}
+    {Ty 255}
+   }
+   {EX
+    [Ly "ATTR2"]
+    [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+    {At PLD C:\USERS\DG\DOCUMENTS\Z80\Z8C-MAINBOARD 210 240}
+   }
+  }
+ }
+
+ {DETAIL
+  {ANNOTATE
+  }
+
+  {NET_DEF
+   {N A0
+   }
+   {N A1
+   }
+   {N A2
+   }
+   {N A3
+   }
+   {N A4
+   }
+   {N A5
+   }
+   {N A6
+   }
+   {N A7
+   }
+   {N IOREQ
+   }
+   {N RD
+   }
+   {N WR
+   }
+   {N CS_BANK
+   }
+   {N CS_SIO
+   }
+   {N CS_CTC
+   }
+   {N CS_DIP
+   }
+  }
+
+  {SUBCOMP
+  }
+ }
+}

Modules/001-CPU Board V2_old/PLD/Z8C-CPU-Board-U11/Z8C-MAINBOARD.pla

@@ -0,0 +1,27 @@
+# Berkeley PLA format generated using
+#
+# CUPL(WM)        5.0a Serial# 60008009
+# Device          g16v8as  Library DLIB-h-40-2
+# Created         Thu Oct 20 08:10:08 2022
+# Name            XXXXX
+# Partno          XXXXX
+# Revision        XX
+# Date            XX/XX/XX
+# Designer        XXXXX
+# Company         XXXXX
+# Assembly        XXXXX
+# Location        XXXXX
+#
+# Inputs  A0 A1 A2 A3 
+#         A4 A5 A6 A7 
+#         CS_BANK CS_CTC CS_DIP CS_SIO 
+#         IOREQ RD WR 
+# Outputs !CS_BANK !CS_CTC !CS_DIP !CS_SIO 
+.i 15
+.o 4
+.p 4
+00000000----0-0 1~~~
+--100000----0-- ~1~~
+10000000----00- ~~1~
+--010000----0-- ~~~1
+.end

Modules/001-CPU Board V2_old/PLD/Z8C-CPU-Board-U11/Z8C-MAINBOARD.sim

@@ -0,0 +1,35 @@
+%SIGNAL
+PIN   1 =  A0 
+PIN   2 =  A1 
+PIN   3 =  A2 
+PIN   4 =  A3 
+PIN   5 =  A4 
+PIN   6 =  A5 
+PIN   7 =  A6 
+PIN   8 =  A7 
+PIN  15 =  CS_BANK 
+PIN  17 =  CS_CTC 
+PIN  19 =  CS_DIP 
+PIN  16 =  CS_SIO 
+PIN   9 =  IOREQ 
+PIN  11 =  RD 
+PIN  12 =  WR 
+%END
+
+%FIELD
+%END
+
+%EQUATION
+CS_BANK =>
+    !A0 & !A1 & !A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ & !WR
+
+CS_CTC =>
+    A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ
+
+CS_DIP =>
+    A0 & !A1 & !A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ & !RD
+
+CS_SIO =>
+    !A2 & A3 & !A4 & !A5 & !A6 & !A7 & !IOREQ
+
+%END

Modules/001-CPU Board V2_old/PLD/Z8C-CPU-Board-U11/Z8C-Mainboard.pld

@@ -0,0 +1,32 @@
+Name       XXXXX;
+Partno     XXXXX;
+Date       XX/XX/XX;
+Revision   XX;
+Designer   XXXXX;
+Company    XXXXX;
+Assembly   XXXXX;
+Location   XXXXX;
+DEVICE g16v8a;
+
+Pin 1 = A0;
+Pin 2 = A1;
+Pin 3 = A2;
+Pin 4 = A3;
+Pin 5 = A4;
+Pin 6 = A5;
+Pin 7 = A6;
+Pin 8 = A7;
+Pin 9 = IOREQ;
+Pin 11 = RD;
+Pin 12 = WR;
+
+Pin 15 = CS_BANK;
+Pin 16 = CS_SIO;
+Pin 17 = CS_CTC;
+Pin 19 = CS_DIP;
+
+
+CS_BANK = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & !A3 & !A2 & !A1 & !A0 & !WR);
+CS_DIP = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & !A3 & !A2 & !A1 & A0 & !RD);
+CS_CTC = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & !A3 & A2);
+CS_SIO = !(!IOREQ & !A7 & !A6 & !A5 & !A4 & A3 & !A2);

Modules/001-CPU Board V2_old/Schematics/GBR/Z80-B_Mask.gbr

@@ -0,0 +1,843 @@
+%TF.GenerationSoftware,KiCad,Pcbnew,(6.0.4)*%
+%TF.CreationDate,2022-09-27T18:30:23+02:00*%
+%TF.ProjectId,Z80,5a38302e-6b69-4636-9164-5f7063625858,rev?*%
+%TF.SameCoordinates,Original*%
+%TF.FileFunction,Soldermask,Bot*%
+%TF.FilePolarity,Negative*%
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW (6.0.4)) date 2022-09-27 18:30:23*
+%MOMM*%
+%LPD*%
+G01*
+G04 APERTURE LIST*
+G04 Aperture macros list*
+%AMRoundRect*
+0 Rectangle with rounded corners*
+0 $1 Rounding radius*
+0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
+0 Add a 4 corners polygon primitive as box body*
+4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
+0 Add four circle primitives for the rounded corners*
+1,1,$1+$1,$2,$3*
+1,1,$1+$1,$4,$5*
+1,1,$1+$1,$6,$7*
+1,1,$1+$1,$8,$9*
+0 Add four rect primitives between the rounded corners*
+20,1,$1+$1,$2,$3,$4,$5,0*
+20,1,$1+$1,$4,$5,$6,$7,0*
+20,1,$1+$1,$6,$7,$8,$9,0*
+20,1,$1+$1,$8,$9,$2,$3,0*%
+G04 Aperture macros list end*
+%ADD10C,1.400000*%
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+%ADD12C,1.600000*%
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+%ADD30R,2.850000X2.850000*%
+G04 APERTURE END LIST*
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Modules/001-CPU Board V2_old/Schematics/GBR/Z80-job.gbrjob

@@ -0,0 +1,127 @@
+{
+  "Header": {
+    "GenerationSoftware": {
+      "Vendor": "KiCad",
+      "Application": "Pcbnew",
+      "Version": "(6.0.4)"
+    },
+    "CreationDate": "2022-09-27T18:30:23+02:00"
+  },
+  "GeneralSpecs": {
+    "ProjectId": {
+      "Name": "Z80",
+      "GUID": "5a38302e-6b69-4636-9164-5f7063625858",
+      "Revision": "rev?"
+    },
+    "Size": {
+      "X": 160.12,
+      "Y": 100.43
+    },
+    "LayerNumber": 2,
+    "BoardThickness": 1.6,
+    "Finish": "None"
+  },
+  "DesignRules": [
+    {
+      "Layers": "Outer",
+      "PadToPad": 0.1524,
+      "PadToTrack": 0.1524,
+      "TrackToTrack": 0.1524,
+      "MinLineWidth": 0.1519,
+      "TrackToRegion": 0.508,
+      "RegionToRegion": 0.508
+    }
+  ],
+  "FilesAttributes": [
+    {
+      "Path": "Z80-F_Cu.gbr",
+      "FileFunction": "Copper,L1,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-B_Cu.gbr",
+      "FileFunction": "Copper,L2,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-F_Paste.gbr",
+      "FileFunction": "SolderPaste,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-B_Paste.gbr",
+      "FileFunction": "SolderPaste,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-F_Silkscreen.gbr",
+      "FileFunction": "Legend,Top",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-B_Silkscreen.gbr",
+      "FileFunction": "Legend,Bot",
+      "FilePolarity": "Positive"
+    },
+    {
+      "Path": "Z80-F_Mask.gbr",
+      "FileFunction": "SolderMask,Top",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "Z80-B_Mask.gbr",
+      "FileFunction": "SolderMask,Bot",
+      "FilePolarity": "Negative"
+    },
+    {
+      "Path": "Z80-Edge_Cuts.gbr",
+      "FileFunction": "Profile",
+      "FilePolarity": "Positive"
+    }
+  ],
+  "MaterialStackup": [
+    {
+      "Type": "Legend",
+      "Name": "Top Silk Screen"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Top Solder Paste"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Top Solder Mask"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "F.Cu"
+    },
+    {
+      "Type": "Dielectric",
+      "Thickness": 1.51,
+      "Material": "FR4",
+      "Name": "F.Cu/B.Cu",
+      "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
+    },
+    {
+      "Type": "Copper",
+      "Thickness": 0.035,
+      "Name": "B.Cu"
+    },
+    {
+      "Type": "SolderMask",
+      "Thickness": 0.01,
+      "Name": "Bottom Solder Mask"
+    },
+    {
+      "Type": "SolderPaste",
+      "Name": "Bottom Solder Paste"
+    },
+    {
+      "Type": "Legend",
+      "Name": "Bottom Silk Screen"
+    }
+  ]
+}

Modules/001-CPU Board V2_old/Schematics/Z80.kicad_prl

@@ -0,0 +1,77 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "All Layers",
+    "auto_track_width": false,
+    "hidden_netclasses": [],
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "images": 0.6,
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
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+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
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+      36
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 1
+  },
+  "meta": {
+    "filename": "Z80.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

Modules/001-CPU Board V2_old/Schematics/Z80.kicad_pro

@@ -0,0 +1,642 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
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+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
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+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
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+          "height": 1.524,
+          "width": 1.524
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+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "45_degree_only": false,
+          "min_clearance": 0.508
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+      "diff_pair_dimensions": [
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+          "via_gap": 0.0,
+          "width": 0.0
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+      ],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "ignore",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_type_mismatch": "error",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "ignore",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "error",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "ignore",
+        "silk_overlap": "ignore",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "allow_blind_buried_vias": false,
+        "allow_microvias": false,
+        "max_error": 0.005,
+        "min_clearance": 0.15189999999999998,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.153,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
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+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.3,
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