115 lines
3.5 KiB
ArmAsm
115 lines
3.5 KiB
ArmAsm
; Z8C Bootloader
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; 2022 by Dennis Gunia
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BTLDR_ENTRY:
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;ld SP, 0ffffh ; set stack pointer
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;Setup Serial Interface
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LD A,01001111b ; External Trigger, Time Constant Follows
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OUT (CS_CTC_0),A
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IN A,(CS_DIP) ; Read BAUD from DIP-Switches
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OUT (CS_CTC_0),A
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LD A,00110000b ;write into WR0: error reset, select WR0
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OUT (CS_SIO_A_C),A
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LD a,018h ;write into WR0: channel reset
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OUT (CS_SIO_A_C),A
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LD a,004h ;write into WR0: select WR4
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OUT (CS_SIO_A_C),A
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;LD a,04h ;write into WR4: clkx1,1 stop bit, no parity
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LD a,01000100b ;write into WR4: clkx16,1 stop bit, no parity
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OUT (CS_SIO_A_C),A
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LD a,005h ;write into WR0: select WR5
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OUT (CS_SIO_A_C),A
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LD a,11101000b ;DTR inactive, TX 8bit, BREAK off, TX on, RTS inactive
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OUT (CS_SIO_A_C),A
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LD a,01h ;write into WR0: select WR1
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OUT (CS_SIO_A_C),A
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LD a,00000100b ;no interrupt in CH B, special RX condition affects vect
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OUT (CS_SIO_A_C),A
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LD a,02h ;write into WR0: select WR2
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OUT (CS_SIO_A_C),A
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LD a,0h ;write into WR2: cmd line int vect (see int vec table)
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;bits D3,D2,D1 are changed according to RX condition
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OUT (CS_SIO_A_C),A
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LD a,003h ;write into WR0: select WR3
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OUT (CS_SIO_A_C),A
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LD a,0C1h ;RX 8bit, auto enable off, RX on
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OUT (CS_SIO_A_C),A
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BTLDR_STARTUP_MSG:
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LD HL,[S_BTLDR_STARTUP_MSG]
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BTLDR_STARTUP_MSG_LOOP:
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LD A,(HL)
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OR A
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JR Z, BTLDR_INPUT
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CALL BTLDR_SUB_WRITEA
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INC HL
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JR BTLDR_STARTUP_MSG_LOOP
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BTLDR_INPUT:
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; Byte 1 & 2 = Length
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CALL BTLDR_SUB_INPUT_READ
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LD B, A
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CALL BTLDR_SUB_INPUT_READ
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LD C, A
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; Byte 3 & 4 = Offset / Start address
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CALL BTLDR_SUB_INPUT_READ
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LD H, A
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CALL BTLDR_SUB_INPUT_READ
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LD L, A
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; Byte 5+ = Payload
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BTLDR_INPUT_1:
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CALL BTLDR_SUB_INPUT_READ
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LD (HL),A ;Store byte
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DEC BC
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LD A,H
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OR A.L
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JR Z, BTLDR_DONE
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INC HL
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JR BTLDR_INPUT_1
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BTLDR_DONE:
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RET
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; Strings
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S_BTLDR_STARTUP_MSG:
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db "Z8C BTLDR.S V0.1 by Dennis Gunia [RDY] ",0
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; Subroutines
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BTLDR_SUB_WRITEA:
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OUT (CS_SIO_A_D),A
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BTLDR_SUB_WRITEA_WAIT:
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XOR A
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INC A
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OUT (CS_SIO_A_C),A
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IN A,(CS_SIO_A_C)
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BIT 0,A
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JR Z, BTLDR_SUB_WRITEA_WAIT
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RET
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BTLDR_SUB_RTS_OFF:
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ld a,005h ;write into WR0: select WR5
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out (CS_SIO_A_C),A
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ld a,0E8h ;DTR active, TX 8bit, BREAK off, TX on, RTS inactive
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out (CS_SIO_A_C),A
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ret
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BTLDR_SUB_RTS_ON:
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ld a,005h ;write into WR0: select WR5
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out (CS_SIO_A_C),A
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ld a,0EAh ;DTR active, TX 8bit, BREAK off, TX on, RTS active
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out (CS_SIO_A_C),A
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ret
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BTLDR_SUB_INPUT_READ:
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CALL BTLDR_SUB_RTS_ON
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XOR A
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OUT (CS_SIO_A_C), a
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IN A, (CS_SIO_A_C)
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AND 1
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JR Z, BTLDR_SUB_INPUT_READ ;LOOP IF BUFFER EMPTY
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CALL BTLDR_SUB_RTS_OFF
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IN A, (CS_SIO_A_D)
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RET |