multiple updates
This commit is contained in:
Dennis Gunia
1
OperatingSystem/iictest/include/extern_symbols.s
Symbolic link
1
OperatingSystem/iictest/include/extern_symbols.s
Symbolic link
@@ -0,0 +1 @@
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../../monitor_v2/zout/symbols.s
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270
OperatingSystem/iictest/include/kdrv_iic.s
Normal file
270
OperatingSystem/iictest/include/kdrv_iic.s
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@@ -0,0 +1,270 @@
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CS_PIO_BD .EQU 0xF5
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CS_PIO_BC .EQU 0xF7
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CS_PIO_AD .EQU 0xF4
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CS_PIO_AC .EQU 0xF6
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CS_I2C_S1 .EQU 0xF3
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CS_I2C_SX .EQU 0xF2
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iic_init:
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LD A,0xCF
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OUT (CS_PIO_AC), A
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LD A,11110101b
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OUT (CS_PIO_AC), A
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LD A,00000000b ; Reset PCF8584 minimum 30 clock cycles
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OUT (CS_PIO_AD), A
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LD BC,0x1000
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CALL _pause_loop
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LD A,0000010b
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OUT (CS_PIO_AD), A
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LD BC,0x1000
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CALL _pause_loop
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LD A, 0x80 ;S1 -> Select S0, PIN disabled, ESO = 0, Interrupt disabled, STA, STA, ACK = 0
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OUT (CS_I2C_S1),A
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CALL _slow_access
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;CALL _slow_access
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LD A,0x55 ;S0 -> Loads byte 55H into register S0'; effective own address becomes AAH
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OUT (CS_I2C_SX),A
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CALL _slow_access
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LD A, 0xA0 ;S1 -> Loads byte A0H into register S1, i.e. next byte will be loaded into the clock control register S2.
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OUT (CS_I2C_S1),A
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CALL _slow_access
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; 000100000
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LD A,0x18 ;Load 18H into S2 register (clock control - 4.43 MHz, 90 KHz)
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LD A,0x00 ;Load 18H into S2 register (clock control - 4.43 MHz, 90 KHz)
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OUT (CS_I2C_SX),A
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CALL _slow_access
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;CALL _slow_access
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;CALL _slow_access
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;CALL _slow_access
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LD A,0xC1 ;S1 -> loads byte C1H into register S1; register enable
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;serial interface, set I 2C-bus into idle mode;
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;SDA and SCL are HIGH. The next write or read
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;operation will be to/from data transfer register
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;S0 if A0 = LOW.;
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OUT (CS_I2C_S1),A
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CALL _slow_access
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RET
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;------------------------------------------------------------------------------
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; iic_send
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;
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; Sends data over the i2c bus
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; A contains BYTE COUNTER
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; B contains ADDRESS
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; DE contains location of Data Buffer
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;------------------------------------------------------------------------------
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iic_send:
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;CALL PRINTINLINE;
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;defb "SEND A",10,13,0
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PUSH BC
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PUSH AF
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CALL iic_bus_rdy
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;CALL PRINTINLINE
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;defb "SEND START",10,13,0
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LD A,B ;Load 'slave address' into S0 register:
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OUT (CS_I2C_SX),A
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CALL _slow_access
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LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
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;the 'START' condition and clocks out the slave
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;address and the clock pulse for slave acknowledgement.
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OUT (CS_I2C_S1),A
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POP AF
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LD C,A
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INC C
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_iic_send_1: ; LOOP 1 : Wait for bus ready
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; Is bus free? (S1 ~BB=1?)
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JR NZ,_iic_send_1 ; No - loop
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BIT 4,A ; slave acknowledged? (LRB = 0?)
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JR NZ, _iic_send_stop ; if not, cancel transmission
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LD A,(DE) ; Load next byte from buffer
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INC DE
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DEC C
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JR Z, _iic_send_stop ; if counter = 0, exit loop
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OUT (CS_I2C_SX),A ; Send byte
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JR _iic_send_1 ; if counter > 0, loop again
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_iic_send_stop:
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LD A, 0xC3 ;STOP
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OUT (CS_I2C_S1),A
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CALL _slow_access
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POP BC
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RET
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;------------------------------------------------------------------------------
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; iic_read
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;
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; Sends data over the i2c bus
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; A contains BYTE COUNTER
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; B contains ADDRESS
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; DE contains location of Data Buffer
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;------------------------------------------------------------------------------
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iic_read:
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PUSH DE
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PUSH BC
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PUSH AF
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LD A,B ;Load 'slave address' into S0 register:
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OR 0x01 ;Set RW Bit for read operation
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OUT (CS_I2C_SX),A
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CALL _slow_access
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CALL iic_bus_rdy ; Is bus ready
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LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
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;the 'START' condition and clocks out the slave
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;address and the clock pulse for slave acknowledgement.
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OUT (CS_I2C_S1),A
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;Setup counter
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POP AF
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LD C,A ; Load BYTE COUNTER into C
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INC C ; Offset C by 1
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_iic_read_1: ;Wait for PIN = 0
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; S1 PIN=1?
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JR NZ,_iic_read_1 ; No - loop
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BIT 3,A ; S1 LRB=0? slave ACK?
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JR NZ, _iic_read_error ; No ACK -> an error has occured
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DEC C
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LD A, C
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DEC A ;If n = m − 1?
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JR Z, _iic_read_last
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IN A,(CS_I2C_SX)
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LD (DE),A
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INC DE
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JR _iic_read_1
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_iic_read_last: ;read last byte
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LD A, 0x40
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OUT (CS_I2C_S1),A
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CALL _slow_access
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IN A,(CS_I2C_SX) ;receives the final data byte. Neg. ACK is also sent.
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LD (DE),A
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INC DE
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_iic_read_last_1:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; S1 PIN=1?
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JR NZ,_iic_read_last_1 ; No - loop
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_iic_read_error:
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NOP
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_iic_read_stop:
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LD A, 0xC3
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OUT (CS_I2C_S1),A
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CALL _slow_access
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IN A,(CS_I2C_SX) ;transfers the final data byte from the
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;data buffer to accumulator.
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CALL _slow_access
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LD (DE),A
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POP BC
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POP DE
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RET
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;------------------------------------------------------------------------------
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; iic_rdy
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;
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; Waits until the PCF8584 signals a byte transmission/reception is complete.
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;------------------------------------------------------------------------------
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iic_rdy:
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PUSH AF
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_iic_rdy_loop:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; Is Tx/Rx complete? (S1 PIN=0?)
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;call print_a_hex
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JR NZ,_iic_rdy_loop ; No - loop
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_iic_rdy_done:
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POP AF
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RET
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;------------------------------------------------------------------------------
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; i2c_bus_rdy
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;
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; Waits until the I2C bus is free before RETurning
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;------------------------------------------------------------------------------
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iic_bus_rdy:
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PUSH AF
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_iic_blp:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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PUSH AF
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call print_a_hex
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POP AF
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BIT 0,A ; Is bus free? (S1 ~BB=1?)
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JR Z,_iic_blp ; No - loop
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POP AF
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RET
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;------------------------------------------------------------------------------
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; _pause_loop
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;
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; Timer function
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;
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; 16-bit (BC) decrement counter, performing 4xNEG loop until BC
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; reaches zero.
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;
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; 61 T-states in loop = 15.25uS per loop @ 4 MHz - near enough
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; a second delay for 65,535 iterations.
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;
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; Set iteration count in BC before calling this function.
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; Destroys: BC
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;------------------------------------------------------------------------------
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_pause_loop:
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PUSH AF ; 11 T-states
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_pause_loop_lp:
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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PUSH BC ; 11 T-states
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POP BC ; 10 T-states
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PUSH BC ; 11 T-states
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POP BC ; 10 T-states
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DEC BC ; 6 T-states
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LD A,C ; 9 T-states
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OR B ; 4 T-states
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JP NZ,_pause_loop_lp ; 10 T-states
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POP AF ; 10 T-states
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RET ; Pause complete, RETurn
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iic_force_stop:
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IN A,(CS_I2C_S1)
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BIT 0, A
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RET NZ
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LD A, 11000011b
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OUT (CS_I2C_S1),A
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NOP
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NOP
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JR iic_force_stop
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_slow_access:
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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RET
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5
OperatingSystem/iictest/properties.env
Normal file
5
OperatingSystem/iictest/properties.env
Normal file
@@ -0,0 +1,5 @@
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export OPT_GEN_SYMBOLTABLE=0
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export OPT_GEN_MONFILE=1
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export OPT_GEN_OBJFILE=1
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export OPT_WRITEROM=0
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export FILENAME=test
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55
OperatingSystem/iictest/test.asm
Normal file
55
OperatingSystem/iictest/test.asm
Normal file
@@ -0,0 +1,55 @@
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.include "include/extern_symbols.s" ;include monitor symbols.
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org 0x8000
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IIC_RTC equ 11010000b
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;Testing code
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CALL iic_init
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;JP PROMPT_BEGIN
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LD BC,$1000
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CALL _pause_loop
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JP PROMPT_BEGIN
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LD DE, 0xC000 ; Set I2C Buffer Location
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LD A,0x00 ; store string in buffer
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LD (DE),A
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LD B, IIC_RTC ; Set I2C Address
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LD A, 1 ; Set I2C Buffer length
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call iic_send
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JP PROMPT_BEGIN
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.include "include/kdrv_iic.s"
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;------------------------------------------------------------------------------
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; PRINTINLINE
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;
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; String output function
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;
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; Prints in-line data (bytes immediately following the PRINTINLINE call)
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; until a string terminator is encountered (0 - null char).
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;------------------------------------------------------------------------------
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PRINTINLINE:
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EX (SP),HL ; PUSH HL and put RET ADDress into HL
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PUSH AF
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PUSH BC
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nxtILC:
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LD A,(HL)
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CP 0
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JR Z,endPrint
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CALL print_char
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INC HL
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JR nxtILC
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endPrint:
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INC HL ; Get past "null" terminator
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POP BC
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POP AF
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EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
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RET
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BIN
OperatingSystem/iictest/zout/test.bin
Normal file
BIN
OperatingSystem/iictest/zout/test.bin
Normal file
Binary file not shown.
21
OperatingSystem/iictest/zout/test.hex
Normal file
21
OperatingSystem/iictest/zout/test.hex
Normal file
@@ -0,0 +1,21 @@
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:10800000CD1C80010010CDEF80C399001100C03E4F
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:10801000001206D03E01CD5E80C399003ECFD3F65C
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:108020003EF5D3F63E00D3F4010010CDEF803E02C2
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:10803000D3F4010010CDEF803E80D3F3CD09813E13
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:1080400055D3F2CD09813EA0D3F3CD09813E183E30
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:1080500000D3F2CD09813EC1D3F3CD0981C9C5F565
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:10806000CDE18078D3F2CD09813EC5D3F3F14F0C39
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:10807000DBF3CB7F20FACB6720091A130D2804D33A
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:10808000F218ED3EC3D3F3CD0981C1C9D5C5F5784A
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:10809000F601D3F2CD0981CDE1803EC5D3F3F14F96
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:1080A0000CDBF3CB7F20FACB5F201C0D793D28063B
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:1080B000DBF2121318EB3E40D3F3CD0981DBF21251
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:1080C00013DBF3CB7F20FA003EC3D3F3CD0981DB72
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:1080D000F2CD098112C1D1C9F5DBF3CB7F20FAF1D2
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:1080E000C9F5DBF3F5CDE702F1CB4728F5F1C9F58A
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:1080F000C5C1C5C10B79B0C2F080F1C9DBF3CB4774
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:10810000C03EC3D3F3000018F300000000000000DD
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:1081100000F5F1F5F1F5F1F5F1F5F1F5F1C9E3F55A
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:10812000C57EFE002806CDB7022318F523C1F1E372
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:01813000C985
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:00000001FF
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1154
OperatingSystem/iictest/zout/test.lst
Normal file
1154
OperatingSystem/iictest/zout/test.lst
Normal file
File diff suppressed because it is too large
Load Diff
20
OperatingSystem/iictest/zout/test.mon
Normal file
20
OperatingSystem/iictest/zout/test.mon
Normal file
@@ -0,0 +1,20 @@
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!8000 CD 1C 80 01 00 10 CD EF 80 C3 99 00 11 00 C0 3E
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!8010 00 12 06 D0 3E 01 CD 5E 80 C3 99 00 3E CF D3 F6
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!8020 3E F5 D3 F6 3E 00 D3 F4 01 00 10 CD EF 80 3E 02
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!8030 D3 F4 01 00 10 CD EF 80 3E 80 D3 F3 CD 09 81 3E
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!8040 55 D3 F2 CD 09 81 3E A0 D3 F3 CD 09 81 3E 18 3E
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!8050 00 D3 F2 CD 09 81 3E C1 D3 F3 CD 09 81 C9 C5 F5
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!8060 CD E1 80 78 D3 F2 CD 09 81 3E C5 D3 F3 F1 4F 0C
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!8070 DB F3 CB 7F 20 FA CB 67 20 09 1A 13 0D 28 04 D3
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!8080 F2 18 ED 3E C3 D3 F3 CD 09 81 C1 C9 D5 C5 F5 78
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!8090 F6 01 D3 F2 CD 09 81 CD E1 80 3E C5 D3 F3 F1 4F
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!80A0 0C DB F3 CB 7F 20 FA CB 5F 20 1C 0D 79 3D 28 06
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!80B0 DB F2 12 13 18 EB 3E 40 D3 F3 CD 09 81 DB F2 12
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!80C0 13 DB F3 CB 7F 20 FA 00 3E C3 D3 F3 CD 09 81 DB
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!80D0 F2 CD 09 81 12 C1 D1 C9 F5 DB F3 CB 7F 20 FA F1
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!80E0 C9 F5 DB F3 F5 CD E7 02 F1 CB 47 28 F5 F1 C9 F5
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!80F0 C5 C1 C5 C1 0B 79 B0 C2 F0 80 F1 C9 DB F3 CB 47
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!8100 C0 3E C3 D3 F3 00 00 18 F3 00 00 00 00 00 00 00
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!8110 00 F5 F1 F5 F1 F5 F1 F5 F1 F5 F1 F5 F1 C9 E3 F5
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!8120 C5 7E FE 00 28 06 CD B7 02 23 18 F5 23 C1 F1 E3
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!8130 C9
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