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Dennis Gunia
2022-11-02 13:13:47 +01:00
parent 28eef40645
commit e3ddeb6121
47 changed files with 34127 additions and 1 deletions
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28
PLDs/Z8C-MIO-Board-U2/XXXXX.jed Normal file
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8as Library DLIB-h-40-2
Created Sat Oct 29 22:13:29 2022
Name XXXXX
Partno XXXXX
Revision XX
Date XX/XX/XX
Designer XXXXX
Company XXXXX
Assembly XXXXX
Location XXXXX
*QP20
*QF2194
*G0
*F0
*L00256 11101111111110111011101110111111
*L00512 11101111111101111011101110111111
*L00768 11101111111111110111101110111111
*L01024 11101111111110111011011110111111
*L01792 10111111111111111111111110111111
*L02048 00000001010110000101100001011000
*L02080 01011000010110000000000000000000
*L02112 00000000100001101111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C1C55
*9C39

BIN
PLDs/Z8C-MIO-Board-U2/Z8C-MAINBOARD.abs Normal file
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163
PLDs/Z8C-MIO-Board-U2/Z8C-MAINBOARD.pdf Normal file
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{COMPONENT C:\USERS\DG\DOCUMENTS\Z80-GIT\PLDS\Z8C-MIO-BOARD-U2\Z8C-MAINBOARD.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Sat Oct 29 22:13:29 2022 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P IOREQ {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P RD {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P WR {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P CS {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P BUSDIR {Pt "I/O"}{Lq 0}{Ploc 310 20}}
{P CS_FPU {Pt "I/O"}{Lq 0}{Ploc 310 40}}
{P CS_PIO {Pt "I/O"}{Lq 0}{Ploc 310 60}}
{P CS_IIC {Pt "I/O"}{Lq 0}{Ploc 310 80}}
{P CS_PS2 {Pt "I/O"}{Lq 0}{Ploc 310 100}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 205 190}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 290 30}
{Pnl 290 50}
{Pnl 290 70}
{Pnl 290 90}
{Pnl 290 110}
{Sd A 1 2 3 4 5 6 7 8 12 15 16 17 18}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 180 280 0}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{L 280 20 310 20}
{L 280 40 310 40}
{L 280 60 310 60}
{L 280 80 310 80}
{L 280 100 310 100}
[Ly "PINNAM"]
[Tj "LC"]
{T "IOREQ" 140 160}
{T "RD" 140 140}
{T "WR" 140 120}
{T "A0" 140 100}
{T "A1" 140 80}
{T "A2" 140 60}
{T "A3" 140 40}
{T "CS" 140 20}
[Tj "RC"]
{T "BUSDIR" 270 20}
{T "CS_FPU" 270 40}
{T "CS_PIO" 270 60}
{T "CS_IIC" 270 80}
{T "CS_PS2" 270 100}
[Ly "DEVICE"]
[Tj "CT"]
{T "G16V8AS" 205 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD C:\USERS\DG\DOCUMENTS\Z80-GIT\PLDS\Z8C-MIO-BOARD-U2\Z8C-MAINBOARD 205 180}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N IOREQ
}
{N RD
}
{N WR
}
{N A0
}
{N A1
}
{N A2
}
{N A3
}
{N CS
}
{N BUSDIR
}
{N CS_FPU
}
{N CS_PIO
}
{N CS_IIC
}
{N CS_PS2
}
}
{SUBCOMP
}
}
}

29
PLDs/Z8C-MIO-Board-U2/Z8C-MAINBOARD.pla Normal file
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# Berkeley PLA format generated using
#
# CUPL(WM) 5.0a Serial# 60008009
# Device g16v8as Library DLIB-h-40-2
# Created Sat Oct 29 22:13:29 2022
# Name XXXXX
# Partno XXXXX
# Revision XX
# Date XX/XX/XX
# Designer XXXXX
# Company XXXXX
# Assembly XXXXX
# Location XXXXX
#
# Inputs A0 A1 A2 A3
# BUSDIR CS CS_FPU CS_IIC
# CS_PIO CS_PS2 IOREQ RD
# WR
# Outputs BUSDIR !CS_FPU !CS_IIC !CS_PIO
# !CS_PS2
.i 13
.o 5
.p 5
-----0-----0- 1~~~~
-001-0----0-- ~1~~~
-100-0----0-- ~~1~~
--10-0----0-- ~~~1~
-000-0----0-- ~~~~1
.end

36
PLDs/Z8C-MIO-Board-U2/Z8C-MAINBOARD.sim Normal file
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%SIGNAL
PIN 4 = A0
PIN 5 = A1
PIN 6 = A2
PIN 7 = A3
PIN 12 = BUSDIR
PIN 8 = CS
PIN 15 = CS_FPU
PIN 17 = CS_IIC
PIN 16 = CS_PIO
PIN 18 = CS_PS2
PIN 1 = IOREQ
PIN 2 = RD
PIN 3 = WR
%END
%FIELD
%END
%EQUATION
BUSDIR =>
!CS & !RD
CS_FPU =>
!A1 & !A2 & A3 & !CS & !IOREQ
CS_IIC =>
A1 & !A2 & !A3 & !CS & !IOREQ
CS_PIO =>
A2 & !A3 & !CS & !IOREQ
CS_PS2 =>
!A1 & !A2 & !A3 & !CS & !IOREQ
%END

33
PLDs/Z8C-MIO-Board-U2/Z8C-Mainboard.pld Normal file
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Name XXXXX;
Partno XXXXX;
Date XX/XX/XX;
Revision XX;
Designer XXXXX;
Company XXXXX;
Assembly XXXXX;
Location XXXXX;
DEVICE g16v8a;
Pin 1 = IOREQ;
Pin 2 = RD;
Pin 3 = WR;
Pin 4 = A0;
Pin 5 = A1;
Pin 6 = A2;
Pin 7 = A3;
Pin 8 = CS;
Pin 18 = CS_PS2;
Pin 17 = CS_IIC;
Pin 16 = CS_PIO;
Pin 15 = CS_FPU;
Pin 12 = BUSDIR;
CS_PS2 = !(!IOREQ & !CS & !A3 & !A2 & !A1 );
CS_IIC = !(!IOREQ & !CS & !A3 & !A2 & A1 );
CS_PIO = !(!IOREQ & !CS & !A3 & A2 );
CS_FPU = !(!IOREQ & !CS & A3 & !A2 & !A1 );
BUSDIR = !CS & !RD;

28
PLDs/Z8C-MIO-Board-U2/tmpcsim.im Normal file
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8as Library DLIB-h-40-2
Created Thu Oct 20 08:10:08 2022
Name XXXXX
Partno XXXXX
Revision XX
Date XX/XX/XX
Designer XXXXX
Company XXXXX
Assembly XXXXX
Location XXXXX
*QP20
*QF2194
*G0
*F0
*L00000 10011011101110111011101110111010
*L00512 11110111101110111011101110111011
*L00768 11111011011110111011101110111011
*L01024 10101011101110111011101110101011
*L02048 00000000010110000101100001011000
*L02080 01011000010110000000000000000000
*L02112 00000000010001111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C16AE
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*