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added i2c controller functions, added IDE interface functions, fiexd IDE schematics

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This commit is contained in:
Dennis Gunia
2023-01-16 19:30:31 +01:00
parent 265342e7f7
commit 96c4dca4d5
34 changed files with 18931 additions and 3700 deletions
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PLDs/Z8C-IDE-Board-U8/XXXXX.jed Normal file
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8as Library DLIB-h-40-2
Created Sun Jan 15 20:24:25 2023
Name XXXXX
Partno XXXXX
Revision XX
Date XX/XX/XX
Designer XXXXX
Company XXXXX
Assembly XXXXX
Location XXXXX
*QP20
*QF2194
*G0
*F0
*L01024 11101011111111111111111111111011
*L01792 11101111111111111111111110111111
*L02048 00100001010110000101100001011000
*L02080 01011000010110000000000000000000
*L02112 00000000110101101111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C1110
*84C9

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PLDs/Z8C-IDE-Board-U8/Z8C-MAINBOARD.abs Normal file
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PLDs/Z8C-IDE-Board-U8/Z8C-MAINBOARD.pdf Normal file
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{COMPONENT Z:\HOME\DENNISGUNIA\PROJECTS\Z8C-HOMEBREW-COMPUTER\PLDS\Z8C-IDE-BOARD-U8\Z8C-MAINBOARD.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Sun Jan 15 20:24:25 2023 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P CS {Pt "INPUT"}{Lq 0}{Ploc 100 240}}
{P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 220}}
{P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
{P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
{P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P RD {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P IOREQ {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P WR {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P CS_LATCH {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P CS_FDC {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P CLK2 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P CLK4 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P BUSDIR {Pt "I/O"}{Lq 0}{Ploc 360 20}}
{P CS_IDE {Pt "I/O"}{Lq 0}{Ploc 360 40}}
{P BUS_WAIT {Pt "I/O"}{Lq 0}{Ploc 360 60}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 230 270}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 250}
{Pnl 120 230}
{Pnl 120 210}
{Pnl 120 190}
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 340 30}
{Pnl 340 50}
{Pnl 340 70}
{Sd A 1 2 3 4 5 8 9 11 13 14 18 19 12 15 17}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 260 330 0}
{L 130 240 100 240}
{L 130 220 100 220}
{L 130 200 100 200}
{L 130 180 100 180}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{L 330 20 360 20}
{L 330 40 360 40}
{L 330 60 360 60}
[Ly "PINNAM"]
[Tj "LC"]
{T "CS" 140 240}
{T "A1" 140 220}
{T "A2" 140 200}
{T "A3" 140 180}
{T "A4" 140 160}
{T "RD" 140 140}
{T "IOREQ" 140 120}
{T "WR" 140 100}
{T "CS_LATCH" 140 80}
{T "CS_FDC" 140 60}
{T "CLK2" 140 40}
{T "CLK4" 140 20}
[Tj "RC"]
{T "BUSDIR" 320 20}
{T "CS_IDE" 320 40}
{T "BUS_WAIT" 320 60}
[Ly "DEVICE"]
[Tj "CT"]
{T "G16V8AS" 230 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD Z:\HOME\DENNISGUNIA\PROJECTS\Z8C-HOMEBREW-COMPUTER\PLDS\Z8C-IDE-BOARD-U8\Z8C-MAINBOARD 230 260}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N CS
}
{N A1
}
{N A2
}
{N A3
}
{N A4
}
{N RD
}
{N IOREQ
}
{N WR
}
{N CS_LATCH
}
{N CS_FDC
}
{N CLK2
}
{N CLK4
}
{N BUSDIR
}
{N CS_IDE
}
{N BUS_WAIT
}
}
{SUBCOMP
}
}
}

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PLDs/Z8C-IDE-Board-U8/Z8C-MAINBOARD.sim Normal file
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%SIGNAL
PIN 2 = A1
PIN 3 = A2
PIN 4 = A3
PIN 5 = A4
PIN 12 = BUSDIR
PIN 17 = BUS_WAIT
PIN 18 = CLK2
PIN 19 = CLK4
PIN 1 = CS
PIN 14 = CS_FDC
PIN 15 = CS_IDE
PIN 13 = CS_LATCH
PIN 9 = IOREQ
PIN 8 = RD
PIN 11 = WR
%END
%FIELD
%END
%EQUATION
BUSDIR =>
!CS & !RD
BUS_WAIT =>
0
CS_IDE =>
!A2 & !CS & !IOREQ
%END

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PLDs/Z8C-IDE-Board-U8/Z8C-Mainboard.pld Normal file
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Name XXXXX;
Partno XXXXX;
Date XX/XX/XX;
Revision XX;
Designer XXXXX;
Company XXXXX;
Assembly XXXXX;
Location XXXXX;
DEVICE g16v8a;
Pin 1 = CS;
Pin 2 = A1;
Pin 3 = A2;
Pin 4 = A3;
Pin 5 = A4;
Pin 9 = IOREQ;
Pin 11 = WR;
Pin 8 = RD;
Pin 13 = CS_LATCH;
Pin 14 = CS_FDC;
Pin 15 = CS_IDE;
Pin 12 = BUSDIR;
Pin 17 = BUS_WAIT;
Pin 18 = CLK2;
Pin 19 = CLK4;
CS_IDE = !(!IOREQ & !CS & !A2 );
BUSDIR = !CS & !RD;
BUS_WAIT = 'b'0;

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PLDs/Z8C-IDE-Board-U8/tmpcsim.im Normal file
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8as Library DLIB-h-40-2
Created Thu Oct 20 08:10:08 2022
Name XXXXX
Partno XXXXX
Revision XX
Date XX/XX/XX
Designer XXXXX
Company XXXXX
Assembly XXXXX
Location XXXXX
*QP20
*QF2194
*G0
*F0
*L00000 10011011101110111011101110111010
*L00512 11110111101110111011101110111011
*L00768 11111011011110111011101110111011
*L01024 10101011101110111011101110101011
*L02048 00000000010110000101100001011000
*L02080 01011000010110000000000000000000
*L02112 00000000010001111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C16AE
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*