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added i2c controller functions, added IDE interface functions, fiexd IDE schematics

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This commit is contained in:
Dennis Gunia
2023-01-16 19:30:31 +01:00
parent 265342e7f7
commit 96c4dca4d5
34 changed files with 18931 additions and 3700 deletions
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243
OperatingSystem/software/include/kdrv_ide8255.s Normal file
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;----------------------------------------------------------------
;BIOS Driver for IDE Interface 82C55
;by Dennis Gunia (01/2023)
;----------------------------------------------------------------
;================================================================
; I/O registers
;================================================================
CS_PIA_PA .EQU 0x30 ; D0-7
CS_PIA_PB .EQU 0x31 ; D8-15
CS_PIA_PC .EQU 0x32 ; Controll Lines
CS_PIA_CR .EQU 0x33
;================================================================
; I/O pins
;================================================================
IDE_WR .EQU 00100000b
IDE_RD .EQU 01000000b
IDE_RST .EQU 10000000b
;================================================================
; IDE registers
;================================================================
IDE_REG_DATA .EQU 01000b ;data I/O register (16-bits)
IDE_REG_ERROR .EQU 01001b ;error information register when read; write precompensation register when written.
IDE_REG_SECTOR .EQU 01010b ;Sector counter register
IDE_REG_SSECTOR .EQU 01011b ;Start sector register
IDE_REG_LCYL .EQU 01100b ;Low byte of the cylinder number
IDE_REG_HCYL .EQU 01101b ;High two bits of the cylinder number
IDE_REG_HEAD .EQU 01110b ;Head and device select register
IDE_REG_CMDSTS .EQU 01111b ;command/status register
IDE_REG_ALTSTS .EQU 10110b ;Alternate Status/Digital Output
IDE_REG_DRVADDR .EQU 10111b ;Drive Address
;================================================================
; I/O access functions
;================================================================
;------------------------------------------------------------------------------
; ide_reset
;
; resets drives on bus
;------------------------------------------------------------------------------
ide_reset:
LD A, 10000000b ;CommandByte-A, Mode 0, PA Out, PC Out, PB Out
OUT (CS_PIA_CR), A ;Set Data direction to out
LD A, IDE_RST
OUT (CS_PIA_PC), A ;Reset IDE Device
NOP
XOR A
OUT (CS_PIA_PC), A ;end device reset
RET
;------------------------------------------------------------------------------
; ide_regwrite_8
;
; Sends data to the IDE device
; A contains DATA
; B contains register number
;------------------------------------------------------------------------------
ide_regwrite_8:
PUSH AF ;store date to stack
; Prepare PIA Data Direction
LD A, 10000000b ;CommandByte-A, Mode 0, PA Out, PC Out, PB Out
OUT (CS_PIA_CR), A ;Set Data direction to out
; Write Data out
POP AF
OUT (CS_PIA_PA), A ;Write Data to bit 0-7
;Prepare Address
LD A, B ;Load register address
AND 00011111b ;Mask unused bits
OUT (CS_PIA_PC), A ;Write Data to bit controll lines
OR IDE_WR ;Set Write bit
OUT (CS_PIA_PC), A ;Set write signal
NOP ;delay to wait for processing
LD A, B ;Load register address
AND 00011111b ;Mask unused bits
OUT (CS_PIA_PC), A ;disable write signal
NOP
XOR A ;clear register A
OUT (CS_PIA_PC), A ;clear controll lines
RET
;------------------------------------------------------------------------------
; ide_regread_8
;
; Sends data to the IDE device
; B contains register number
; A returns data
;------------------------------------------------------------------------------
ide_regread_8:
LD A, 10010010b ;CommandByte-A, Mode 0, PA IN, PC Out, PB IN
OUT (CS_PIA_CR), A ;Set Data direction to in
;Prepare Address
LD A, B ;Load register address
AND 00011111b ;Mask unused bits
OUT (CS_PIA_PC), A ;Write Data to bit controll lines
OR IDE_RD ;Set Write bit
OUT (CS_PIA_PC), A ;Write Data to bit controll lines
NOP ;delay to wait for processing
PUSH AF
POP AF
PUSH AF
POP AF
PUSH AF
POP AF
PUSH AF
POP AF
IN A,(CS_PIA_PA) ;read data from ide device to b (because a is used later)
PUSH AF
XOR A ;clear register A
OUT (CS_PIA_PC), A ;clear controll lines
POP AF ;put data in accumulator
RET
;------------------------------------------------------------------------------
; ide_readsector_256
;
; Reads IDE Data
; HL contains destination address
;------------------------------------------------------------------------------
ide_readsector_256:
LD C,255 ;Setup counter for 256 words
ide_readsector_256_waitloop:
LD B, IDE_REG_CMDSTS
CALL ide_regread_8
BIT 0,a ;Error Bit set.
JP NZ, ide_printerror
BIT 3,a ;DRQ Bit set. If set, disk has data
JR Z, ide_readsector_256_waitloop ;If not set, wait
LD A, 10010010b ;CommandByte-A, Mode 0, PA IN, PC Out, PB IN
OUT (CS_PIA_CR), A ;Set Data direction to IN
LD A, IDE_REG_DATA ;CS0 and A=0 -> I/O register
OUT (CS_PIA_PC), A ;set register
OR IDE_RD ;Set Read bit
OUT (CS_PIA_PC), A ;Write Read to bit controll lines
NOP
NOP
NOP
IN A,(CS_PIA_PB) ;Load 16-Bit data to buffer
LD (HL), A
INC HL
IN A,(CS_PIA_PA)
LD (HL), A
INC HL
LD A,C
OR A
JP Z,ide_readsector_256_done
DEC C
JR ide_readsector_256_waitloop
ide_readsector_256_done:
RET
ide_readsector_256_inv:
LD C,255 ;Setup counter for 256 words
ide_readsector_256_inv_waitloop:
LD B, IDE_REG_CMDSTS
CALL ide_regread_8
BIT 0,a ;Error Bit set.
JP NZ, ide_printerror
BIT 3,a ;DRQ Bit set. If set, disk has data
JR Z, ide_readsector_256_inv_waitloop ;If not set, wait
LD A, 10010010b ;CommandByte-A, Mode 0, PA IN, PC Out, PB IN
OUT (CS_PIA_CR), A ;Set Data direction to IN
LD A, IDE_REG_DATA ;CS0 and A=0 -> I/O register
OUT (CS_PIA_PC), A ;set register
OR IDE_RD ;Set Read bit
OUT (CS_PIA_PC), A ;Write Read to bit controll lines
NOP
NOP
NOP
IN A,(CS_PIA_PA) ;Load 16-Bit data to buffer
LD (HL), A
INC HL
IN A,(CS_PIA_PB)
LD (HL), A
INC HL
LD A,C
OR A
JP Z,ide_readsector_256_done
DEC C
JR ide_readsector_256_inv_waitloop
;------------------------------------------------------------------------------
; ide_writesector_256
;
; Writes 512 bytes (256 words) of IDE Data
; HL contains data start address
;------------------------------------------------------------------------------
ide_writesector_256:
RET ;NOT IMPLEMENTED
;================================================================
; utility functions
;================================================================
;------------------------------------------------------------------------------
; ide_printerror
;
; prints IDE error to console
;------------------------------------------------------------------------------
ide_printerror:
LD HL, [str_error_start]
CALL print_str
LD B, IDE_REG_CMDSTS
CALL ide_regread_8
CALL print_a_hex
LD HL, [str_error_start1]
CALL print_str
LD A,(MEM_IDE_DEVICE)
CALL print_a_hex
LD HL, [str_error_start2]
CALL print_str
LD B, IDE_REG_ERROR
CALL ide_regread_8
CALL print_a_hex
LD A,10
CALL print_char
LD A,13
CALL print_char
RET
str_error_start:
db 13,10,"Disk I/O error. Status: 0x",0
str_error_start1:
db " Dev: 0x",0
str_error_start2:
db " Err: 0x",0

93
OperatingSystem/software/include/kdrv_ideif.s Normal file
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;----------------------------------------------------------------
;BIOS Driver for IDE Access
;by Dennis Gunia (01/2023)
;----------------------------------------------------------------
;================================================================
; IDE commands
;================================================================
IDE_CMD_IDENT .EQU 0xEC ;Identify drive.
IDE_CMD_READSEC .EQU 0x20 ;Read sectors.
;================================================================
; IDE Variables
;================================================================
MEM_IDE_BASE .EQU 0x5000
MEM_IDE_DEVICE .EQU MEM_IDE_BASE ;1Byte: Device ID for IDE-Port, Controller and Master/Slave
MEM_IDE_STATUS .EQU MEM_IDE_BASE + 1 ;1Byte: 0x00 if status is okay
MEM_IDE_BUFFER .EQU MEM_IDE_BASE + 2 ;512Byte: buffer for read/write data
;================================================================
; IDE funtions
;================================================================
;------------------------------------------------------------------------------
; ideif_init_drive
;
; initializes drive
;------------------------------------------------------------------------------
ideif_init_drive:
xor a
ld (MEM_IDE_DEVICE),A ;Set device to 0
ld (MEM_IDE_STATUS),A ;Set status to 0 (OK)
di ;disable interrupt
call ide_reset ;Reset drives on bus
ld hl, [str_dev_waitready]
call print_str ;print waiting message
ld DE, 0x1FFF ;preload timeout counter
ideif_init_drive_loop1:
ld b, IDE_REG_CMDSTS
call ide_regread_8 ;read drive status register
OR A
JR Z, ideif_init_drive_nodrv ;no drive found
BIT 6,A ;Wait for device ready
JR NZ, ideif_init_drive_detected
DEC DE ; decrement timeout
LD A,D
OR E
JR Z, ideif_init_drive_nodrv
JR ideif_init_drive_loop1
ideif_init_drive_nodrv:
ld hl, [str_dev_notfound]
call print_str
RET
ideif_init_drive_detected:
ld hl, [str_dev_ready]
call print_str
LD B, IDE_REG_CMDSTS ;Get drive identification
LD A, IDE_CMD_IDENT
call ide_regwrite_8 ;Write command to drive
LD HL,MEM_IDE_BUFFER ;set read/write buffer start address
call ide_readsector_256 ;read 256 words from device
LD HL,MEM_IDE_BUFFER + 20 ;print device serial
LD B, 20
CALL print_str_fixed
ld hl, [str_dev_ready2]
call print_str
LD HL,MEM_IDE_BUFFER + 54 ;print device name
LD B, 40
CALL print_str_fixed
LD A,10 ;New line
CALL print_char
LD A,13
CALL print_char
RET
;================================================================
; IDE strings
;===============================================================
str_dev_waitready:
db 13,10,"Seek HDD ... ",0
str_dev_ready:
db "Device Found!",13,10,"Serial: ",0
str_dev_ready2:
db " Name: ",0
str_dev_notfound:
db "no drive detected",13,10,0

90
OperatingSystem/software/include/prettydump.s Normal file
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;----------------------------------------------------------------
;HEX and ASCII dump function
;by Dennis Gunia (01/2023)
;----------------------------------------------------------------
;------------------------------------------------------------------------------
; dump_pretty
;
; Dumps memory content
; B contains amount of rows
; HL contains start address
; Destroys BC, HL
;------------------------------------------------------------------------------
dump_pretty:
PUSH HL
LD HL,[STR_PD_HEADER] ;Print header
CALL print_str
POP HL
dump_pretty_row:
LD A,B ;Check row counter
OR A
JP Z, dump_pretty_end ;If counter is 0, exit
DEC B ;Decrement row counter by 1
LD C, 16 ;Load column counter
LD A, H ;Print base address
CALL print_a_hex
LD A, L
CALL print_a_hex
LD A, ' '
CALL print_char
dump_pretty_col: ;Loop for column
LD A,(HL) ;Load byte to disply
CALL print_a_hex
LD A, ' '
CALL print_char
INC HL
DEC C ;Decrement column counter
JR NZ, dump_pretty_col ;Loop if not 0
dump_pretty_ascii:
PUSH BC
PUSH HL
LD B,0
LD C,16
SBC HL,BC ;Reset HL by column count
dump_pretty_ascii_loop:
LD A,(HL)
INC HL
CP 32
JP C, dump_pretty_ascii_none ;if less than 32, it is not a char
CP 127
JP NC, dump_pretty_ascii_none ;if greater or equal than 128, it is not a char
call print_char
jr dump_pretty_ascii_cont
dump_pretty_ascii_none:
LD A,'.'
call print_char
dump_pretty_ascii_cont:
DEC C
JP NZ, dump_pretty_ascii_loop
POP HL
POP BC
dump_pretty_nextrow:
LD A,10 ;New line
CALL print_char
LD A,13
CALL print_char
JR dump_pretty_row ;Else next line
dump_pretty_end:
RET
STR_PD_HEADER:
db 13,10,'BASE 0 1 2 3 4 5 6 7 8 9 A B C D E F ASCII',13,10,0
;------------------------------------------------------------------------------
; print_str_fixed
;
; Prints string with fixed length
; B contains length
; HL contains start address
;------------------------------------------------------------------------------
print_str_fixed:
LD A,(HL)
INC HL
CALL print_char
DJNZ print_str_fixed
RET

347
OperatingSystem/software/test.asm
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@@ -1,327 +1,50 @@
.include "extern_symbols.s" ;include monitor symbols.
.include "extern_symbols.s" ;include monitor symbols.
org 0xB000
CS_PIO_BD .EQU 0xF5
CS_PIO_BC .EQU 0xF7
CS_PIO_AD .EQU 0xF4
CS_PIO_AC .EQU 0xF6
;Testing code
call ideif_init_drive
CS_I2C_S1 .EQU 0xF3
CS_I2C_SX .EQU 0xF2
;testread sector
LD A,1 ;read 1 sector
LD B,IDE_REG_SECTOR
CALL ide_regwrite_8
IIC_RTC equ 11010000b
LD A,1 ;read sector 0
LD B,IDE_REG_SSECTOR
CALL ide_regwrite_8
IIC_INIT:
LD A,0xCF
OUT (CS_PIO_AC), A
LD A,11110101b
OUT (CS_PIO_AC), A
LD A,0 ;read cylinder 0
LD B,IDE_REG_LCYL
CALL ide_regwrite_8
LD A,0
LD B,IDE_REG_HCYL
CALL ide_regwrite_8
LD A,00000000b ; Reset PCF8584 minimum 30 clock cycles
OUT (CS_PIO_AD), A
LD BC,0x1000
CALL PAUSE_LOOP
LD A,0000010b
OUT (CS_PIO_AD), A
LD A,10100000b ;read head 0
LD B,IDE_REG_HEAD
CALL ide_regwrite_8
NOP
NOP
NOP
LD A, 0x80 ;S1 -> Select S0, PIN disabled, ESO = 0, Interrupt disabled, STA, STA, ACK = 0
OUT (CS_I2C_S1),A
CALL SlowAccess
CALL SlowAccess
LD A,0x55 ;S0 -> Loads byte 55H into register S0'; effective own address becomes AAH
OUT (CS_I2C_SX),A
CALL SlowAccess
LD A, 0xA0 ;S1 -> Loads byte A0H into register S1, i.e. next byte will be loaded into the clock control register S2.
OUT (CS_I2C_S1),A
CALL SlowAccess
LD A,0x00 ;Load 18H into S2 register (clock control - 8 MHz, 90 KHz)
OUT (CS_I2C_SX),A
CALL SlowAccess
LD A,0xC1 ;S1 -> loads byte C1H into register S1; register enable
;serial interface, set I 2C-bus into idle mode;
;SDA and SCL are HIGH. The next write or read
;operation will be to/from data transfer register
;S0 if A0 = LOW.;
OUT (CS_I2C_S1),A
CALL SlowAccess
;CALL force_stop
JP PROMPT_BEGIN
LD BC,$0100
CALL PAUSE_LOOP
; Send test message to RTC
LD DE, 0xC000 ; Set I2C Buffer Location
LD A,0x00
LD (DE),A
;call regdump
LD B, IIC_RTC ; Set I2C Address
LD A, 1 ; Set I2C Buffer length
call i2c_send
LD DE, 0xC010
LD B, IIC_RTC
LD A, 7
call i2c_read
LD A,IDE_CMD_READSEC ;send read command
LD B,IDE_REG_CMDSTS
CALL ide_regwrite_8
LD HL,MEM_IDE_BUFFER ;set read/write buffer start address
call ide_readsector_256_inv ;read 256 words from device
LD HL,MEM_IDE_BUFFER
LD B,32
call dump_pretty
JP PROMPT_BEGIN
;CLK_ENABLE:
; LD DE, 0xC000 ; Set I2C Buffer Location
; LD A,0x00
; LD (0xC000),A
; LD (0xC001),A
; ;call regdump
;
; LD B, IIC_RTC ; Set I2C Address
; LD A, 2 ; Set I2C Buffer length
; call i2c_send
; JP PROMPT_BEGIN
;------------------------------------------------------------------------------
; i2c_send
;
; Sends data over the i2c bus
; A contains BYTE COUNTER
; B contains ADDRESS
; DE contains location of Data Buffer
;------------------------------------------------------------------------------
i2c_send:
; CALL PRINTINLINE;
; defb "SEND A",10,13,0
PUSH BC
PUSH AF
CALL i2c_bus_rdy
; CALL PRINTINLINE
; defb "SEND START",10,13,0
LD A,B ;Load 'slave address' into S0 register:
OUT (CS_I2C_SX),A
CALL SlowAccess
.include "kdrv_ide8255.s" ;include ide interface driver.
.include "kdrv_ideif.s" ;include ide driver.
.include "prettydump.s" ;include monitor symbols.
LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
;the 'START' condition and clocks out the slave
;address and the clock pulse for slave acknowledgement.
OUT (CS_I2C_S1),A
POP AF
LD C,A
INC C
i2c_send_1: ; LOOP 1 : Wait for bus ready
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; Is bus free? (S1 ~BB=1?)
JR NZ,i2c_send_1 ; No - loop
BIT 4,A ; slave acknowledged? (LRB = 0?)
JR NZ, i2c_send_stop ; if not, cancel transmission
LD A,(DE) ; Load next byte from buffer
INC DE
DEC C
JR Z, i2c_send_stop ; if counter = 0, exit loop
OUT (CS_I2C_SX),A ; Send byte
JR i2c_send_1 ; if counter > 0, loop again
i2c_send_stop:
LD A, 0xC3 ;STOP
OUT (CS_I2C_S1),A
CALL SlowAccess
POP BC
RET
;------------------------------------------------------------------------------
; i2c_read
;
; Sends data over the i2c bus
; A contains BYTE COUNTER
; B contains ADDRESS
; DE contains location of Data Buffer
;------------------------------------------------------------------------------
i2c_read:
PUSH DE
PUSH BC
PUSH AF
LD A,B ;Load 'slave address' into S0 register:
OR 0x01 ;Set RW Bit for read operation
OUT (CS_I2C_SX),A
CALL SlowAccess
CALL i2c_bus_rdy ; Is bus ready
LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
;the 'START' condition and clocks out the slave
;address and the clock pulse for slave acknowledgement.
OUT (CS_I2C_S1),A
;Setup counter
POP AF
LD C,A ; Load BYTE COUNTER into C
INC C ; Offset C by 1
i2c_read_1: ;Wait for PIN = 0
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; S1 PIN=1?
JR NZ,i2c_read_1 ; No - loop
BIT 3,A ; S1 LRB=0? slave ACK?
JR NZ, i2c_read_error ; No ACK -> an error has occured
DEC C
LD A, C
DEC A ;If n = m − 1?
JR Z, i2c_read_last
IN A,(CS_I2C_SX)
LD (DE),A
INC DE
JR i2c_read_1
i2c_read_last: ;read last byte
LD A, 0x40
OUT (CS_I2C_S1),A
CALL SlowAccess
IN A,(CS_I2C_SX) ;receives the final data byte. Neg. ACK is also sent.
LD (DE),A
INC DE
i2c_read_last_1:
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; S1 PIN=1?
JR NZ,i2c_read_last_1 ; No - loop
i2c_read_error:
NOP
i2c_read_stop:
LD A, 0xC3
OUT (CS_I2C_S1),A
CALL SlowAccess
IN A,(CS_I2C_SX) ;transfers the final data byte from the
;data buffer to accumulator.
CALL SlowAccess
LD (DE),A
POP BC
POP DE
RET
i2c_stop_force:
;------------------------------------------------------------------------------
; i2c_rdy
;
; Waits until the PCF8584 signals a byte transmission/reception is complete.
;------------------------------------------------------------------------------
i2c_rdy:
PUSH AF
i2c_rlp:
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; Is Tx/Rx complete? (S1 PIN=0?)
call print_a_hex
JR NZ,i2c_rlp ; No - loop
i2crlpex:
POP AF
RET
;------------------------------------------------------------------------------
; i2c_bus_rdy
;
; Waits until the I2C bus is free before RETurning
;------------------------------------------------------------------------------
i2c_bus_rdy:
PUSH AF
i2c_blp:
IN A,(CS_I2C_S1) ; Read byte from S1 register
PUSH AF
call print_a_hex
delay_small:
PUSH AF
POP AF
BIT 0,A ; Is bus free? (S1 ~BB=1?)
JR Z,i2c_blp ; No - loop
i2cblpex:
POP AF
RET
;------------------------------------------------------------------------------
; PAUSE_LOOP
;
; Timer function
;
; 16-bit (BC) decrement counter, performing 4xNEG loop until BC
; reaches zero.
;
; 61 T-states in loop = 15.25uS per loop @ 4 MHz - near enough
; a second delay for 65,535 iterations.
;
; Set iteration count in BC before calling this function.
; Destroys: BC
;------------------------------------------------------------------------------
PAUSE_LOOP:
PUSH AF ; 11 T-states
pau_lp:
;NEG ; 8 T-states
;NEG ; 8 T-states
;NEG ; 8 T-states
;NEG ; 8 T-states
PUSH BC ; 11 T-states
POP BC ; 10 T-states
PUSH BC ; 11 T-states
POP BC ; 10 T-states
DEC BC ; 6 T-states
LD A,C ; 9 T-states
OR B ; 4 T-states
JP NZ,pau_lp ; 10 T-states
POP AF ; 10 T-states
RET ; Pause complete, RETurn
;------------------------------------------------------------------------------
; PRINTINLINE
;
; String output function
;
; Prints in-line data (bytes immediately following the PRINTINLINE call)
; until a string terminator is encountered (0 - null char).
;------------------------------------------------------------------------------
PRINTINLINE:
EX (SP),HL ; PUSH HL and put RET ADDress into HL
PUSH AF
PUSH BC
nxtILC:
LD A,(HL)
CP 0
JR Z,endPrint
CALL print_char
INC HL
JR nxtILC
endPrint:
INC HL ; Get past "null" terminator
POP BC
POP AF
EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
RET
SlowAccess:
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
RET
;.include "regdump.s"
force_stop:
IN A,(CS_I2C_S1)
BIT 0, A
RET NZ
LD A, 11000011b
OUT (CS_I2C_S1),A
NOP
NOP
JR force_stop
PUSH AF
POP AF
RET

327
OperatingSystem/software/test_iic.asm Normal file
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@@ -0,0 +1,327 @@
.include "extern_symbols.s" ;include monitor symbols.
org 0xB000
CS_PIO_BD .EQU 0xF5
CS_PIO_BC .EQU 0xF7
CS_PIO_AD .EQU 0xF4
CS_PIO_AC .EQU 0xF6
CS_I2C_S1 .EQU 0xF3
CS_I2C_SX .EQU 0xF2
IIC_RTC equ 11010000b
IIC_INIT:
LD A,0xCF
OUT (CS_PIO_AC), A
LD A,11110101b
OUT (CS_PIO_AC), A
LD A,00000000b ; Reset PCF8584 minimum 30 clock cycles
OUT (CS_PIO_AD), A
LD BC,0x1000
CALL PAUSE_LOOP
LD A,0000010b
OUT (CS_PIO_AD), A
NOP
NOP
NOP
LD A, 0x80 ;S1 -> Select S0, PIN disabled, ESO = 0, Interrupt disabled, STA, STA, ACK = 0
OUT (CS_I2C_S1),A
CALL SlowAccess
CALL SlowAccess
LD A,0x55 ;S0 -> Loads byte 55H into register S0'; effective own address becomes AAH
OUT (CS_I2C_SX),A
CALL SlowAccess
LD A, 0xA0 ;S1 -> Loads byte A0H into register S1, i.e. next byte will be loaded into the clock control register S2.
OUT (CS_I2C_S1),A
CALL SlowAccess
LD A,0x00 ;Load 18H into S2 register (clock control - 8 MHz, 90 KHz)
OUT (CS_I2C_SX),A
CALL SlowAccess
LD A,0xC1 ;S1 -> loads byte C1H into register S1; register enable
;serial interface, set I 2C-bus into idle mode;
;SDA and SCL are HIGH. The next write or read
;operation will be to/from data transfer register
;S0 if A0 = LOW.;
OUT (CS_I2C_S1),A
CALL SlowAccess
;CALL force_stop
JP PROMPT_BEGIN
LD BC,$0100
CALL PAUSE_LOOP
; Send test message to RTC
LD DE, 0xC000 ; Set I2C Buffer Location
LD A,0x00
LD (DE),A
;call regdump
LD B, IIC_RTC ; Set I2C Address
LD A, 1 ; Set I2C Buffer length
call i2c_send
LD DE, 0xC010
LD B, IIC_RTC
LD A, 7
call i2c_read
JP PROMPT_BEGIN
;CLK_ENABLE:
; LD DE, 0xC000 ; Set I2C Buffer Location
; LD A,0x00
; LD (0xC000),A
; LD (0xC001),A
; ;call regdump
;
; LD B, IIC_RTC ; Set I2C Address
; LD A, 2 ; Set I2C Buffer length
; call i2c_send
; JP PROMPT_BEGIN
;------------------------------------------------------------------------------
; i2c_send
;
; Sends data over the i2c bus
; A contains BYTE COUNTER
; B contains ADDRESS
; DE contains location of Data Buffer
;------------------------------------------------------------------------------
i2c_send:
; CALL PRINTINLINE;
; defb "SEND A",10,13,0
PUSH BC
PUSH AF
CALL i2c_bus_rdy
; CALL PRINTINLINE
; defb "SEND START",10,13,0
LD A,B ;Load 'slave address' into S0 register:
OUT (CS_I2C_SX),A
CALL SlowAccess
LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
;the 'START' condition and clocks out the slave
;address and the clock pulse for slave acknowledgement.
OUT (CS_I2C_S1),A
POP AF
LD C,A
INC C
i2c_send_1: ; LOOP 1 : Wait for bus ready
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; Is bus free? (S1 ~BB=1?)
JR NZ,i2c_send_1 ; No - loop
BIT 4,A ; slave acknowledged? (LRB = 0?)
JR NZ, i2c_send_stop ; if not, cancel transmission
LD A,(DE) ; Load next byte from buffer
INC DE
DEC C
JR Z, i2c_send_stop ; if counter = 0, exit loop
OUT (CS_I2C_SX),A ; Send byte
JR i2c_send_1 ; if counter > 0, loop again
i2c_send_stop:
LD A, 0xC3 ;STOP
OUT (CS_I2C_S1),A
CALL SlowAccess
POP BC
RET
;------------------------------------------------------------------------------
; i2c_read
;
; Sends data over the i2c bus
; A contains BYTE COUNTER
; B contains ADDRESS
; DE contains location of Data Buffer
;------------------------------------------------------------------------------
i2c_read:
PUSH DE
PUSH BC
PUSH AF
LD A,B ;Load 'slave address' into S0 register:
OR 0x01 ;Set RW Bit for read operation
OUT (CS_I2C_SX),A
CALL SlowAccess
CALL i2c_bus_rdy ; Is bus ready
LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
;the 'START' condition and clocks out the slave
;address and the clock pulse for slave acknowledgement.
OUT (CS_I2C_S1),A
;Setup counter
POP AF
LD C,A ; Load BYTE COUNTER into C
INC C ; Offset C by 1
i2c_read_1: ;Wait for PIN = 0
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; S1 PIN=1?
JR NZ,i2c_read_1 ; No - loop
BIT 3,A ; S1 LRB=0? slave ACK?
JR NZ, i2c_read_error ; No ACK -> an error has occured
DEC C
LD A, C
DEC A ;If n = m − 1?
JR Z, i2c_read_last
IN A,(CS_I2C_SX)
LD (DE),A
INC DE
JR i2c_read_1
i2c_read_last: ;read last byte
LD A, 0x40
OUT (CS_I2C_S1),A
CALL SlowAccess
IN A,(CS_I2C_SX) ;receives the final data byte. Neg. ACK is also sent.
LD (DE),A
INC DE
i2c_read_last_1:
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; S1 PIN=1?
JR NZ,i2c_read_last_1 ; No - loop
i2c_read_error:
NOP
i2c_read_stop:
LD A, 0xC3
OUT (CS_I2C_S1),A
CALL SlowAccess
IN A,(CS_I2C_SX) ;transfers the final data byte from the
;data buffer to accumulator.
CALL SlowAccess
LD (DE),A
POP BC
POP DE
RET
i2c_stop_force:
;------------------------------------------------------------------------------
; i2c_rdy
;
; Waits until the PCF8584 signals a byte transmission/reception is complete.
;------------------------------------------------------------------------------
i2c_rdy:
PUSH AF
i2c_rlp:
IN A,(CS_I2C_S1) ; Read byte from S1 register
BIT 7,A ; Is Tx/Rx complete? (S1 PIN=0?)
call print_a_hex
JR NZ,i2c_rlp ; No - loop
i2crlpex:
POP AF
RET
;------------------------------------------------------------------------------
; i2c_bus_rdy
;
; Waits until the I2C bus is free before RETurning
;------------------------------------------------------------------------------
i2c_bus_rdy:
PUSH AF
i2c_blp:
IN A,(CS_I2C_S1) ; Read byte from S1 register
PUSH AF
call print_a_hex
POP AF
BIT 0,A ; Is bus free? (S1 ~BB=1?)
JR Z,i2c_blp ; No - loop
i2cblpex:
POP AF
RET
;------------------------------------------------------------------------------
; PAUSE_LOOP
;
; Timer function
;
; 16-bit (BC) decrement counter, performing 4xNEG loop until BC
; reaches zero.
;
; 61 T-states in loop = 15.25uS per loop @ 4 MHz - near enough
; a second delay for 65,535 iterations.
;
; Set iteration count in BC before calling this function.
; Destroys: BC
;------------------------------------------------------------------------------
PAUSE_LOOP:
PUSH AF ; 11 T-states
pau_lp:
;NEG ; 8 T-states
;NEG ; 8 T-states
;NEG ; 8 T-states
;NEG ; 8 T-states
PUSH BC ; 11 T-states
POP BC ; 10 T-states
PUSH BC ; 11 T-states
POP BC ; 10 T-states
DEC BC ; 6 T-states
LD A,C ; 9 T-states
OR B ; 4 T-states
JP NZ,pau_lp ; 10 T-states
POP AF ; 10 T-states
RET ; Pause complete, RETurn
;------------------------------------------------------------------------------
; PRINTINLINE
;
; String output function
;
; Prints in-line data (bytes immediately following the PRINTINLINE call)
; until a string terminator is encountered (0 - null char).
;------------------------------------------------------------------------------
PRINTINLINE:
EX (SP),HL ; PUSH HL and put RET ADDress into HL
PUSH AF
PUSH BC
nxtILC:
LD A,(HL)
CP 0
JR Z,endPrint
CALL print_char
INC HL
JR nxtILC
endPrint:
INC HL ; Get past "null" terminator
POP BC
POP AF
EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
RET
SlowAccess:
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
RET
;.include "regdump.s"
force_stop:
IN A,(CS_I2C_S1)
BIT 0, A
RET NZ
LD A, 11000011b
OUT (CS_I2C_S1),A
NOP
NOP
JR force_stop

BIN
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