added i2c controller tests
This commit is contained in:
Dennis Gunia
34
OperatingSystem/software/include/regdump.s
Normal file
34
OperatingSystem/software/include/regdump.s
Normal file
@@ -0,0 +1,34 @@
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regdump:
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PUSH BC
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PUSH DE
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PUSH HL
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PUSH AF
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CALL PRINTINLINE
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defb "REGDUMP",10,13,"A: 0x",0
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call print_a_hex
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CALL PRINTINLINE
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defb " F: 0x",0
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POP BC
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PUSH BC
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LD A,C
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call print_a_hex
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CALL PRINTINLINE
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defb 13,10,"BC: 0x",0
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ld a,b
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call print_a_hex
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ld a,c
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call print_a_hex
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CALL PRINTINLINE
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defb 13,10,0
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POP AF
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POP HL
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POP DE
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POP BC
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@@ -1,10 +1,327 @@
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.include "extern_symbols.s" ;include monitor symbols.
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org 0x8000
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org 0xB000
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CS_PIO_BD .EQU 0xF5
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CS_PIO_BC .EQU 0xF7
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CS_PIO_AD .EQU 0xF4
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CS_PIO_AC .EQU 0xF6
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CS_I2C_S1 .EQU 0xF3
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CS_I2C_SX .EQU 0xF2
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IIC_RTC equ 11010000b
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IIC_INIT:
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LD A,0xCF
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OUT (CS_PIO_AC), A
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LD A,11110101b
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OUT (CS_PIO_AC), A
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LD A,00000000b ; Reset PCF8584 minimum 30 clock cycles
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OUT (CS_PIO_AD), A
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LD BC,0x1000
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CALL PAUSE_LOOP
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LD A,0000010b
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OUT (CS_PIO_AD), A
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NOP
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NOP
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NOP
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LD A, 0x80 ;S1 -> Select S0, PIN disabled, ESO = 0, Interrupt disabled, STA, STA, ACK = 0
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OUT (CS_I2C_S1),A
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CALL SlowAccess
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CALL SlowAccess
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LD A,0x55 ;S0 -> Loads byte 55H into register S0'; effective own address becomes AAH
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OUT (CS_I2C_SX),A
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CALL SlowAccess
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LD A, 0xA0 ;S1 -> Loads byte A0H into register S1, i.e. next byte will be loaded into the clock control register S2.
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OUT (CS_I2C_S1),A
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CALL SlowAccess
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LD A,0x00 ;Load 18H into S2 register (clock control - 8 MHz, 90 KHz)
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OUT (CS_I2C_SX),A
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CALL SlowAccess
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LD A,0xC1 ;S1 -> loads byte C1H into register S1; register enable
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;serial interface, set I 2C-bus into idle mode;
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;SDA and SCL are HIGH. The next write or read
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;operation will be to/from data transfer register
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;S0 if A0 = LOW.;
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OUT (CS_I2C_S1),A
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CALL SlowAccess
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;CALL force_stop
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JP PROMPT_BEGIN
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LD BC,$0100
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CALL PAUSE_LOOP
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; Send test message to RTC
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LD DE, 0xC000 ; Set I2C Buffer Location
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LD A,0x00
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LD (DE),A
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;call regdump
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LD B, IIC_RTC ; Set I2C Address
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LD A, 1 ; Set I2C Buffer length
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call i2c_send
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LD DE, 0xC010
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LD B, IIC_RTC
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LD A, 7
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call i2c_read
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LD A,4
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LD B,5
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ADD A,b
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LD (0x8010),A
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JP PROMPT_BEGIN
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;CLK_ENABLE:
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; LD DE, 0xC000 ; Set I2C Buffer Location
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; LD A,0x00
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; LD (0xC000),A
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; LD (0xC001),A
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; ;call regdump
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;
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; LD B, IIC_RTC ; Set I2C Address
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; LD A, 2 ; Set I2C Buffer length
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; call i2c_send
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; JP PROMPT_BEGIN
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;------------------------------------------------------------------------------
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; i2c_send
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;
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; Sends data over the i2c bus
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; A contains BYTE COUNTER
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; B contains ADDRESS
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; DE contains location of Data Buffer
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;------------------------------------------------------------------------------
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i2c_send:
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; CALL PRINTINLINE;
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; defb "SEND A",10,13,0
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PUSH BC
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PUSH AF
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CALL i2c_bus_rdy
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; CALL PRINTINLINE
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; defb "SEND START",10,13,0
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LD A,B ;Load 'slave address' into S0 register:
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OUT (CS_I2C_SX),A
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CALL SlowAccess
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LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
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;the 'START' condition and clocks out the slave
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;address and the clock pulse for slave acknowledgement.
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OUT (CS_I2C_S1),A
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POP AF
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LD C,A
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INC C
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i2c_send_1: ; LOOP 1 : Wait for bus ready
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; Is bus free? (S1 ~BB=1?)
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JR NZ,i2c_send_1 ; No - loop
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BIT 4,A ; slave acknowledged? (LRB = 0?)
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JR NZ, i2c_send_stop ; if not, cancel transmission
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LD A,(DE) ; Load next byte from buffer
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INC DE
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DEC C
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JR Z, i2c_send_stop ; if counter = 0, exit loop
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OUT (CS_I2C_SX),A ; Send byte
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JR i2c_send_1 ; if counter > 0, loop again
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i2c_send_stop:
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LD A, 0xC3 ;STOP
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OUT (CS_I2C_S1),A
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CALL SlowAccess
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POP BC
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RET
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;------------------------------------------------------------------------------
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; i2c_read
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;
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; Sends data over the i2c bus
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; A contains BYTE COUNTER
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; B contains ADDRESS
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; DE contains location of Data Buffer
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;------------------------------------------------------------------------------
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i2c_read:
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PUSH DE
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PUSH BC
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PUSH AF
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LD A,B ;Load 'slave address' into S0 register:
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OR 0x01 ;Set RW Bit for read operation
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OUT (CS_I2C_SX),A
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CALL SlowAccess
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CALL i2c_bus_rdy ; Is bus ready
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LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
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;the 'START' condition and clocks out the slave
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;address and the clock pulse for slave acknowledgement.
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OUT (CS_I2C_S1),A
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;Setup counter
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POP AF
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LD C,A ; Load BYTE COUNTER into C
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INC C ; Offset C by 1
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i2c_read_1: ;Wait for PIN = 0
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; S1 PIN=1?
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JR NZ,i2c_read_1 ; No - loop
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BIT 3,A ; S1 LRB=0? slave ACK?
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JR NZ, i2c_read_error ; No ACK -> an error has occured
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DEC C
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LD A, C
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DEC A ;If n = m − 1?
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JR Z, i2c_read_last
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IN A,(CS_I2C_SX)
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LD (DE),A
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INC DE
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JR i2c_read_1
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i2c_read_last: ;read last byte
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LD A, 0x40
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OUT (CS_I2C_S1),A
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CALL SlowAccess
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IN A,(CS_I2C_SX) ;receives the final data byte. Neg. ACK is also sent.
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LD (DE),A
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INC DE
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i2c_read_last_1:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; S1 PIN=1?
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JR NZ,i2c_read_last_1 ; No - loop
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i2c_read_error:
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NOP
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i2c_read_stop:
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LD A, 0xC3
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OUT (CS_I2C_S1),A
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CALL SlowAccess
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IN A,(CS_I2C_SX) ;transfers the final data byte from the
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;data buffer to accumulator.
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CALL SlowAccess
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LD (DE),A
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POP BC
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POP DE
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RET
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i2c_stop_force:
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;------------------------------------------------------------------------------
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; i2c_rdy
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;
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; Waits until the PCF8584 signals a byte transmission/reception is complete.
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;------------------------------------------------------------------------------
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i2c_rdy:
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PUSH AF
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i2c_rlp:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; Is Tx/Rx complete? (S1 PIN=0?)
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call print_a_hex
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JR NZ,i2c_rlp ; No - loop
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i2crlpex:
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POP AF
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RET
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;------------------------------------------------------------------------------
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; i2c_bus_rdy
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;
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; Waits until the I2C bus is free before RETurning
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;------------------------------------------------------------------------------
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i2c_bus_rdy:
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PUSH AF
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i2c_blp:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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PUSH AF
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call print_a_hex
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POP AF
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BIT 0,A ; Is bus free? (S1 ~BB=1?)
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JR Z,i2c_blp ; No - loop
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i2cblpex:
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POP AF
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RET
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;------------------------------------------------------------------------------
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; PAUSE_LOOP
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;
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; Timer function
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;
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; 16-bit (BC) decrement counter, performing 4xNEG loop until BC
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; reaches zero.
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;
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; 61 T-states in loop = 15.25uS per loop @ 4 MHz - near enough
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; a second delay for 65,535 iterations.
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;
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; Set iteration count in BC before calling this function.
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; Destroys: BC
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;------------------------------------------------------------------------------
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PAUSE_LOOP:
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PUSH AF ; 11 T-states
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pau_lp:
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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PUSH BC ; 11 T-states
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POP BC ; 10 T-states
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PUSH BC ; 11 T-states
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POP BC ; 10 T-states
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DEC BC ; 6 T-states
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LD A,C ; 9 T-states
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OR B ; 4 T-states
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JP NZ,pau_lp ; 10 T-states
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POP AF ; 10 T-states
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RET ; Pause complete, RETurn
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;------------------------------------------------------------------------------
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; PRINTINLINE
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;
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; String output function
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;
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; Prints in-line data (bytes immediately following the PRINTINLINE call)
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; until a string terminator is encountered (0 - null char).
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;------------------------------------------------------------------------------
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PRINTINLINE:
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EX (SP),HL ; PUSH HL and put RET ADDress into HL
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PUSH AF
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PUSH BC
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nxtILC:
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LD A,(HL)
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CP 0
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JR Z,endPrint
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CALL print_char
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INC HL
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JR nxtILC
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endPrint:
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INC HL ; Get past "null" terminator
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POP BC
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POP AF
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EX (SP),HL ; PUSH new RET ADDress on stack and restore HL
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RET
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SlowAccess:
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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RET
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;.include "regdump.s"
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force_stop:
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IN A,(CS_I2C_S1)
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BIT 0, A
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RET NZ
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LD A, 11000011b
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OUT (CS_I2C_S1),A
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NOP
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NOP
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JR force_stop
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Binary file not shown.
@@ -1,2 +1,20 @@
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:0B8000003E04060580321080C38B0098
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:10B000003ECFD3F63EF5D3F63E00D3F4010010CD8B
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:10B01000F6B03E02D3F40000003E80D3F3CD16B16B
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:10B02000CD16B13E55D3F2CD16B13EA0D3F3CD1619
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:10B03000B13E00D3F2CD16B13EC1D3F3CD16B1C3AC
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:10B040009900010001CDF6B01100C03E001206D0FB
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:10B050003E01CD62B01110C006D03E07CD90B0C306
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:10B060009900C5F5CDE8B078D3F2CD16B13EC5D381
|
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:10B07000F3F14F0CDBF3CB7F20FACB6720091A13D7
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:10B080000D2804D3F218ED3EC3D3F3CD16B1C1C9D8
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:10B09000D5C5F578F601D3F2CD16B1CDE8B03EC5F1
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:10B0A000D3F3F14F0CDBF3CB7F20FACB5F201C0DE9
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||||
:10B0B000793D2806DBF2121318EB3E40D3F3CD1690
|
||||
:10B0C000B1DBF21213DBF3CB7F20FA003EC3D3F3E4
|
||||
:10B0D000CD16B1DBF2CD16B112C1D1C9F5DBF3CB80
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||||
:10B0E0007FCDE70220F7F1C9F5DBF3F5CDE702F1FB
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:10B0F000CB4728F5F1C9F5C5C1C5C10B79B0C2F779
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||||
:10B10000B0F1C9E3F5C57EFE002806CDB7022318CD
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:10B11000F523C1F1E3C90000000000000000C9DB15
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:0CB12000F3CB47C03EC3D3F3000018F38C
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:00000001FF
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File diff suppressed because it is too large
Load Diff
@@ -1 +1,19 @@
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!8000 3E 04 06 05 80 32 10 80 C3 8B 00
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!B000 3E CF D3 F6 3E F5 D3 F6 3E 00 D3 F4 01 00 10 CD
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!B010 F6 B0 3E 02 D3 F4 00 00 00 3E 80 D3 F3 CD 16 B1
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!B020 CD 16 B1 3E 55 D3 F2 CD 16 B1 3E A0 D3 F3 CD 16
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!B030 B1 3E 00 D3 F2 CD 16 B1 3E C1 D3 F3 CD 16 B1 C3
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||||
!B040 99 00 01 00 01 CD F6 B0 11 00 C0 3E 00 12 06 D0
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||||
!B050 3E 01 CD 62 B0 11 10 C0 06 D0 3E 07 CD 90 B0 C3
|
||||
!B060 99 00 C5 F5 CD E8 B0 78 D3 F2 CD 16 B1 3E C5 D3
|
||||
!B070 F3 F1 4F 0C DB F3 CB 7F 20 FA CB 67 20 09 1A 13
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||||
!B080 0D 28 04 D3 F2 18 ED 3E C3 D3 F3 CD 16 B1 C1 C9
|
||||
!B090 D5 C5 F5 78 F6 01 D3 F2 CD 16 B1 CD E8 B0 3E C5
|
||||
!B0A0 D3 F3 F1 4F 0C DB F3 CB 7F 20 FA CB 5F 20 1C 0D
|
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!B0B0 79 3D 28 06 DB F2 12 13 18 EB 3E 40 D3 F3 CD 16
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||||
!B0C0 B1 DB F2 12 13 DB F3 CB 7F 20 FA 00 3E C3 D3 F3
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||||
!B0D0 CD 16 B1 DB F2 CD 16 B1 12 C1 D1 C9 F5 DB F3 CB
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||||
!B0E0 7F CD E7 02 20 F7 F1 C9 F5 DB F3 F5 CD E7 02 F1
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||||
!B0F0 CB 47 28 F5 F1 C9 F5 C5 C1 C5 C1 0B 79 B0 C2 F7
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!B100 B0 F1 C9 E3 F5 C5 7E FE 00 28 06 CD B7 02 23 18
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!B110 F5 23 C1 F1 E3 C9 00 00 00 00 00 00 00 00 C9 DB
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!B120 F3 CB 47 C0 3E C3 D3 F3 00 00 18 F3
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||||
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