reorganize everything
This commit is contained in:
Dennis Gunia
271
OperatingSystem/.unused/iictest/include/kdrv_iic.s
Normal file
271
OperatingSystem/.unused/iictest/include/kdrv_iic.s
Normal file
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CS_PIO_BD .EQU 0xF5
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CS_PIO_BC .EQU 0xF7
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CS_PIO_AD .EQU 0xF4
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CS_PIO_AC .EQU 0xF6
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CS_I2C_S1 .EQU 0xF3
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CS_I2C_SX .EQU 0xF2
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iic_init:
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LD A,0xCF
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OUT (CS_PIO_AC), A
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LD A,11110101b
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OUT (CS_PIO_AC), A
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LD A,00000000b ; Reset PCF8584 minimum 30 clock cycles
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OUT (CS_PIO_AD), A
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LD BC,0x1000
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CALL _pause_loop
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LD A,0000010b
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OUT (CS_PIO_AD), A
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LD BC,0x2000
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CALL _pause_loop
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LD A, 0x80 ;S1 -> Select S0, PIN disabled, ESO = 0, Interrupt disabled, STA, STA, ACK = 0
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OUT (CS_I2C_S1),A
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CALL _slow_access
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;CALL _slow_access
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LD A,0x55 ;S0 -> Loads byte 55H into register S0'; effective own address becomes AAH
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OUT (CS_I2C_SX),A
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CALL _slow_access
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LD A, 0xA0 ;S1 -> Loads byte A0H into register S1, i.e. next byte will be loaded into the clock control register S2.
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OUT (CS_I2C_S1),A
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CALL _slow_access
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; 000100000
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LD A,0x18 ;Load 18H into S2 register (clock control - 4.43 MHz, 90 KHz)
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LD A,0x00 ;Load 18H into S2 register (clock control - 4.43 MHz, 90 KHz)
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OUT (CS_I2C_SX),A
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CALL _slow_access
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;CALL _slow_access
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;CALL _slow_access
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;CALL _slow_access
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LD A,0xC1 ;S1 -> loads byte C1H into register S1; register enable
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;serial interface, set I 2C-bus into idle mode;
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;SDA and SCL are HIGH. The next write or read
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;operation will be to/from data transfer register
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;S0 if A0 = LOW.;
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OUT (CS_I2C_S1),A
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CALL _slow_access
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RET
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;------------------------------------------------------------------------------
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; iic_send
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;
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; Sends data over the i2c bus
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; A contains BYTE COUNTER
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; B contains ADDRESS
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; DE contains location of Data Buffer
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;------------------------------------------------------------------------------
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iic_send:
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;CALL PRINTINLINE;
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;defb "SEND A",10,13,0
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PUSH BC
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PUSH AF
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CALL iic_bus_rdy
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;CALL PRINTINLINE
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;defb "SEND START",10,13,0
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LD A,B ;Load 'slave address' into S0 register:
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OUT (CS_I2C_SX),A
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CALL _slow_access
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LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
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;the 'START' condition and clocks out the slave
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;address and the clock pulse for slave acknowledgement.
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OUT (CS_I2C_S1),A
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POP AF
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LD C,A
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INC C
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_iic_send_1: ; LOOP 1 : Wait for bus ready
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; Is bus free? (S1 ~BB=1?)
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JR NZ,_iic_send_1 ; No - loop
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BIT 4,A ; slave acknowledged? (LRB = 0?)
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JR NZ, _iic_send_stop ; if not, cancel transmission
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LD A,(DE) ; Load next byte from buffer
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INC DE
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DEC C
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JR Z, _iic_send_stop ; if counter = 0, exit loop
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OUT (CS_I2C_SX),A ; Send byte
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JR _iic_send_1 ; if counter > 0, loop again
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_iic_send_stop:
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LD A, 0xC3 ;STOP
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OUT (CS_I2C_S1),A
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CALL _slow_access
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POP BC
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RET
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;------------------------------------------------------------------------------
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; iic_read
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;
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; Sends data over the i2c bus
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; A contains BYTE COUNTER
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; B contains ADDRESS
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; DE contains location of Data Buffer
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;------------------------------------------------------------------------------
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iic_read:
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PUSH DE
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PUSH BC
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PUSH AF
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LD A,B ;Load 'slave address' into S0 register:
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OR 0x01 ;Set RW Bit for read operation
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OUT (CS_I2C_SX),A
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CALL _slow_access
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CALL iic_bus_rdy ; Is bus ready
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LD A, 0xC5 ;Load C5H into S1. 'C5H' = PCF8584 generates
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;the 'START' condition and clocks out the slave
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;address and the clock pulse for slave acknowledgement.
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OUT (CS_I2C_S1),A
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;Setup counter
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POP AF
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LD C,A ; Load BYTE COUNTER into C
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INC C ; Offset C by 1
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_iic_read_1: ;Wait for PIN = 0
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; S1 PIN=1?
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JR NZ,_iic_read_1 ; No - loop
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BIT 3,A ; S1 LRB=0? slave ACK?
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JR NZ, _iic_read_error ; No ACK -> an error has occured
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DEC C
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LD A, C
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DEC A ;If n = m − 1?
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JR Z, _iic_read_last
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IN A,(CS_I2C_SX)
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LD (DE),A
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INC DE
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JR _iic_read_1
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_iic_read_last: ;read last byte
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LD A, 0x40
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OUT (CS_I2C_S1),A
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CALL _slow_access
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IN A,(CS_I2C_SX) ;receives the final data byte. Neg. ACK is also sent.
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LD (DE),A
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INC DE
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_iic_read_last_1:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; S1 PIN=1?
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JR NZ,_iic_read_last_1 ; No - loop
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_iic_read_error:
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NOP
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_iic_read_stop:
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LD A, 0xC3
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OUT (CS_I2C_S1),A
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CALL _slow_access
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IN A,(CS_I2C_SX) ;transfers the final data byte from the
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;data buffer to accumulator.
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CALL _slow_access
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LD (DE),A
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POP BC
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POP DE
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RET
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;------------------------------------------------------------------------------
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; iic_rdy
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;
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; Waits until the PCF8584 signals a byte transmission/reception is complete.
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;------------------------------------------------------------------------------
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iic_rdy:
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PUSH AF
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_iic_rdy_loop:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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BIT 7,A ; Is Tx/Rx complete? (S1 PIN=0?)
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;call print_a_hex
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JR NZ,_iic_rdy_loop ; No - loop
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_iic_rdy_done:
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POP AF
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RET
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;------------------------------------------------------------------------------
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; i2c_bus_rdy
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;
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; Waits until the I2C bus is free before RETurning
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;------------------------------------------------------------------------------
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iic_bus_rdy:
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PUSH AF
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_iic_blp:
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IN A,(CS_I2C_S1) ; Read byte from S1 register
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PUSH AF
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call print_a_hex
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POP AF
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BIT 0,A ; Is bus free? (S1 ~BB=1?)
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JR Z,_iic_blp ; No - loop
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POP AF
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RET
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;------------------------------------------------------------------------------
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; _pause_loop
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;
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; Timer function
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;
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; 16-bit (BC) decrement counter, performing 4xNEG loop until BC
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; reaches zero.
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;
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; 61 T-states in loop = 15.25uS per loop @ 4 MHz - near enough
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; a second delay for 65,535 iterations.
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;
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; Set iteration count in BC before calling this function.
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; Destroys: BC
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;------------------------------------------------------------------------------
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_pause_loop:
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PUSH AF ; 11 T-states
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_pause_loop_lp:
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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;NEG ; 8 T-states
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PUSH BC ; 11 T-states
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POP BC ; 10 T-states
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PUSH BC ; 11 T-states
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POP BC ; 10 T-states
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DEC BC ; 6 T-states
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LD A,C ; 9 T-states
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OR B ; 4 T-states
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JP NZ,_pause_loop_lp ; 10 T-states
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POP AF ; 10 T-states
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RET ; Pause complete, RETurn
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iic_force_stop:
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IN A,(CS_I2C_S1)
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BIT 0, A
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RET NZ
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LD A, 11000011b
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OUT (CS_I2C_S1),A
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NOP
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NOP
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JR iic_force_stop
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_slow_access:
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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PUSH AF
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POP AF
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POP AF
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RET
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