reorganize everything
This commit is contained in:
Dennis Gunia
484
OperatingSystem/.unused/cmon/sdcc/share/doc/ucsim/stm8/test.asm
Normal file
484
OperatingSystem/.unused/cmon/sdcc/share/doc/ucsim/stm8/test.asm
Normal file
@@ -0,0 +1,484 @@
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; For an STM8S003
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TIM4_CR1 =: 0x5340
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TIM4_IER =: 0x5343
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TIM4_EGR =: 0x5345
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TIM4_ARR =: 0x5348
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.macro codebndry
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.$.end =: .
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.bndry 4
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.$.diff =: . - .$.end
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. = . - .$.diff
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.rept .$.diff
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nop
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.endm
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.endm
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.macro areabndry n
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.$.end =: .
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.bndry n
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.ifne . - .$.end
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. = . - 1
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.byte 0
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.endif
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.endm
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.area _CODE (REL,CON)
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int reset
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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int no_action
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no_action:
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iret
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codebndry
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.area INITIALIZER (REL,CON)
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.area CODE (REL,CON)
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codebndry
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reset:
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; PM0044 5.4 Conventions, table 3
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; N.B. PM004 cannot be right. Table 3 disagrees with the section 7 documentation for ADDW.
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; Table 4 has cycle counts for ADDW that disagree with the time graph on the right.
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jra table3
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codebndry
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table3: ldw x,[0x50]
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addw x,#20
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ld a,[0x30]
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table3_end:
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; PM0044 5.4.1 Optimized pipeline example, table 6
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; N.B. Table 6 has the final F3 load one cycle too early surely?
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jra table6
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codebndry
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table6: neg a
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xor a, 0x10
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ld a, #20
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sub a, 0x1000
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inc a
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ld xl, a
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srl a
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swap a
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sla 0x15
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cp a, #0xfe
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mov 0x100, #11
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mov 0x101, #22
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table6_end:
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; PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8 (requires copy to RAM)
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table8_copy:
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ldw x, #table8_end - table8_start
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jreq table8_copy_end
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table8_copy_loop:
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ld a, (table8_start - 1, x)
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ld (0x100 - 1, x), a
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decw x
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jrne table8_copy_loop
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table8_copy_end:
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call 0x100
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codebndry
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.area INITIALIZER
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codebndry
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table8_start:
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jra table8
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codebndry
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table8: neg a
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xor a, 0x10
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ld a, #20
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sub a, 0x1000
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inc a
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ld xl, a
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srl a
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swap a
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sla 0x15
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cp a, #0xfe
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ret
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table8_end:
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codebndry
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.area CODE
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codebndry
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; PM0044 5.4.3 Pipeline with Call/Jump, table 10
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jra table10
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codebndry
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table10:
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inc a
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jp label
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ldw x, [0x5432]
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label: neg a
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call label2
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ldw x, [0x5432]
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ldw x, [0x7895]
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label2: incw x
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table10_end:
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; PM0044 5.4.4 Pipeline stalled, table 12
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clr a
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ld 0x10, a
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ld 0x20, a ; Table 12 doesn't include any setup...
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jra table12
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codebndry
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table12:
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sub sp, #20
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ld a, #20
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btjt 0x10, #5, to ; Table 12 assumes not taken
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inc a
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btjf 0x20, #3, to ; Table 12 assumes taken
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nop
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ldw x, [0x5432]
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ldw x, [0x1234]
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to: incw y
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ld a, (x)
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table12_end:
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; DIV tests - available ST docs simply say "2-17 cycles"
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.macro timed_div dividend divisor ?aligned
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jra aligned
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codebndry
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aligned:
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ldw x, #dividend
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ld a, #divisor
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div x, a
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end_'aligned:
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.endm
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timed_div 0x8000,0x80
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timed_div 0x8000,0x40
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timed_div 0x8000,0x20
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timed_div 0x8000,0x10
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timed_div 0x8000,0x08
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timed_div 0x8000,0x04
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timed_div 0x8000,0x02
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timed_div 0x8000,0x01
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timed_div 0x8000,0x80
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timed_div 0x4000,0x80
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timed_div 0x2000,0x80
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timed_div 0x1000,0x80
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timed_div 0x0800,0x80
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timed_div 0x0400,0x80
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timed_div 0x0200,0x80
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timed_div 0x0100,0x80
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timed_div 0x0080,0x80
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timed_div 0x0040,0x80
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timed_div 0x0020,0x80
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timed_div 0x0010,0x80
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timed_div 0x0008,0x80
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timed_div 0x0004,0x80
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timed_div 0x0002,0x80
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timed_div 0x0001,0x80
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timed_div 0x0000,0x80
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timed_div 63, 8
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timed_div 64, 8
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timed_div 65, 8
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.macro timed_divw dividend divisor ?aligned
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jra aligned
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codebndry
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aligned:
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ldw x, #dividend
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ldw y, #divisor
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divw x, y
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end_'aligned:
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.endm
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timed_divw 0x8000, 1
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; Interrupted div
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jra test_idiv
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codebndry
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test_idiv:
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bset TIM4_IER, #0
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bset TIM4_EGR, #0
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mov TIM4_ARR, #8
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ldw x, #255
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ld a, #10
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mov TIM4_CR1, #0x0f
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div x, a
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; Exercising all code in stm8.cc + inst.cc
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.macro timed_op op operand1 operand2a operand2b ?aligned
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jra aligned
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codebndry
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aligned:
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.narg .narg
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.ifeq .narg - 4
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op operand1,operand2a,operand2b
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.else
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.ifeq .narg - 3
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op operand1,operand2a
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.else
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.ifeq .narg - 2
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op operand1
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.else
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op
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.endif
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.endif
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.endif
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end_'aligned:
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.endm
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; a, shortmem, longmem,
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; (X), (shortoff,X), (longoff,X)
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; (Y), (shortoff,Y), (longoff,Y)
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; (shortoff,SP)
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; ([shortptr.w],X), ([longptr.w],X)
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; ([shortptr.w],X), ([longptr.w],X)
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; ([shortptr.w],Y)
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.macro timed_class_1 op
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timed_op op a
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timed_op op 0xf5
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timed_op op 0xf5c2
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.irp reg,X,Y
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timed_op op (reg)
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timed_op op (0xf5,reg)
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timed_op op (0xf5c2,reg)
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.endm
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timed_op op (0xf5,SP)
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timed_op op [0xf5]
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timed_op op [0xf5c2]
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timed_op op ([0xf5],X)
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timed_op op ([0xf5c2],X)
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timed_op op ([0xf5],Y)
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.endm
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; a <- #byte, shortmem, longmem,
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; (X), (shortoff,X), (longoff,X)
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; (Y), (shortoff,Y), (longoff,Y)
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; (shortoff,SP)
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; ([shortptr.w],X), ([longptr.w],X)
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; ([shortptr.w],X), ([longptr.w],X)
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; ([shortptr.w],Y)
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.macro timed_class_2 op
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timed_op op a,#0x55
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timed_op op a,0x10
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timed_op op a,0x1000
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.irp reg,X,Y
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timed_op op a,(reg)
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timed_op op a,(0x10,reg)
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timed_op op a,(0x1000,reg)
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.endm
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timed_op op a,(0x10,SP)
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timed_op op a,[0x10]
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timed_op op a,[0x1000]
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timed_op op a,([0x10],X)
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timed_op op a,([0x1000],X)
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timed_op op a,([0x10],Y)
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.endm
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; SP <- #byte
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.macro timed_class_sp_imm op
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timed_op op sp,#0x55
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.endm
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; X, Y
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.macro timed_class_xy op
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timed_op op X
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timed_op op Y
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.endm
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; Bit addressed
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.macro timed_class_bit op
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timed_op op 0x1000,#2
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.endm
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; Inherent
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.macro timed_class_inh op
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timed_op op
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.endm
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timed_class_2 adc
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timed_class_2 add
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timed_op addw X,#0x1000
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timed_op addw X,0x1000
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timed_op addw X,(0x10,SP)
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timed_op addw Y,#0x1000
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timed_op addw Y,0x1000
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timed_op addw Y,(0x10,SP)
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timed_class_sp_imm addw
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timed_class_2 and
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timed_class_bit bccm
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timed_class_2 bcp
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timed_class_bit bcpl
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;break
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timed_class_bit bres
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timed_class_bit bset
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;btjf - covered by table 12 above
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;btjt - covered by table 12 above
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;call - uses common fetchea code
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;callf
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;callr
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timed_class_inh ccf
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timed_class_1 clr
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timed_class_xy clrw
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timed_class_2 cp
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timed_op cpw X,#0x55
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timed_op cpw X,0x10
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timed_op cpw X,0x1000
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timed_op cpw X,(Y)
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timed_op cpw X,(0x10,Y)
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timed_op cpw X,(0x1000,Y)
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timed_op cpw X,(0x10,SP)
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timed_op cpw X,[0x10]
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timed_op cpw X,[0x1000]
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timed_op cpw X,([0x10],Y)
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timed_op cpw Y,([0x1000],X)
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timed_class_1 cpl
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timed_class_xy cplw
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timed_class_1 dec
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timed_class_xy decw
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; ;div - covered above
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; ;divw - covered above
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timed_op exg a,xl
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timed_op exg a,yl
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timed_op exg a,0x1000
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timed_op exgw x,y
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;halt
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timed_class_1 inc
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timed_class_xy incw
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;int
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;iret
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;jp -covered by table 10 above
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;jpf
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;jra
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;jrxx
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timed_class_2 ld
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timed_op ld 0x10,a
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timed_op ld 0x1000,a
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timed_op ld (X),a
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timed_op ld (0x10,X),a
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timed_op ld (0x1000,X),a
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timed_op ld (Y),a
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timed_op ld (0x10,Y),a
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timed_op ld (0x1000,Y),a
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timed_op ld (0x10,SP),a
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timed_op ld [0x10],a
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timed_op ld [0x1000],a
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timed_op ld ([0x10],X),a
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timed_op ld ([0x1000],X),a
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timed_op ld ([0x10],Y),a
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timed_op ldf a,0x500000
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timed_op ldf a,(0x500000,X)
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timed_op ldf a,(0x500000,Y)
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timed_op ldf a,([0x5000],X)
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timed_op ldf a,([0x5000],Y)
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timed_op ldf a,[0x5000]
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timed_op ldw X,#0x55
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timed_op ldw X,0x10
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timed_op ldw X,0x1000
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timed_op ldw X,(X)
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timed_op ldw X,(0x10,X)
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timed_op ldw X,(0x1000,X)
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timed_op ldw X,(0x10,SP)
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timed_op ldw X,[0x10]
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timed_op ldw X,[0x1000]
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timed_op ldw X,([0x10],X)
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timed_op ldw X,([0x1000],X)
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timed_op mov 0x8000,#0xAA
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timed_op mov 0x80,0x10
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timed_op mov 0x8000,0x1000
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timed_op mul x,a
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timed_class_1 neg
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timed_class_xy negw
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timed_op nop
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timed_class_2 or
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;pop
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;popw
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;push
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;pushw
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timed_class_inh rcf
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;ret
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;retf
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; timed_class_inh rim
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timed_class_1 rlc
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timed_class_xy rlcw
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timed_class_xy rlwa
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timed_class_1 rrc
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timed_class_xy rrcw
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timed_class_xy rrwa
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timed_class_inh rvf
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timed_class_2 sbc
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timed_class_inh scf
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; timed_class_inh sim
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timed_op subw X,#0x5500
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timed_op subw X,0x1000
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timed_op subw X,(0x10,SP)
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timed_op ldw Y,X
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timed_op ldw 0x10,X
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timed_op ldw 0x1000,X
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timed_op ldw (X),Y
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timed_op ldw (0x10,X),Y
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timed_op ldw (0x1000,X),Y
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timed_op ldw (0x10,SP),X
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timed_op ldw [0x10],X
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timed_op ldw [0x1000],X
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timed_op ldw ([0x10],X),Y
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timed_op ldw ([0x1000],X),Y
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timed_class_1 sla
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timed_class_xy slaw
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timed_class_1 sll
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timed_class_xy sllw
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timed_class_1 sra
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timed_class_xy sraw
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timed_class_1 srl
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timed_class_xy srlw
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timed_class_2 sub
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timed_class_sp_imm sub
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timed_class_1 swap
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timed_class_xy swapw
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timed_class_1 tnz
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timed_class_xy tnzw
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;trap
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;wfe
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;wfi
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timed_class_2 xor
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dividend = 0x8000
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.rept 15
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timed_div dividend,0x02
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dividend = dividend >> 1
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.endm
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dividend = 0x10000
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.rept 15
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timed_div dividend-1,0x02
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dividend = dividend >> 1
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.endm
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timed_div 0x2000 0x02
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timed_div 0x2040 0x02
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timed_div 0x2048 0x02
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timed_div 0x2148 0x02
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timed_div 0x21c8 0x02
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timed_div 45831 94
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end:
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||||
halt
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||||
.area _DATA
|
||||
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