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Dennis Gunia
2024-06-24 20:38:02 +02:00
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commit 1ed6034d99
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SDCC Binary Kit Install Help
----------------------------
For Linux users:
================
To install:
* Extract the binary kit to a temporary directory.
This will create a new directory called 'sdcc-4.2.0' in the temporary directory.
cd ~
mkdir tmp
cd tmp
tar xjf path/to/binary/kit/sdcc-4.2.0-i386-unknown-linux2.5.tar.bz2
* Change to the sdcc directory and copy all files to /usr/local
cd sdcc-4.2.0
cp -r * /usr/local
This will install sdcc binaries into: /usr/local/bin/
header files into: /usr/local/share/sdcc/include/
non-free header files into: /usr/local/share/sdcc/non-free/include/
library files into: /usr/local/share/sdcc/lib/
non-free library files into: /usr/local/share/sdcc/non-free/lib/
and documentation into: /usr/local/share/sdcc/doc/
You can test the install by entering:
/usr/local/bin/sdcc -v
This should return sdcc's version number.
Even if the default search paths look into /usr/local, sdcc is fully
relocatable. Try `sdcc --print-search-dirs` if you have problems with header
or library files. See sdccman.pdf for more detailed information.
For Windows 9X/NT/2000/XP/Vista/7/8 users:
==========================================
To install:
* If you would like to keep a copy of your previous version,
rename the directory where it's installed first
* Run sdcc-4.2.0-setup.exe for 32 bit Windows or
Run sdcc-4.2.0-x64-setup.exe for 64 bit Windows
By default this will install sdcc binaries into: C:\Program Files\SDCC\bin\
header files into: C:\Program Files\SDCC\include\
non-free header files into: C:\Program Files\SDCC\non-free\include\
library files into: C:\Program Files\SDCC\lib\
non-free library files into: C:\Program Files\SDCC\non-free\lib\
and documentation into: C:\Program Files\SDCC\doc\
You can test the install by opening a DOS box and entering:
sdcc -v
This should return sdcc's version number.
sdcc for windows is fully relocatable. Try `sdcc --print-search-dirs` if you
have problems with header or library files. See sdccman.pdf for more
detailed information.
For Mac OS X users:
===================
To install:
* Extract the binary kit to a temporary directory.
This will create a new directory called 'sdcc-4.2.0' in the temporary directory.
cd ~
mkdir tmp
cd tmp
tar xjf path/to/binary/kit/sdcc-4.2.0-x86_64-apple-macosx.tar.bz2
* Change to the sdcc directory and copy all files to /Developer/sdcc
cp -r sdcc /Developer/sdcc
This will install sdcc binaries into: /Developer/sdcc/bin/
header files into: /Developer/sdcc/share/sdcc/include/
non-free header files into: /Developer/sdcc/share/sdcc/non-free/include/
library files into: /Developer/sdcc/share/sdcc/lib/
non-free library files into: /Developer/sdcc/share/sdcc/non-free/lib/
and documentation into: /Developer/sdcc/share/sdcc/doc/
You can test the install by entering:
/Developer/sdcc/bin/sdcc -v
This should return sdcc's version number.
Even if the default search paths look into /usr/local, sdcc is fully
relocatable. Try `sdcc --print-search-dirs` if you have problems with header
or library files. See sdccman.pdf for more detailed information.

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SDCC - free open source, retargettable, optimizing ANSI-C compiler
------------------------------------------------------------------
Welcome to SDCC, free open source, retargettable, optimizing ANSI C
compiler suite that targets a growing list of processors including the
Intel MCS-51 based microprocessors (8031, 8032, 8051, 8052, etc.), Maxim
(formerly Dallas) DS80C390 variants, Freescale (formerly Motorola) HC08
based (hc08, s08), Zilog Z80 based MCUs (Z80, Z80N, Z180, SM83 (e.g. Game Boy),
Rabbit 2000, Rabbit 2000A/3000, Rabbit 3000A, TLCS-90), STMicroelectronics STM8
and Padauk PDK14 and PDk15.
Work is in progress on supporting the Padauk PDK13 and MOS 6502 targets.
There are unmaintained Microchip PIC16 and PIC18 targets.
It can be retargeted for other microprocessors.
See share/sdcc/doc/INSTALL.txt for the installation instructions for
the binary kits.
See the share/sdcc/doc directory for more documentation.
See http://sdcc.sourceforge.net/ for the latest information on sdcc.
Licenses:
~~~~~~~~~
SDCC compiler suite is a collection of several components derived from
different sources with different FOSS licenses. See the sdccman.pdf
document, chapter "SDCC Suite Licenses" for details.
The code or object files generated by SDCC suite are not licensed, so
they can be used in FLOSS or proprietary (closed source) applications.
The great majority of sdcc run-time libraries are licensed under the
GPLv2+LE which allows linking of sdcc run time libraries with
proprietary (closed source) applications.
Exception are pic device libraries and header files which are derived
from Microchip header (.inc) and linker script (.lkr) files. Microchip
requires that "The header files should state that they are only to be
used with authentic Microchip devices" which makes them incompatible
with the GPL. Pic device libraries and header files are located at
non-free/lib and non-free/include directories respectively. Sdcc should
be run with the --use-non-free command line option in order to include
the potentially non-free header files and libraries.
However: Many think that the Microchip requirement is not legally enforceable,
arguing that the header files only contain noncopyrightable facts.
See:
http://www.gnu.org/copyleft/gpl.html
http://sourceforge.net/apps/trac/sdcc/wiki/SDCC%20Library%20Licenses
Support:
~~~~~~~~
SDCC compiler suite is a collaborative effort between a group of
volunteers. Please feel free to report bugs via the Sourceforge bug
tracker, or to ask questions on the user mailing list. See:
http://sourceforge.net/tracker/?atid=100599&group_id=599&func=browse
http://sourceforge.net/mail/?group_id=599
Notes:
* The ds400, pic14 and pic16 are currently experimental, but work is in
progress. Please check http://sdcc.sourceforge.net/snap.php for snapshots.
* The TININative, avr and xa51 targets are no longer maintained.
Roadmap:
~~~~~~~~
COPYING - GPL v2
debugger/ - sdcdb debugger
device/ - Device libraries and examples
doc/ - sdcc and target specific documentation
sdas/ - Assemblers and linkers, derived from asxxxx
sim/ - ucsim simulator
src/ - Source to the C compiler and targets
support/ - Libraries and apps that may not be provided by your system.
Authors and interested persons:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Sandeep Dutta (sandeep AT users.sourceforge.net)
* Jean Loius-VERN <jlvern AT writeme.com>
* Daniel Drotos <drdani AT mazsola.iit.uni-miskolc.hu>
* Kevin Vigor <kevin AT vigor.nu>
* Johan Knol <johan.knol AT iduna.nl>
* Scott Dattalo <scott AT dattalo.com>
* Karl Bongers <karl AT turbobit.com>
* Bernhard Held <bernhard AT bernhardheld.de>
* Frieder Ferlemann <frieder.ferlemann AT web.de>
* Jesus Calvino-Fraga <jesusc AT ece.ubc.ca>
* Borut Razem <borut.razem AT siol.net>
* Vangelis Rokas <vrokas AT otenet.gr>
* Erik Petrich <epetrich AT ivorytower.norman.ok.us>
* Paul Stoffregen <paul AT pjrc.com>
* Michael Hope <michaelh AT juju.net.nz> <nz_michaelh AT yahoo.com>
* Maarten Brock <sourceforge.brock AT dse.nl>
* Raphael Neider <RNeider AT web.de>
* Hans-Juergen Dorn <hans.dorn AT apl-landau.de>
* Klaus Flittner <klaus_flittner AT gmx.de>
* Philipp Klaus Krause <pkk AT spth.de>
* Leland Morrison <enigmalee.AT.sourceforget.net>
* Molnar Karoly <molnarkaroly AT users.sf.net>
* Ben Shi <powerstudio1st AT 163.com>
SDCC includes code from:
* Alan Baldwin <baldwin AT shop-pdp.kent.edu>
Initial version of ASXXXX and ASLINK.
* John Hartman <noice AT noicedebugger.com>
Porting ASXXXX and ASLINK for 8051.
* Dmitry S. Obukhov <dso AT usa.net>
malloc and serial I/O routines.
* Pascal Felber
Some of the Z80 related files are borrowed from the Gameboy
Development Kit (GBDK).
* The GCC development team http://gcc.gnu.org/
for GNU C preprocessor, the basis of sdcpp preprocessor and
gcc test suite, partially included into the SDCC regression test suite
* The GNU Binutils development team http://www.gnu.org/software/binutils/
for GNU Binutils, the basis of sdbinutils
* Boost Community http://www.boost.org/
for Boost C++ libraries used in sdcc compiler
* Timo Bingmann http://idlebox.net/2007/stx-btree/
for TX B+ Tree C++ Template Classes used in sdcc compiler
* Malini Dutta <malini AT mediaone.net>
Sandeep's wife, for her patience and support.

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<html>
<head>
<meta content="text/html; charset=ISO-8859-2" http-equiv="content-type">
<title>&mu;Csim: Code Analyser</title>
</head>
<body bgcolor="white">
<h1>Code analyser</h1>
<p>The code analyser analyses the memory of the simulated microprocessor and
tries to figure out which address contains valid instruction.</p>
<p>The analyser starts from the known hardware vectors (reset, IRQs etc.)
and follows the possible execution paths through jumps, branches and
calls marking data as code and adding variables as necessary. Execution
paths that are indirect, indexed or otherwise computed are not followed
initially but will be analysed when, or if, execution reaches them.</p>
<p>If code is known to exist elsewhere in memory and is not reachable
without being run explicitly (such as by the "<code>run <i>addr</i></code>"
command) you can use "<code>analyse <i>addr</i></code>" to ask the analyser
to look there. This is not persistent however. Whenever data is loaded
or "<code>analyse</code>" run with no <i>addr</i> argument all the analyser
state is reset and recreated from the known vectors so any explicit
"<code>analyse <i>addr</i></code>" needs to be rerun if required.</p>
<p>Variables created by the analyser always start with a dot. Such variables
cannot be created by the "<code>var</code>" command and are not listed by
"<code>info var</code>" (although can be using "<code>info var .</code>") but
otherwise work like any other variable with one exception. If you create
a new variable for the exact same memory location the analyser's variable
will be silently removed.</p>
<pre>0&gt; <font color="#118811">dump .loop$21</font>
0x081f8 &lt;.loop$21&gt;:
0x081f8 d6 81 da ld A,(0x81da &lt;.bit0_isset$19&gt;,X)
0x081fb d7 00 3d ld (0x003d,X),A
0x081fe 5a decw X
0x081ff 26 f7 jrne 0x81f8 &lt;.loop$21&gt;
0&gt; <font color="#118811">var copy_data .loop$21</font>
0&gt; <font color="#118811">dump .loop$21</font>
dump [/format] memory_type [start [stop [bytes_per_line]]] | dump bit...
Dump memory of specified type or bit(s)
0&gt; <font color="#118811">dump copy_data</font>
0x081f8 &lt;copy_data&gt;:
0x081f8 d6 81 da ld A,(0x81da &lt;.bit0_isset$19&gt;,X)
0x081fb d7 00 3d ld (0x003d,X),A
0x081fe 5a decw X
0x081ff 26 f7 jrne 0x81f8 &lt;copy_data&gt;
</pre>
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>Commands of μCsim</title>
</head>
<body style="background-color: white;">
<h1>Command reference of <i>&#956;Csim</i></h1>
<!--GENERAL--> <a href="cmd_general.html">General commands and information</a>
<ul>
<li><a href="cmd_general.html#analyse"><b>analyse</b> Analyse code</a></li>
<li><a href="cmd_general.html#conf"><b>conf</b> Configuration</a>
<ul>
<li><a href="cmd_general.html#conf_objects"><b>conf objects</b></a></li>
</ul>
</li>
<li><a href="cmd_general.html#version"><b>version</b> Print version of the
program</a></li>
<li><a href="cmd_general.html#h"><b>help,?</b> Help about commands</a></li>
<li><a href="cmd_general.html#q"><b>quit</b> Quit</a></li>
<li><a href="cmd_general.html#kill"><b>kill</b> Shut down the simulator</a></li>
<li><a href="cmd_general.html#exec"><b>exec</b> Execute commands from file</a></li>
<li><a href="cmd_general.html#expression"><b>expression</b> Compute value
of an expression</a></li>
<li><a href="cmd_general.html#show"><b>show</b> Show different kind of
information</a>
<ul>
<li><a href="cmd_general.html#show_copying"><b>show copying</b></a> </li>
<li><a href="cmd_general.html#show_warranty"><b>show warranty</b></a>
</li>
<li><a href="cmd_general.html#show_option"><b>show option</b></a></li>
<li><a href="cmd_general.html#show_error"><b>show error</b></a></li>
</ul>
</li>
<li><a href="cmd_general.html#get"><b>get</b> Get various things</a>
<ul>
<li><b><a href="cmd_general.html#get_option">get option</a></b> </li>
<li><b><a href="cmd_general.html#get_sfr">get sfr</a></b> </li>
<li><b><a href="cmd_general.html#get_error">get error</a></b></li>
</ul>
</li>
<li><a href="cmd_general.html#set"><b>set</b> Set various things</a>
<ul>
<li><a href="cmd_general.html#set_option"><b>set option</b></a></li>
<li><a href="cmd_general.html#set_error"><b>set error</b></a></li>
<li><a href="cmd_general.html#set_console"><b>set console</b></a></li>
<li><a href="cmd_general.html#set_memory"><b>set memory</b></a> </li>
<li><a href="cmd_general.html#set_bit"><b>set bit</b></a> </li>
<li><a href="cmd_general.html#set_hardware"><b>set hardware</b></a></li>
</ul>
</li>
<li><a href="cmd_general.html#state"><b>state</b> State of simulator</a> </li>
<li><a href="cmd_general.html#reset"><b>reset</b> Reset </a></li>
<li><a href="cmd_general.html#info"><b>info</b> Information</a>
<ul>
<li><a href="cmd_general.html#info_breakpoints"><b>info breakpoints</b></a>
</li>
<li><a href="cmd_general.html#info_registers"><b>info registers</b></a>
</li>
<li><a href="cmd_general.html#info_hardware"><b>info hardware</b></a>
</li>
<!--li><a href="cmd_general.html#info_stack"><b>info stack</b></a>
(<font color="#ff2211">since 0.5.0</font>) </li-->
<li><a href="cmd_general.html#info_memory"><b>info memory</b></a></li>
<li><a href="cmd_general.html#info_variables"><b>info variables</b></a></li>
<li><a href="cmd_general.html#info_history"><b>info history</b></a></li>
</ul>
</li>
<li><a href="cmd_general.html#timer"><b>timer</b> Managing timers to
measure execution time and profiling</a>
<ul>
<li><a href="cmd_general.html#timer_add"><b>timer add</b></a> </li>
<li><a href="cmd_general.html#timer_delete"><b>timer delete</b></a> </li>
<li><a href="cmd_general.html#timer_get"><b>timer get</b></a> </li>
<li><a href="cmd_general.html#timer_start"><b>timer start</b></a> </li>
<li><a href="cmd_general.html#timer_stop"><b>timer stop</b></a> </li>
<li><a href="cmd_general.html#timer_set"><b>timer set</b></a> </li>
</ul>
</li>
</ul>
<!--MEMORY--> <a href="cmd_memory.html">Memory manipulation</a>
<ul>
<li><a href="cmd_memory.html#file"><b>file,load</b> Load FILE into ROM</a>
</li>
<li><a href="cmd_memory.html#dl"><b>download,dl</b> Download (intel hex)
data into ROM</a> </li>
<li><a href="cmd_memory.html#fill"><b>fill</b> Fill memory region with
data</a></li>
<li><a href="cmd_memory.html#where"><b>where,Where</b> Search for data in
memory</a></li>
<li><a href="cmd_memory.html#hole"><b>hole</b> search area in memory,
filled with value </a></li>
<li><a href="cmd_memory.html#memory"><b>memory</b> Manage address spaces,
memory chips and address decoders</a>
<ul>
<li><b>memory create</b></li>
<ul>
<li><a href="cmd_memory.html#memory_createchip"><b>memory create chip</b></a></li>
</ul>
<ul>
<li><a href="cmd_memory.html#memory_createaddressspace"><b>memory
create addressspace</b></a></li>
<li><a href="cmd_memory.html#memory_createaddressdecoder"><b>memory
create addressdecoder</b></a></li>
<li><b>memory create banker</b></li>
<li><b>memory create bank</b></li>
<li><b>memory create bander</b></li>
</ul>
<li>memory remove</li>
<ul>
<li><a href="cmd_memory.html#memory_remove_chip">memory remove chip</a>
</ul>
</ul>
<ul>
<li><a href="cmd_memory.html#memory_info"><b>memory info</b></a></li>
<li><b>memory cell</b></li>
</ul>
<ul>
</ul>
<ul>
<ul>
</ul>
</ul>
</li>
<li><b><a href="cmd_memory.html#var">var</a></b></li>
</ul>
<!--EXEC--> <a href="cmd_exec.html">Execution</a>
<ul>
<li><a href="cmd_exec.html#run"><b>r,run,go</b> Go</a></li>
<li><a href="cmd_exec.html#stop"><b>stop</b> Stop</a></li>
<li><a href="cmd_exec.html#step"><b>s,step</b> Step</a></li>
<li><a href="cmd_exec.html#n"><b>n,next</b> Next</a> </li>
<li><a href="cmd_exec.html#pc"><b>pc</b> Set/get PC</a></li>
<li><a href="cmd_exec.html#history"><b>history</b> Print and manage execution history</a>
<ul><li><a href="cmd_exec.html#history_">history</a></li>
<li><a href="cmd_exec.html#history_info">history information</a></li>
<li><a href="cmd_exec.html#history_list">history list</a></li>
<li><a href="cmd_exec.html#history_clear">history clear</a></li>
</ul>
</li>
</ul>
<!--BREAKPOINT--> <a href="cmd_bp.html">Breakpoints</a>
<ul>
<li><a href="cmd_bp.html#break"><b>break</b> Set fix breakpoint</a></li>
<li><a href="cmd_bp.html#tbreak"><b>tbreak</b> Set temporary breakpoint</a></li>
<li><a href="cmd_bp.html#clear"><b>clear</b> Clear fix breakpoint</a> </li>
<li><a href="cmd_bp.html#delete"><b>delete</b> Delete breakpoint(s)</a></li>
<li><a href="cmd_bp.html#commands"><b>commands</b> Define breakpoint
script</a></li>
<li><a href="cmd_bp.html#display"><b>display</b> Set expression to show on breakpoint</a></li>
<li><a href="cmd_bp.html#undisplay"><b>undisplay</b> Remove display expression</a></li>
</ul>
<!--DUMP--> <a href="cmd_dump.html">Dump commands</a>
<ul>
<li><a href="cmd_dump.html#dump"><b>dump</b> Dump memory or bits</a></li>
<li><a href="cmd_dump.html#disassemble"><b>disassemble</b> Disassemble</a>
</li>
<li><a href="cmd_dump.html#dc"><b>dc</b> Dump code in disass format</a> </li>
<li><a href="cmd_dump.html#dch"><b>dch</b> Dump code in hex format</a> </li>
<li><a href="cmd_dump.html#di"><b>di</b> Dump Internal RAM</a> </li>
<li><a href="cmd_dump.html#dx"><b>dx</b> Dump External RAM</a> </li>
<li><a href="cmd_dump.html#ds"><b>ds</b> Dump SFR</a> </li>
</ul>
<!--REMOVED--> <a href="cmd_removed.html">Removed obsolete commands</a>
<ul>
<li><a href="cmd_removed.html#wi">wi,Wi</a> Search for string in Internal
RAM (use <a href="cmd_memory.html#where">where,Where</a> instead) </li>
<li><a href="cmd_removed.html#wx">wx,Wx</a> Search for string in External
RAM (use <a href="cmd_memory.html#where">where,Where</a> instead) </li>
<li><a href="cmd_removed.html#wc">wc,Wc</a> Search for string in ROM (use
<a href="cmd_memory.html#where">where,Where</a> instead) </li>
<li><a href="cmd_removed.html#gopt">gopt</a> Get value of option(s) (use <a
href="cmd_general.html#get_option">get option</a> instead) </li>
<li><a href="cmd_removed.html#sopt">sopt</a> Set value of option (use <a
href="cmd_general.html#set_option">set option</a> instead) </li>
<li><a href="cmd_removed.html#g">g Go</a> (use <a href="cmd_exec.html#run">run</a>
instead) </li>
<li>bs Set FETCH Breakpoint (use <a href="cmd_bp.html#break">break</a> or
<a href="cmd_bp.html#tbreak">tbreak</a> instead) </li>
<li><a href="cmd_removed.html#bse">bse</a> Set EVENT Breakpoint (use <a href="cmd_bp.html#break">break</a>
or <a href="cmd_bp.html#tbreak">tbreak</a> instead) </li>
<li>bd Delete FETCH Breakpoint (use <a href="cmd_bp.html#clear">clear</a>
instead) </li>
<li><a href="cmd_removed.html#bde">bde</a> Delete EVENT Breakpoint (use <a
href="cmd_bp.html#delete">delete</a> instead) </li>
<li><a href="cmd_removed.html#ba">ba</a> Delete all breakpoints (use <a href="cmd_bp.html#delete">delete</a>
instead) </li>
<li>bl List Breakpoints (use <a href="cmd_bp.html#info">info breakpoints</a>
instead) </li>
<li>dr Dump registers (use <a href="cmd_general.html#info_reg">info
registers</a> instead) </li>
<li><a href="cmd_removed.html#dp">dp</a> Dump ports (use <a href="cmd_general.html#info_hw">info
hardware</a> instead) </li>
<li><a href="cmd_removed.html#si">si</a> Set Internal RAM (use <a href="cmd_general.html#set_mem">set
memory</a> instead) </li>
<li><a href="cmd_removed.html#sx">sx</a> Set External RAM (use <a href="cmd_general.html#set_mem">set
memory</a> instead) </li>
<li><a href="cmd_removed.html#sc">sc</a> Set code (ROM) (use <a href="cmd_general.html#set_mem">set
memory</a> instead) </li>
<li><a href="cmd_removed.html#ss">ss</a> Set SFR area (use <a href="cmd_general.html#set_mem">set
memory</a> instead) </li>
<li><a href="cmd_removed.html#sb">sb</a> Set bit (use <a href="cmd_general.html#set_bit">set
bit</a> instead) </li>
<li><a href="cmd_removed.html#fi">fi</a> Fill IRAM area with data (use <a
href="cmd_memory.html#fill">fill</a> instead) </li>
<li><a href="cmd_removed.html#fx">fx</a> Fill XRAM area with data (use <a
href="cmd_memory.html#fill">fill</a> instead) </li>
<li><a href="cmd_removed.html#fs">fs</a> Fill SFR area with data (use <a
href="cmd_memory.html#fill">fill</a> instead) </li>
<li><a href="cmd_removed.html#fc">fc</a> Fill ROM area with data (use <a
href="cmd_memory.html#fill">fill</a> instead) </li>
<li><a href="cmd_removed.html#db">db</a> Dump bit (use <a href="cmd_general.html#dump">dump</a>
instead) </li>
<li><a href="cmd_removed.html#sp">sp</a> Set port pins (use <a href="cmd_general.html#set_port">set
port</a> instead) </li>
</ul>
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>Breakpoints commands of &#956;Csim</title>
</head>
<body style=" background-color: white;">
<!-- BREAKPOINTS -->
<h2>Commands of <i>&#956;Csim</i> to manage breakpoints</h2>
Two kind of breakpoint can be used: fetch and event breakpoint. <b>Fetch</b>
breakpoints are classical breakpoints. They can be placed at any instruction
in the code memory. Breakpoint will be hit if CPU fetches instruction code
from the memory location specified by the breakpoint. Only fetching of first
byte of the instruction hits the breakpoint. If the execution reaches a
breakpoint it stops <i>before</i> the instruction at location specified by
the breakpoint would be executed.
<p><b>Event</b> breakpoints are special onces. They cause stop of execution
if event specified by the breakpoint occurs. Event can be a read or a
write operation on any address space location. Event breakpoint stops
execution <i>after</i> specified event occurred. </p>
<p>Every breakpoint can be <b>fix</b> (permanent) or <b>dynamic</b>
(temporary). Dynamic breakpoints are automatically removed when they
reached. Some commands place dynamic fetch breakpoints into the code, for
example <a href="#g"><b>go</b></a> or <a href="#n"><b>next</b></a>. </p>
<p>A <b>hit number</b> can be associated to any breakpoint. This hit number
specifies how many times the breakpoint must be hit before it causes the
execution to stop. This hit number is 1 by default. </p>
<hr>
<!-- ----------------------------------------------------------------- -->
<a name="break">
<h3>break <i>addr [hit] [if expression]</i> <br>
break <i>memory_type r|w addr [hit] [if expression]<br>
</i></h3>
</a>
<a name="tbreak">
<h3>tbreak<i> addr [hit] [if expression]</i> <br>
tbreak <i>memory_type r|w addr [hit] [if expression]<br>
</i></h3>
</a>
Set fetch or event breakpoint. The command specifies if the breakpoint
will be fix (<b>break</b>) or dynamic (temporary) (<b>tbreak</b>).
<p>Fetch or event breakpoint can be defined. First form defines fetch while
second form defines event breakpoint. </p>
<dl>
<dt>Fetch breakpoint </dt>
<dd>First parameter specifies address where the breakpoint must be placed
to. It should be address of an instruction. <br>
Second parameter is optional and it specifies the hit number. It is 1 by
default. </dd>
<dt>Event breakpoint </dt>
<dd>First parameter specifies class name of memory where we are going to
watch for en event. Class names of memories can be checked by <a href="cmd_general.html#info_memory">info
memory</a> command. <br>
Second parameter specifies the event. It can be <b>r</b> to specify <b>read</b>
operation or <b>w</b> which means <b>write</b> operation. <br>
Remaining parameters are address of watched memory location and an
optional hit number (1 by default). </dd>
</dl>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">dc 0 0x10</font>
000000 02 01 60 LJMP 0160
* 000003 02 00 3c LJMP 003c
* 000006 ff MOV R7,A
* 000007 ff MOV R7,A
* 000008 ff MOV R7,A
* 000009 ff MOV R7,A
* 00000a ff MOV R7,A
* 00000b 02 3b e0 LJMP 3be0
* 00000e ff MOV R7,A
* 00000f ff MOV R7,A
* 000010 ff MOV R7,A
&gt; <font color="#118811">break 0x160</font>
Breakpoint 1 at 0x000160: CLR P1.0
&gt; <font color="#118811">tbreak 8 2</font>
Breakpoint 2 at 0x000008: MOV R7,A
&gt; <font color="#118811">g</font>
Simulation started, PC=0x000000
Stop at 000160: (4) Breakpoint
F 000160
&gt; </pre>
Breakpoint hits can be made more noticeable by printing a beep character on
the console. This function can be turned on by <a href="cmd_general.html#set_option">setting
the option</a> <b>beep_break</b> (FALSE by default).<br>
<hr>
<!-- ----------------------------------------------------------------- -->
<a name="clear">
<h3>clear <i>[addr...]</i></h3>
</a>
Delete fetch breakpoint. Parameter specifies address of breakpoint. If
there is no breakpoint specified at given address this command prints out a
warning message.
<p>If parameter is not given then breakpoint at current PC will be deleted
if it exists. If more than one address is specified then all breakpoints
at specified addresses will be deleted. </p>
<pre>&gt; <font color="#118811">i b</font>
Num Type Disp Hit Cnt Address What
1 fetch keep 1 1 0x000160 CLR P1.0
2 fetch del 1 1 0x000180 LJMP 022a
1 event keep 1 1 0x000006 wi
&gt; <font color="#118811">clear 160</font>
No breakpoint at 0000a0
&gt; <font color="#118811">clear 0x160</font>
&gt; <font color="#118811">i b</font>
Num Type Disp Hit Cnt Address What
2 fetch del 1 1 0x000180 LJMP 022a
1 event keep 1 1 0x000006 wi
&gt; </pre>
<hr>
<!-- ----------------------------------------------------------------- -->
<a name="delete">
<h3>delete <i>[number...]</i></h3>
</a>
Delete breakpoint(s) by its number.
<p>If parameter is not used then all breakpoints are deleted. </p>
<hr>
<!-- ----------------------------------------------------------------- -->
<a name="commands">
<h3>commands <i>[breakpoint-nr] script</i></h3>
</a>
<p>Attach a script to a breakpoint. Breakpoint number can
be omitted if only one breakpoint exists. Breakpoint numbers can be
checked by <a href="cmd_general.html#info_breakpoints">info
breakpoint</a> command. Script is command or a list of commands
separated by ; character. It will be executed when the specified
breakpoint is hit. If the text of the script is printed before execution
is controlled by the option <b>echo_script</b>, which is FALSE by
default. See <a href="cmd_general.html#set_option">set option</a> command
how to set it.</p>
<hr>
<!-- ----------------------------------------------------------------- -->
<a name="display">
<h3>display <i>[[/format] expr]</i></h3>
</a>
Set expression to be displayed when simulation stops on a
breakpoint.
<p><i>/format</i> option can be used to specify print format for the
expression. For meaning of the options, see <a href="cmd_general.html#expression">expression</a> command.</p>
<p>If no <i>expr</i> argument is given, all defined expressions
are listed and evaluated and values are printed.</p>
<pre>0&gt; <font color="#118811">disp R7</font>
0&gt; <font color="#118811">disp ACC</font>
0&gt; <font color="#118811">b 0x10</font>
Breakpoint 1 at 0x000010 (cond="")
0x0010 F? ff MOV R7,A
0&gt; <font color="#118811">display</font>
1: R7 = 107
2: ACC = 0
0&gt; <font color="#118811">run</font>
Simulation started, PC=0x000000
Stop at 0x000010: (104) Breakpoint
R0 R1 R2 R3 R4 R5 R6 R7
41 58 fc c9 8b bc 95 00
@R0 76 v ACC= 0x00 0 . B= 0x00
@R1 73 s PSW= 0x00 CY=0 AC=0 OV=0 P=0
SP 0x07 -> 00 95 bc 8b c9 fc 58 41
DPTR= 0x0000 @DPTR= 0x83 131 .
0x0010 F ff MOV R7,A
F 0x000010
Simulated 192 ticks (1.736e-05 sec)
Host usage: 0.007306 sec, rate=0.002376
1: R7 = 0
2: ACC = 0
0&gt;
</pre>
<hr>
<!-- ----------------------------------------------------------------- -->
<a name="undisplay">
<h3>undisplay <i>[nr]</i></h3>
</a>
Remove selected, or all (if no <i>nr</i> argument is specified)
expression from display list. To check out id number of an
expression, use <a href="#display">display</a> command without arguments.
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>Dump commands of &#956;Csim</title>
</head>
<body style="background-color: white;">
<h2>Dump commands of &#956;Csim</h2>
<a name="dump">
<h3>dump <i>[/format] memory_type [start [end [bytes_per_line]]]</i>
<br>
dump <i>bit...</i></h3>
</a>
The first form can be used get the contents of memory while the second form can be
used to check the value of one or more bits.
<blockquote>
<a name="dump_memory">
<h4>dump <i>[/format] memory_name [start [end
[bytes_per_line]]]</i></h4>
</a>
Dump a memory region.
<p>The optional <b>/format</b> specifies how memory is to be dumped.
<dl>
<dt><b>/b</b> - binary</dt>
<dd>Dumps raw binary data. The output MUST be redirected to a file.</dd>
<dt><b>/h</b> - hexadecimal</dt>
<dd>Dumps data in a tabular hexadecimal format with an accompanying
table of equivalent characters to the right.</dd>
<dt><b>/i</b> - ihex</dt>
<dd>Dumps data in ihex format.</dd>
<dt><b>/s</b> - string</dt>
<dd>Dumps a single, null terminated string starting at <b>start</b>.</dd>
</dl>
If no <b>format</b> is given dump uses a "smart" mode. This will disassemble
where the <a href="analyzer.html"> code analyzer</a> has identified executable
code otherwise it is similar to
the hexadecimal format except that where labels (vars that name an address)
are found they are shown between the address and data and where HW
registers (vars that name an address AND specify the full bit range)
are found that address is shown on a line of its own and the data is
given as binary, character, hex, unsigned decimal and, if the high bit
is set, signed decimal. Note that smart mode only applies if
<b>memory_name</b> is an address space since vars can only be set for
cells within an address space. If <b>memory_name</b> is a chip the
output is the same as hexadecimal (<b>/h</b>) output.
</p>
<p><b>memory_name</b> specifies
memory. It can be the name of an address space or a chip, and can be
checked using <a href="cmd_general.html#info_memory">info memory</a>
command which lists size and name of all available memories.
</p>
<p><b>start</b> and <b>end</b> parameters can be used to specify the
first and last address of the dumped region. If <b>end</b> is omitted
then 64 memory locations are dumped. If both <b>start</b> and <b>end</b>
are omitted then the next 64 memory locations will be dumped out. Every
time when dump command is used the address of the last dumped memory
location is stored and next dump command automatically continues at
the next address.
</p>
<p><b>bytes_per_line</b> can be used to specify how many memory locations
should be dumped out in one line. It is 8 by default.
</p>
<pre>$ <font color="#118811">ucsim_51</font>
uCsim 0.6-pre34, Copyright (C) 1997 Daniel Drotos.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">dump regs</font>
regs[0x0] R0 0b00001000 0x08 '.' 8
regs[0x1] R1 0b01110000 0x70 'p' 112
regs[0x2] R2 0b11010100 0xd4 '.' 212 (212)
regs[0x3] R3 0b10110010 0xb2 '.' 178 (178)
regs[0x4] R4 0b10001010 0x8a '.' 138 (138)
regs[0x5] R5 0b00101001 0x29 ')' 41
regs[0x6] R6 0b01010100 0x54 'T' 84
regs[0x7] R7 0b01001000 0x48 'H' 72
&gt; <font color="#118811">dump rom 0</font>
0x0000 00 00 00 00 00 00 00 00 ........
0x0008 00 00 00 00 00 00 00 00 ........
0x0010 00 00 00 00 00 00 00 00 ........
0x0018 00 00 00 00 00 00 00 00 ........
0x0020 00 00 00 00 00 00 00 00 ........
0x0028 00 00 00 00 00 00 00 00 ........
0x0030 00 00 00 00 00 00 00 00 ........
0x0038 00 00 00 00 00 00 00 00 ........
0x0040 00 00 00 00 00 00 00 00 ........
0x0048 00 00 00 00 00 00 00 00 ........
&gt; <font color="#118811">var label1 rom 0x0016</font>
&gt; <font color="#118811">var reg1 rom[0x0020][7:0]</font>
&gt; <font color="#118811">var reg2 rom[0x0021][7:0]</font>
&gt; <font color="#118811">dump rom 0</font>
0x0000 00 00 00 00 00 00 00 00 ........
0x0008 00 00 00 00 00 00 00 00 ........
0x0010 00 00 00 00 00 00 ......
0x0016 label1 00 00 00 00 00 00 00 00 ........
0x001e 00 00 ..
0x0020 reg1 0b00000000 0x00 '.' 0
0x0021 reg2 0b00000000 0x00 '.' 0
0x0022 00 00 00 00 00 00 00 00 ........
0x002a 00 00 00 00 00 00 00 00 ........
0x0032 00 00 00 00 00 00 00 00 ........
0x003a 00 00 00 00 00 00 00 00 ........
0x0042 00 00 00 00 00 00 00 00 ........
0x004a 00 00 00 00 00 00 ......
&gt;
</pre>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; 55470 words read from remo.hex
55470 words read from remo.hex
&gt; <font color="#118811">run</font>
Simulation started, PC=0x000000
Stop at 0x000515: (105) User stopped
F 0x000515
&gt; <font color="#118811">du rom 20</font>
0x0014 00 ac ff ff ff ff ff ff ........
0x001c ff ff ff ff ff ff ff 02 ........
0x0024 01 1c ff ff ff ff ff 32 .......2
0x002c ff ff ff ff 02 0f a7 02 ........
0x0034 0e 9c 02 0d d2 02 08 41 .......A
0x003c c0 82 c0 83 c0 d0 c0 e0 ........
0x0044 c0 00 a2 90 c0 d0 c2 90 ........
0x004c 78 18 06 30 03 4b 20 92 x..0.K .
0x0054 48 30 07 05 c2 07 02 00 H0......
0x005c 9d 30 08 05 20 93 3a c2 .0.. .:.
&gt; <font color="#118811">du xram 10 20 10</font>
0x000a ff 01 00 fa 01 01 40 01 01 44 ......@..D
0x0014 01 .
&gt; <font color="#118811">du xram</font>
0x0015 00 00 00 00 00 00 00 00 ........
0x001d 00 10 01 00 ae 01 00 ae ........
0x0025 02 12 e1 00 5a 85 00 01 ....Z...
0x002d 00 3b 00 00 5a 85 00 ab .;..Z...
0x0035 1f 80 00 00 01 00 01 00 ........
0x003d fa 0c 02 01 00 fa 00 02 ........
0x0045 00 01 00 ab 00 00 00 00 ........
0x004d 00 00 5a 85 ff 00 01 00 ..Z.....
0x0055 00 00 00 94 a7 01 0c a6 ........
0x005d 00 6f ff 00 00 00 00 00 .o......
&gt;
</pre>
<hr>
<a name="dump_bit">
<h4>dump <i>bit_name...</i></h4>
</a>This command can be used to print out values of bit(s). <a href="syntax.html#bit_param">Any
form of bit address</a> can be used as parameter:
<pre>0&gt; <font color="#118811">dump AC P1.2 0x21</font>
0xd6 AC: 0b0 0x00 '.' 0
0x90.2 0b-----1-- 0x01 '.' 1
0x24.1 0b------0- 0x00 '.' 0
0&gt;
</pre> </blockquote>
<hr> <a name="dch">
<h3>dch <i>[start [stop]]</i></h3>
</a> Hexadecimal dump of code memory area from address <b>start</b> to
address <b>stop</b>. Default value of start address is address of following
memory cell which was dumped by previous <b>dch</b> command. If <b>stop</b>
parameter is not given <b>dch</b> command lists 10 lines 8 bytes per line.
<pre>$ <font color="#118811">ucsim_51 remo.hex</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">wc remo</font>
0013da 52 65 6d 6f Remo
&gt; <font color="#118811">dch 0x13da</font>
0013da 52 65 6d 6f 20 00 56 65 Remo .Ve
0013e2 72 73 69 6f 6e 20 31 2e rsion 1.
0013ea 30 20 00 43 6f 70 79 72 0 .Copyr
0013f2 69 67 68 74 20 28 63 29 ight (c)
0013fa 20 00 31 39 39 34 2c 39 .1994,9
001402 35 20 00 54 61 6c 6b 65 5 .Talke
00140a 72 20 42 74 2e 00 53 75 r Bt..Su
001412 6e 64 61 79 2e 00 4d 6f nday..Mo
00141a 6e 64 61 79 2e 00 54 68 nday..Th
001422 75 65 73 64 61 79 2e 00 uesday..
&gt; </pre>
First element in every lines is address of first byte dumped out in the
line. Next elements are hexadecimal values of bytes followed by ASCII
characters of bytes dumped out in the line. If value of the memory cell is
not printable than a dot is dumped out.
<hr> <a name="dc">
<h3>dc <i>[start [stop]]</i></h3>
</a> Disassembled dump of code memory area. This command simply produces
disassembled list of memory area specified by the parameters. Default value
of <b>start</b> parameter is last address listed by previous <b>dc</b>
command. If <b>stop</b> parameter is not given 20 lines are listed.
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">dc</font>
000000 02 01 60 LJMP 0160
* 000003 02 00 3c LJMP 003c
* 000006 ff MOV R7,A
* 000007 ff MOV R7,A
* 000008 ff MOV R7,A
* 000009 ff MOV R7,A
* 00000a ff MOV R7,A
* 00000b 02 3b e0 LJMP 3be0
* 00000e ff MOV R7,A
* 00000f ff MOV R7,A
* 000010 ff MOV R7,A
* 000011 ff MOV R7,A
* 000012 ff MOV R7,A
* 000013 02 00 ac LJMP 00ac
* 000016 ff MOV R7,A
* 000017 ff MOV R7,A
* 000018 ff MOV R7,A
* 000019 ff MOV R7,A
* 00001a ff MOV R7,A
* 00001b ff MOV R7,A
* 00001c ff MOV R7,A
&gt; </pre>
<hr> <a name="disassemble">
<h3>disassemble <i>[start [offset [lines]]]</i></h3>
</a> Disassemble code. This command can be used to list disassembled
instructions which discovered by the <a href="analyzer.html">code analyser</a>.
First two parameters specify the address where the list starts. First
parameter is address where the command starts to search an instruction. This
search goes forward. When the first instruction marked by code analyzer
found the simulator skips as many instructions as you specify in second
parameter. If <b>offset</b> is negative the simulator goes backward and
skips specified number of instructions. Default value of <b>start</b>
parameter is last address which was listed by previous <b>dis</b> command
and default value of <b>offset</b> is -1. It means you can make continuous
list repeating parameterless <b>dis</b> command.
<p>In third parameter you can specify how many instructions you want to
list. Default value is 20. </p>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">dis</font>
000000 02 01 60 LJMP 0160
000160 c2 90 CLR P1.0
000162 c2 97 CLR P1.7
000164 d2 b5 SETB P3.5
000166 d2 b4 SETB P3.4
000168 75 81 22 MOV SP,#22
00016b 75 d0 00 MOV PSW,#00
00016e 7e 00 MOV R6,#00
000170 7f 00 MOV R7,#00
000172 79 04 MOV R1,#04
000174 12 0d b8 LCALL 0db8
000177 0f INC R7
000178 d9 fa DJNZ R1,0174
00017a 75 0b 00 MOV 0b,#00
00017d 75 0c 00 MOV 0c,#00
000180 02 02 2a LJMP 022a
000183 78 22 MOV R0,#22
000185 76 00 MOV @R0,#00
000187 d8 fc DJNZ R0,0185
&gt; <font color="#118811">br 0x180</font>
&gt; <font color="#118811">tbr 0x189</font>
&gt; <font color="#118811">dis 0x180 -3 10</font>
000178 d9 fa DJNZ R1,0174
00017a 75 0b 00 MOV 0b,#00
00017d 75 0c 00 MOV 0c,#00
F 000180 02 02 2a LJMP 022a
000183 78 22 MOV R0,#22
000185 76 00 MOV @R0,#00
000187 d8 fc DJNZ R0,0185
D 000189 22 RET
00018a 90 09 ec MOV DPTR,#09ec
00018d ae 83 MOV R6,DPH
&gt; </pre>
If there is an <b>F</b> or <b>D</b> character at the beginning of the
line, it means that there is a fix or dynamic fetch breakpoint at listed
address. Next element on the list can be an asterisk (<b>*</b>) which means
that the listed address is not marked by the code analyzer. <b>dis</b>
lists marked instructions only so asterisk never appears in the list. Next
element of the list is address displayed as six digit hexadecimal number.
Address is followed by hexadecimal dump of instruction's code. Last element
of the list is disassembled instruction. Every number appeared on the list
is hexadecimal number.
<hr> <a name="di">
<h3>di <i>[start [stop]]</i></h3>
</a> Hexadecimal dump of <b>iram</b> named address space area from address
<b>start</b> to address <b>stop</b>. Default value of start address is
address of following memory cell which was dumped by previous <b>di</b>
command. If <b>stop</b> parameter is not given <b>di</b> command lists 10
lines 8 bytes per line.
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
0&gt; <font color="#118811">set opt irq_stop 1</font>
0&gt; <font color="#118811">go</font>
Simulation started, PC=0x000000
Stop at 000023: (5) Interrupt
F 000023
0&gt; <font color="#118811">di</font>
000000 18 02 16 ba 00 02 00 0a ........
000008 00 00 00 00 00 00 00 00 ........
000010 00 00 00 00 00 00 00 00 ........
000018 4a 00 00 00 00 00 00 00 J.......
000020 bc 27 06 2d 02 ee 35 8f .'.-..5.
000028 31 e7 42 01 0e 01 0b 00 1.B.....
000030 ec 0b 7f 10 7f a9 7e 08 ......~.
000038 fe 03 09 00 00 00 af 08 ........
000040 af 08 00 00 00 00 00 00 ........
000048 00 00 00 00 00 00 00 00 ........
0&gt;
</pre>
<hr> <a name="dx">
<h3>dx <i>[start [stop]]</i></h3>
</a> Hexadecimal dump of <b>xram</b> named address space area from address
<b>start</b> to address <b>stop</b>. Default value of start address is
address of following memory cell which was dumped by previous <b>dx</b>
command. If <b>stop</b> parameter is not given <b>dx</b> command lists 10
lines 8 bytes per line.
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
0&gt; <font color="#118811">set opt irq_stop 1</font>
0&gt; <font color="#118811">go</font>
Simulation started, PC=0x000000
Stop at 000023: (5) Interrupt
F 000023
0&gt; <font color="#118811">dx 0x100</font>
000100 00 00 00 00 00 00 00 00 ........
000108 00 00 00 00 00 00 00 00 ........
000110 00 00 00 00 00 00 00 00 ........
000118 00 00 00 00 00 00 00 00 ........
000120 00 00 00 00 00 00 00 00 ........
000128 00 00 00 00 00 00 00 44 .......D
000130 61 6e 69 00 00 00 02 02 ani.....
000138 07 00 00 ff 00 00 07 cb ........
000140 08 0c 32 00 07 cb 06 05 ..2.....
000148 02 00 24 00 00 00 00 00 ..$.....
0&gt;
</pre>
<hr> <a name="ds">
<h3>ds <i>[start [stop]]</i></h3>
</a> Hexadecimal dump of <b>sfr</b> named address space area from address <b>start</b>
to address <b>stop</b>. Default value of start address is address of
following memory cell which was dumped by previous <b>ds</b> command. If <b>stop</b>
parameter is not given <b>ds</b> command lists 10 lines 8 bytes per line.
<pre>$ <font color="#118811">ucsim_51 remo.hex</font>
ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
0&gt; <font color="#118811">set opt irq_stop 1</font>
0&gt; <font color="#118811">go</font>
Simulation started, PC=0x000000
Stop at 000023: (5) Interrupt
F 000023
0&gt; <font color="#118811">ds</font>
0x80 ff 2a 1e 13 00 00 00 80 .*......
0x88 d5 21 f7 fd 50 fd 00 00 .!..P...
0x90 fe 00 00 00 00 00 00 00 ........
0x98 7e 0a 00 00 00 00 00 00 ~.......
0xa0 ff 00 00 00 00 00 00 00 ........
0xa8 97 00 00 00 00 00 00 00 ........
0xb0 ff 00 00 00 00 00 00 00 ........
0xb8 15 00 00 00 00 00 00 00 ........
0xc0 00 00 00 00 00 00 00 00 ........
0xc8 00 00 00 00 00 00 00 00 ........
0&gt;
</pre>
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>Execution commands of &#956;Csim</title>
</head>
<body bgcolor="white">
<h2>Execution commands of <i>&#956;Csim</i></h2>
<a name="run">
<h3>r,run,go [start [stop]]</h3>
</a> This command starts the execution of the simulated program.
<p>Parameters are optional. First parameter specifies start address of the
execution. By default execution starts at address specified by actual
value of the PC. This can be overridden by first parameter. </p>
<p>If second parameter is specified it places a dynamic breakpoint at
specified address which stops the execution. If stop address is not given
the simulator stops if it reaches a breakpoint, or the CPU accepts an
interrupt and <b>stopit</b> option is TRUE, or fatal error occurs or <a
href="#stop">stop</a> command is used on an other console, or ENTER key
is pressed on the console where the run command was issued. </p>
<p>If program execution is started the console is <i>frozen</i> it is not
possible to give commands on this console to the simulator while execution
is running. If it is needed to control the simulator during program
execution then more consoles can be used. See using <a href="mulcons.html">multiple
consoles</a> for more information. </p>
<p>Note that first instruction is executed without effect of breakpoints and
simulation will be started afterwards. It means that if there is a
breakpoint at start address then it will not be hit. See following
example: </p>
<pre>$ <font color="#118811">./ucsim_51</font>
ucsim 0.2.38-pre1, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">b 0x10</font>
Breakpoint 1 at 0x000010: MOV R7,A
&gt; <font color="#118811">b 0x20</font>
Breakpoint 2 at 0x000020: MOV R7,A
&gt; <font color="#118811">run 0x10</font>
Warning: maybe not instruction at 0x000010
Simulation started, PC=0x000010
Stop at 0x000020: (104) Breakpoint
F 0x000020
&gt;
</pre>
<hr> <a name="stop">
<h3>stop</h3>
</a> This command stops the simulation, it freezes the CPU and all the
peripherals.
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">g</font>
Simulation started
&gt; <font color="#118811">dr</font>
000000 00 01 00 14 00 00 5a 47 ......ZG
000000 00 . ACC= 0x47 71 G B= 0x01 DPTR= 0x001c @DPTR= 0x47 71 G
000001 01 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
006f02 90 00 1e MOV DPTR,#001e
&gt; <font color="#118811">stop</font>
006ac5 24 a5 ADD A,#a5
&gt;
</pre> Simulated program is executed in background and the simulator accepts
commands. If it stopped by the stop command the instruction pointed by PC is
disassembled, see the <a href="#dis"><b>dis</b></a> command for description
of disassembled form.
<hr> <a name="step">
<h3>s,step [steps]</h3>
</a> Step command. It executes one instruction without effect of
breakpoints.
<p>The optional parameter can be used to specify number of instructions to
execute. Note that breakpoints will stop the execution after the first
instruction. </p>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">s</font>
000000 00 00 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0000 @DPTR= 0x00 0 .
000000 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000160 c2 90 CLR P1.0
&gt; </pre>
<p> After execution of actual instruction pointed by PC (or all instructions
specified by the optional parameter) the <b>step</b> command dumps out
the register set.</p>
<p>Number of steps can be specified in different units. If no unit is
appended to step number then it will be interpreted as number of
instruction. Other know units are:</p>
<dl>
<dt> s, sec</dt>
<dd>Simulated execution time in seconds.</dd>
<dt>ms, msec</dt>
<dd>Simulated execution time in milliseconds.</dd>
<dt>us, usec</dt>
<dd>Simulated execution time in microseconds.</dd>
<dt>ns, nsec</dt>
<dd>Simulated execution time in nanoseconds.</dd>
<dt>vclk</dt>
<dd>Number of virtual clock counts.</dd>
<dt>fclk, fetch</dt>
<dd>Number of fetches.</dd>
<dt>rclk, read</dt>
<dd>Number of memory read operations.</dd>
<dt>wclk, write</dt>
<dd>Number of memory write operations.</dd>
</dl>
<br>
<hr> <a name="n">
<h3>n,next</h3>
</a> Execute until next instruction is reached. This command is similar to <a
href="#s"><b>step</b></a> command described above but if actual
instruction to execute is a subroutine call the <b>next</b> command places
a dynamic breakpoint after the call instruction and starts to execute the
subroutine. If the subroutine is infinite the breakpoint set by <b>next</b>
will never reached. It can be a dangerous situation because the execution
started by the <b>next</b> command can not be stopped interactively. But it
can be stopped by other breakpoints.
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">run 0 0x172</font>
000172 79 04 MOV R1,#04
&gt; <font color="#118811">dis 0x172 0 5</font>
000170 7f 00 MOV R7,#00
000172 79 04 MOV R1,#04
000174 12 0d b8 LCALL 0db8
000177 0f INC R7
000178 d9 fa DJNZ R1,0174
00017a 75 0b 00 MOV 0b,#00
&gt; <font color="#118811">n</font>
000000 00 04 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0000 @DPTR= 0x00 0 .
000004 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000174 12 0d b8 LCALL 0db8
&gt; <font color="#118811">n</font>
000000 00 04 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0167 @DPTR= 0x00 0 .
000004 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000177 0f INC R7
&gt; </pre>
<hr> <a name="pc">
<h3>pc [address]</h3>
</a> Using this command without any parameter it simply dumps out
instruction pointed by the PC. Specify address if you want to set the PC.
<pre>$ ucsim_51
S51 0.1.5, Copyright (C) 1997 Daniel Drotos, Talker Bt.
S51 comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">pc</font>
* 000000 ff MOV R7,A
&gt; <font color="#118811">pc 123</font>
* 00007b ff MOV R7,A
&gt; <font color="#118811">sopt debug t </font>
&gt; <font color="#118811">pc 32</font>
Warning: maybe not instruction at 000020
* 000020 ff MOV R7,A
&gt; </pre>
<hr>
<h3><a name="history">history</a></h3>
History command can be used to inspect and manipulate history of executed
instructions. It accepts following subcommands:
<p><a href="#history_">history</a> <br>
history <a href="#history_information">information</a> <br>
history <a href="#history_list">list</a> <br>
history <a href="#history_clear">clear</a> </p>
<blockquote>
<h4><a name="history_">history</a></h4>
This command (without a subcommand) prints out last 10 elements of the
command history in disassembled form.
<pre>0&gt; <font color="#118811">hist</font>
? 0x0211 78 LD A,B
? 0x0212 de 22 SBC A,#0x22
? 0x0214 38 f7 JR C,#-9
? 0x0216 c9 RET
? 0x0109 c3 04 02 JP #0x0204
? 0x0204 3e 00 LD A,#0x00
? 0x0206 cf RST 8
? 0x0008 fb EI
? 0x0009 ed 4d RETI
? 0x0207 76 HALT
0&gt;
</pre>
<hr>
<h4><a name="history_information">history information</a></h4>
Print out information about execution history.
<pre>0&gt; <font color="#118811">hist info</font>
len: 100
used: 100
insts: 100
0&gt;
</pre>
<b>Len</b> is size of the history, <b>used</b> shows how many slots are
filled, <b>insts</b> is number of the instructions recorded by the
history.
<hr>
<h4><a name="history_list">history list [nr]</a> <br>
history print [nr]</h4>
This command is the same as the <a href="#history_">history</a> command
but it accepts a parameter which specifies how many records to print
(defaults to 10):
<pre>0&gt; <font color="#118811">hist list 3</font>
? 0x0008 fb EI
? 0x0009 ed 4d RETI
? 0x0207 76 HALT
0&gt; <font color="#118811">hist list 30</font>
? 0x020e 79 LD A,C
? 0x020f d6 33 sub #0x33
? 0x0211 78 LD A,B
? 0x0212 de 22 SBC A,#0x22
? 0x0214 38 f7 JR C,#-9
? 0x020d 03 INC BC
? 0x020e 79 LD A,C
? 0x020f d6 33 sub #0x33
? 0x0211 78 LD A,B
? 0x0212 de 22 SBC A,#0x22
? 0x0214 38 f7 JR C,#-9
? 0x020d 03 INC BC
? 0x020e 79 LD A,C
? 0x020f d6 33 sub #0x33
? 0x0211 78 LD A,B
? 0x0212 de 22 SBC A,#0x22
? 0x0214 38 f7 JR C,#-9
? 0x020d 03 INC BC
? 0x020e 79 LD A,C
? 0x020f d6 33 sub #0x33
? 0x0211 78 LD A,B
? 0x0212 de 22 SBC A,#0x22
? 0x0214 38 f7 JR C,#-9
? 0x0216 c9 RET
? 0x0109 c3 04 02 JP #0x0204
? 0x0204 3e 00 LD A,#0x00
? 0x0206 cf RST 8
? 0x0008 fb EI
? 0x0009 ed 4d RETI
? 0x0207 76 HALT
0&gt;
</pre>
<hr>
<h4><a name="history_clear">history clear</a></h4>
This command clears the history, it deletes all recorded elements.
<pre>0&gt; <font color="#118811">hist list 3</font>
? 0x0008 fb EI
? 0x0009 ed 4d RETI
? 0x0207 76 HALT
0&gt; <font color="#118811">hist clear</font>
0&gt; <font color="#118811">hist info</font>
len: 100
used: 0
insts: 0
0&gt;
</pre>
</blockquote>
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<h2>General commands of <i>&#956;Csim</i></h2>
<h3><a name="analyse">analyse|analyze [<i>addr</i>]</a></h3>
<p>Runs the <a href="analyzer.html">analyser</a> to identify code.
If an address is given it is taken as the starting point and the results
added to any existing analysis. If no address is given or a file is loaded
into memory using the <a href="cmd_memory.html#file">file,load</a> command
any existing analysis is cleared and a new one created using all the known
hardware vectors as starting points.</p>
<h3><a name="conf">conf</a></h3>
Conf command can be used to display different kind of information about <i>&#956;Csim</i>.
It can be followed by a subcommand:
<p><a href="#conf_">conf</a> <br>
conf <a href="#conf_objects">objects</a> </p>
<blockquote>
<h4><a name="conf_">conf</a></h4>
This command (without a subcommand) prints out configuration of the
simulator:
<pre>0&gt; <font color="#118811">conf</font>
ucsim version 0.5.0-pre3
Type of microcontroller: 51 CMOS
Controller has 9 hardware element(s).
timer0[0]
timer1[1]
uart[0]
port[0]
port[1]
port[2]
port[3]
irq[0]
_51_dummy[0]
0&gt;
</pre> First line contains version number of the program. Second line informs
about type of the simulated microcontroller. Third line prints out how
many hardware elements are simulated.
<h4><a name="conf_objects">conf <i>objects</i></a></h4>
This command is for development only. </blockquote>
<hr>
<h3><a name="version">version</a></h3>
Print out the version of the program.
<pre>0&gt; <font color="#118811">ver</font>
0.6-pre58
0&gt;
</pre>
<hr>
<h3><a name="h">?,help <i>[command]</i></a></h3>
Help command. It prints out short description of the commands.
<p>If a command name is given as parameter then <i>?Csim</i> prints out all
command that has similar names: </p>
<pre>0&gt; <font color="#118811">? s</font>
show subcommand Generic command for showing things about the uCsim
set subcommand Set, see `set' command for more help
stop Stop
step Step
state State of microcontroller
statistic [mem [startaddr [endaddr]]]
Statistic of memory accesses
0&gt; <font color="#118811">? s o</font>
show option [name] Show internal data of options
set option name|nr value
Set value of an option
0&gt;
</pre> Some commands have more than one name which can produce interesting
result:
<pre>0&gt; <font color="#118811">? t r</font>
timer delete id Delete a timer
timer start id Start a timer
0&gt;
</pre> It looks that names of listed subcommands start with no "r" but take a
closer look on that commands:
<pre>0&gt; <font color="#118811">? t d</font>
timer delete id Delete a timer
Names of command: delete remove
long help of timer delete
0&gt; <font color="#118811">? t start</font>
timer start id Start a timer
Names of command: run start
long help of timer run
0&gt; </pre>
<p>If parameter is unique name of a command then long description of the
command is printed out. </p>
<hr>
<h3><a name="q">quit</a></h3>
Quit. This command terminates actual console, it does not ask you to confirm
your intention. Simulator always reads commands from a file so end of file
condition finishes too.
<p>Note that if <a href="invoke.html#Zoption">-Z option</a> was used at
invocation then the quit command does not terminate the simulator program.
In this case <a href="#kill">kill</a> command can be used to terminate
the simulator. See for more information about <a href="mulcons.html">using
multiple consoles</a>. </p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">q</font>
$ </pre>
<hr>
<h3><a name="kill">kill</a></h3>
This command terminates the simulator. It does not ask for confirmation. It
doesn't matter how many consoles are used and what commands are running on
them.
<hr>
<h3><a name="exec">exec <i>"file"</i></a></h3>
Reads commands from "file" and executes them. This command opens a new
console (which will use same in/out file as the actual one) to execute the
file. This means the "quit" command in the file will not exit the simulator:
<pre>drdani@emma:~$ <font color="#118811">cat /tmp/x</font>
get opt
quit
conf
drdani@emma:~$ <font color="#118811">ucsim_51</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">exec "/tmp/x"</font>
1&gt; get opt
0. config_file(by application) is hidden!
1. console_on(by application) is hidden!
2. cpu_type(by application) is hidden!
3. debug(by console1): FALSE - Debug messages to console1
4. debug(by console0): FALSE - Debug messages to console0
5. debug(by application): FALSE - Print debug messages (-V)
6. irq_stop(by mcs51_controller): FALSE - Stop when IRQ accepted
7. null_prompt(by application): FALSE - Use \0 as prompt (-P)
8. prompt(by console1): "" - Prompt string of console1
9. prompt(by console0): "" - Prompt string of console0
10. prompt(by application): (null) - String of prompt (-p)
11. serial_in_file(by application) is hidden!
12. serial_out_file(by application) is hidden!
13. xtal(by application): 11059200.000 - Frequency of XTAL in Hz
1&gt; quit
0&gt;
</pre>
<hr>
<h3><a name="expression">expression [/format] <i>expr</i></a></h3>
Executes "expr" as an expression. For more about expressions, see <a href="syntax.html">command
syntax</a>.
<pre>0&gt; <font color="#118811">expr 1+2</font>
3
0&gt; <font color="#118811">expr xram[256*dph+dpl]= &amp;sp</font>
129
0&gt;
</pre>
Following formats are supported:
<ul>
<li><b>x</b> hexadecimal</li>
<li><b>X</b> hexadecimal prefixed with <tt>0x</tt></li>
<li><b>0</b> 8 characted long hexadecimal prefixed with <tt>0x</tt></li>
<li><b>d</b> signed decimal</li>
<li><b>o</b> octal</li>
<li><b>u</b> unsigned decimal</li>
<li><b>b</b> binary</li>
<li><b>B</b> logical value as one bit</li>
<li><b>L</b> logical value in T/F form</li>
<li><b>c</b> chacter constant in 'c' form (non-printable values are
escaped in c syntax)</li>
</ul>
If more then one format character is used then all requested form will be
printed:
<pre>0&gt; <font color="#118811">expr /bx 123</font>
00000000000000000000000001111011
7b
0&gt; </pre>
<hr>
<h3><a name="show">show</a></h3>
Show command can be used to display different kind of information. It must
be followed by a subcommand. Subcommands are:
<p>show <a href="#show_copying">copying</a> <br>
show <a href="#show_warranty">warranty</a> <br>
show <a href="#show_option">option</a> <br>
show <a href="#show_error">error</a> </p>
<blockquote>
<h4><a name="show_copying">show copying</a></h4>
This command can be used to list licensing information. It is first 10
point of the version 2 of GNU General Public License. If you do not accept
GPL simply do not use the program.
<hr>
<h4><a name="show_warranty">show warranty</a></h4>
This command prints out last 2 point of the license ("NO WARRANTY"
message).
<hr>
<h4><a name="show_option">show option</a></h4>
This command is for development only.
<hr>
<h4><a name="show_error">show error</a></h4>
Errors or warnings are events which can happen in the simulated system
during simulation. Report of that events can be turned on or off using <a
href="#set_error"><b>set error</b></a> command. Errors are organized in
parent-child relationship. Children are listed under the parent:
<pre>0&gt; <font color="#118811">sh er</font>
Error: non-classified [on/ON]
Error: memory [on/ON]
Error: invalid_address [unset/ON]
Error: non_decoded [unset/ON]
Error: stack [off/OFF]
Error: stack_tracker [unset/OFF]
Error: stack_tracker_wrong_handle [unset/OFF]
Error: operation_on_empty_stack [unset/OFF]
Warning: stack_operation_unmatched_to_top_of_stack [unset/OFF]
Warning: stack_looks_corrupted [unset/OFF]
0&gt; </pre>
First element is the type (Error or Warning). Error stops the simulation.
Warning is just reported and simulation goes on. Next element is the name
of the error. Last element shows actual value and state. Value can be:
<dl>
<dt><b>on</b></dt>
<dd>state is ON </dd>
<dt><b>off</b></dt>
<dd>state is OFF </dd>
<dt><b>unset</b></dt>
<dd>state is inherited from the parent. </dd>
</dl>
If state is <b>ON</b> and the event happens, it is reported. If state is
<b>OFF</b> then the event is silently ignored. </blockquote>
<hr>
<h3><a name="get">get</a></h3>
This command can be used to get value of various kind of things. It requires
a subcommand to specify what is going to be set. Known subcommands are:
<p>get <a href="#get_sfr">sfr</a> <br>
get <a href="#get_option">option</a> <br>
get <a href="#get_error">error</a> </p>
<blockquote>
<h4><a name="get_sfr">get sfr <i>address...</i></a></h4>
This command can be used to check values of SFR location(s) if SFR exists
in simulated memory. Note that <a href="cmd_dump.html#dump_memory">dump
memory</a> or <a href="cmd_dump.html#ds">ds</a> can be used as well.
<p>Parameters are interpreted as SFR names or addresses and values of
addressed locations are dumped out. </p>
<pre>$ <font color="#118811">ucsim_51 </font>
ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">get sfr pcon p1 0 0x80 kahd scon 256</font>
0x87 00 .
0x90 ff .
Warning: Invalid address 0
0x80 ff .
Warning: Invalid address kahd
0x98 00 .
Warning: Invalid address 256
0&gt; </pre>
<hr>
<h4><a name="get_option">get option <i>[name]</i></a></h4>
Get actual value of option(s). Some options can be set by <a href="#set_option"><b>set
option</b></a> to modify behaviour of the simulator. Using <b>get
option</b> you can get actual value of these options. If you use this
command without parameter you get list of all options known by the
program. In this way you can figure out which options can be used.
<pre>$ <font color="#118811">ucsim_51 -V</font>
ucsim 0.5.0, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">get opt</font>
3. debug(by console0): FALSE - Debug messages to console0
4. debug(by application): FALSE - Print debug messages (-V)
5. irq_stop(by mcs51_controller): FALSE - Stop when IRQ accepted
6. null_prompt(by application): FALSE - Use \0 as prompt (-P)
7. prompt(by console0): "" - Prompt string of console0
8. prompt(by application): (null) - String of prompt (-p)
11. xtal(by application): 11059200.000 - Frequency of XTAL in Hz
0&gt;
</pre> First element of the list is the number of the option. It is followed by
name of the option (<b>debug</b>, <b>irq_stop</b>, etc.). Number or the
name can be used to identify the option in <b>get option</b> and <a href="#set_option"><b>set
option</b></a> command. Next element shows which part of the simulator
created the option.
<p>Next element of the list is the value of the option. It can be an
integer or a floating point number, a string or a boolean value. </p>
<p>Last part describes the option. </p>
<p>Some options can have same name. An example is the <b>debug</b>
option. One is created by the application to store value given by -V
(see <a href="invoke.html">invocation</a>). This will be used as
default value when a new instance of a console is created: </p>
<pre>$ <font color="#118811">cat /tmp/x</font>
get opt debug
$ <font color="#118811">ucsim_51</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">get opt debug</font>
3. debug(by console0): FALSE - Debug messages to console0
4. debug(by application): FALSE - Print debug messages (-V)
0&gt; <font color="#118811">set opt 4 1</font>
0&gt; <font color="#118811">get opt debug</font>
3. debug(by console0): FALSE - Debug messages to console0
4. debug(by application): TRUE - Print debug messages (-V)
0&gt; <font color="#118811">exec "/tmp/x"</font>
1&gt; get opt debug
3. debug(by console1): TRUE - Debug messages to console1
4. debug(by console0): FALSE - Debug messages to console0
5. debug(by application): TRUE - Print debug messages (-V)
1&gt;
0&gt;
</pre>
<hr>
<h4><a name="get_error">get error</a></h4>
Same as <a href="#show_error">show error</a>. </blockquote>
<hr>
<h3><a name="set">set</a></h3>
This command can be used to set various kind of things. It requires a
subcommand to specify what is going to be set. Known subcommands are:
<p>set <a href="#set_option">option</a> <br>
set <a href="#set_error">error</a> <br>
set <a href="#set_memory">memory</a> <br>
set <a href="#set_bit">bit</a> <br>
set <a href="#set_hardware">hardware</a> </p>
<blockquote>
<h4><a name="set_option">set option <i>name|nr value</i></a></h4>
<p>Set option value. Options described at (<a href="#get_option"><b>get
option</b></a>) command can be set using this command. First
parameter must be an option name or number and second the new value.
Interpretation of the value depends on type of the option. Value for a
boolean type of option interpreted as follows: if first character of the
value is one of <tt>1</tt>, <tt>t</tt>, <tt>T</tt>, <tt>y</tt>, <tt>Y</tt>
then value will be TRUE otherwise it will be FALSE. </p>
<pre>$ <font color="#118811">ucsim_51 -V</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">get opt</font>
0. config_file(by application) is hidden!
1. console_on(by application) is hidden!
2. cpu_type(by application) is hidden!
3. debug(by console0): TRUE - Debug messages to console0
4. debug(by application): TRUE - Print debug messages (-V)
5. irq_stop(by mcs51_controller): FALSE - Stop when IRQ accepted
6. null_prompt(by application): FALSE - Use \0 as prompt (-P)
7. prompt(by console0): "" - Prompt string of console0
8. prompt(by application): (null) - String of prompt (-p)
9. serial_in_file(by application) is hidden!
10. serial_out_file(by application) is hidden!
11. xtal(by application): 11059200.000 - Frequency of XTAL in Hz
&gt; <font color="#118811">set opt debug f</font>
Ambiguous option name, use number instead
&gt; <font color="#118811">set opt 3 f</font>
&gt; <font color="#118811">get opt debug</font>
3. debug(by console0): FALSE - Debug messages to console0
4. debug(by application): TRUE - Print debug messages (-V)
&gt; </pre>
<hr>
<h4><a name="set_error">set error <i>error_name on|off|unset</i></a></h4>
This command can be used to set if an error event should be reported or
not. Actual settings can be retrieved by <a href="show_error">show error</a>
command.<br>
<hr>
<h4><a name="set_console">set console <i>interactive
[on|off]|noninteractive|raw|edited</i><br>
</a></h4>
<hr>
<h4><a name="set_memory">set memory <i>memory_type address data...</i></a></h4>
This command can be used to modify content of any simulated memory. First
parameter must be a class name to specify type of memory. Class names can
be checked by <a href="cmd_general.html#info_memory">info memory</a>
command. Chips and address spaces can be used as well.
<p>Second parameter specifies start address of the modification. </p>
<p>Remaining parameters will be written into the memory starting at
address specified by second parameter. Data list can include numbers as
well as strings. See <a href="syntax.html">syntax</a> for more details.
</p>
<p>Modified memory locations will be dumped out. </p>
<pre>0&gt; <font color="#118811">set mem xram 1 "ab\tcd\0ef\012ghq" 2 "ABC"</font>
0x0001 61 62 09 63 64 00 65 66 ab.cd.ef
0x0009 0a 67 68 71 02 41 42 43 .ghq.ABC
0&gt; <font color="#118811">set mem sfr pcon 0x34</font>
0x87 34 4
0&gt; <font color="#118811">set mem xram_chip 1 2</font>
0x0001 02 .
0&gt; </pre>
<hr>
<h4><a name="set_bit">set bit <i>address 0|1</i></a></h4>
Set one bit to 0 or 1. First parameter specifies the bit. It can be the
address of the bit (number or symbolic name) or it can be specified in <i>address<b>.</b>bitnumber</i>
format where <i>address</i> addresses SFR area and <i>bitnumber</i> is
number of bit in specified SFR location. Using this syntax any SFR (and
8051's internal RAM) location can be modified it need not be really bit
addressable.
<p>Second parameter interpreted as 1 if it is not zero. </p>
<p>Modified memory location is dumped out. </p>
<pre>$ <font color="#118811">ucsim_51 </font>
ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">set bit tf1 1</font>
0x88 80 .
&gt; <font color="#118811">set bit 130 0</font>
0x80 fb .
&gt; <font color="#118811">set bit pcon.2 1</font>
0x87 04 .
&gt; <font color="#118811">set bit 10.7 1</font>
0x0a 80 .
&gt;
</pre>
<hr>
<h4><a name="set_hardware">set hardware <i>hardware_id data</i></a></h4>
This command can be used to set value into a hardware element of the
controller (<a href="#conf">conf</a> command lists them).
<p>Actually only <b>port</b> element of MCS51 accepts this method. It can
be used to set value of external circuits which connected to ports of
simulated controller. First parameter specifies port element (as an
array), second is the new value. </p>
<pre>0&gt; <font color="#118811">conf</font>
Type of microcontroller: 51 CMOS
Controller has 9 hardware element(s).
timer0[0]
timer1[1]
uart[0]
port[0]
port[1]
port[2]
port[3]
irq[0]
_51_dummy[0]
0&gt; <font color="#118811">set hw port[0] 12</font>
0&gt; <font color="#118811">i h po[0]</font>
port[0]
P0 11111111 0xff 255 . (Value in SFR register)
Pin0 00001100 0x0c 12 . (Output of outside circuits)
Port0 00001100 0x0c 12 . (Value on the port pins)
0&gt; <font color="#118811">set hw port[0] 23</font>
0&gt; <font color="#118811">i h po[0]</font>
port[0]
P0 11111111 0xff 255 . (Value in SFR register)
Pin0 00010111 0x17 23 . (Output of outside circuits)
Port0 00010111 0x17 23 . (Value on the port pins)
0&gt; <font color="#118811">set hw irq[0] 12</font>
Nothing to do
0&gt;
</pre> </blockquote>
<hr>
<h3><a name="state">state</a></h3>
State of the simulator and the simulated microcontroller:
<pre>&gt; <font color="#118811">state</font>
CPU state= OK PC= 0x009c6c XTAL= 1.10592e+07
Operation since last reset= (51682412 vclks)
Inst= 51682412 Fetch= 51682412 Read= 0 Write= 0
Total time since last reset= 56.079 sec (620188944 clks)
Time in isr = 0 sec (0 clks) 0%
Time in idle= 0 sec (0 clks) 0%
Max value of stack pointer= 0x000007, avg= 0x000003
Simulation: stopped
&gt;
</pre> The "CPU state" in the first line is an internal information. PC is value
of the program counter. First line shows XTAL frequency too.
<p>Following lines contain information about simulated time. First, full
simulated time (elapsed from last reset) is printed out in seconds and
number of clock periods then same data is printed out about time spent in
interrupt service routines as well as in idle mode. Last data in lines of
ISR and IDLE time shows ratio of ISRs, Idle times and main program. </p>
<p>Last lines inform about maximum value of the stack pointer and a "not
very well" calculated average value of it, and if the simulation is
running or stopped. </p>
<hr>
<h3><a name="reset">reset</a></h3>
Reset command. It resets the microcontroller. It has same effect as active
signal on the RST pin.
<pre>$ <font color="#118811">ucsim_51 -V remoansi.hex</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">i r</font>
000000 00 00 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0000 @DPTR= 0x00 0 .
000000 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000000 02 01 60 LJMP 0160
&gt; <font color="#118811">s</font>
000000 00 00 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0000 @DPTR= 0x00 0 .
000000 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000160 c2 90 CLR P1.0
&gt; <font color="#118811">s</font>
000000 00 00 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0000 @DPTR= 0x00 0 .
000000 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000162 c2 97 CLR P1.7
&gt; <font color="#118811">res</font>
&gt; <font color="#118811">i r</font>
000000 00 00 00 00 00 00 00 00 ........
000000 00 . ACC= 0x00 0 . B= 0x00 DPTR= 0x0000 @DPTR= 0x00 0 .
000000 00 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
000000 02 01 60 LJMP 0160
&gt; </pre>
<hr>
<h3><a name="info">info</a></h3>
This command prints out information about different things which must be
specified as parameter to the command. Following subcommands are known:
<p>info <a href="#info_breakpoints">breakpoints</a> <br>
info <a href="#info_registers">registers</a> <br>
info <a href="#info_hardware">hardware</a> <br>
info <a href="#info_memory">memory</a> <br>
info <a href="#info_variables">variables</a> <br>
info <a href="#info_history">history</a> </p>
<blockquote>
<h4><a name="info_breakpoints">info breakpoints</a></h4>
This subcommand prints out information about breakpoints:
<pre>0&gt; <font color="#118811">b 12</font>
Breakpoint 1 at 0x00000c: MOV R7,A
0&gt; <font color="#118811">tb 43</font>
Breakpoint 2 at 0x00002b: MOV R7,A
0&gt; <font color="#118811">b sfr w 0x80</font>
0&gt; <font color="#118811">i b</font>
Num Type Disp Hit Cnt Address What
1 fetch keep 1 1 0x00000c MOV R7,A
2 fetch del 1 1 0x00002b MOV R7,A
3 event keep 1 1 0x000080 write
0&gt;
</pre> As you see above, the command can be shortened to "i b". The list of
breakpoints contains 7 columns:
<dl>
<dt><b>Num</b> </dt>
<dd>Number of the breakpoint. </dd>
<dt><b>Type</b> </dt>
<dd>This column shows type of the breakpoint. It can be <i>fetch</i>
for normal breakpoints or <i>event</i> for event breakpoints. First
the normal breakpoints are listed and then the event breakpoints. </dd>
<dt><b>Disp</b> </dt>
<dd>This shows if the breakpoint is temporary (<i>del</i>) or not (<i>keep</i>).
</dd> <dt><b>Hit</b> </dt>
<dd>How many times the breakpoint must be hit before it really stops the
program. </dd>
<dt><b>Cnt</b> </dt>
<dd>Counter of breakpoint hits. This counter decrements and the
breakpoint is activated if it reaches zero. </dd>
<dt><b>Address</b> </dt>
<dd>Address where the breakpoint is set. </dd>
<dt><b>What</b> </dt>
<dd>For normal breakpoints this field contains disassembled instruction
where the breakpoint is set. For event breakpoints it contains type of
event. </dd>
</dl>
<hr>
<h4><a name="info_registers">info registers</a></h4>
This subcommand prints out full register set of the CPU. Output of this
command depends of type of CPU.
<h5>Registers of MCS51 family</h5>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">sopt stopit 1</font>
&gt; <font color="#118811">g</font>
5
* 000023 02 01 1c LJMP 011c
&gt; <font color="#118811">i r</font>
000000 18 02 16 ba 00 02 00 0a ........
000018 4a J ACC= 0x0a 10 . B= 0x00 DPTR= 0x16ba @DPTR= 0x00 0 .
000002 16 . PSW= 0x00 CY=0 AC=0 OV=0 P=0
* 000023 02 01 1c LJMP 011c
&gt; </pre>
In first line the actual register bank is dumped out. Register banks
reside in internal RAM, address at the beginning of the line shows start
address of actual register bank selected by RS0 and RS1 bits of PSW
register.
<p>Next two lines begin with value of indirectly addressed internal RAM
cells. Second line shows IRAM cell pointed by R0 while third line shows
IRAM addressed by R1. </p>
<p>Second line displays some important registers. First one is the
accumulator. Its value dumped out in hexadecimal, decimal form and then
the ASCII character of its value. It is followed by value of the B
register which is dumped out in hexadecimal form only. Next is DPTR
register in hexadecimal and then external RAM cell which is addressed by
DPTR. This is dumped out in hexadecimal, decimal and ASCII too. </p>
<p>In third line you find program status word in hexadecimal and then some
flag bits of PSW register. Last line is disassembled instruction at PC.
</p>
<h5>Registers of AVR family</h5>
<pre>$ <font color="#118811">ucsim_avr test_arith.hex</font>
ucsim 0.2.37, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; 83 words read from test_arith.hex
83 words read from test_arith.hex
&gt; <font color="#118811">run</font>
Stop at 0x000047: (105) User stopped
F 0x000047
&gt; <font color="#118811">i r</font>
000000 00 2c 21 23 20 35 19 14 03 00 00 00 00 00 00 00 .,!# 5..........
000010 00 01 1e 89 01 00 10 e2 14 00 01 10 00 00 00 00 ................
ITHSVNZC SREG= 0x03 3 .
00000011 SP = 0x000000
X= 0x1001 [X]= 0x00 0 . Y= 0x0000 [Y]= 0x00 0 . Z= 0x0000 [Z]= 0x00 0 .
* 000047 940c 0047 jmp 0x000047
&gt;
</pre> First two lines show first 32 bytes of internal RAM which is the register
set of AVR controllers.
<p>At the beginning of next two lines bits of status register are printed.
These lines present hexadecimal, decimal and ASCII values of the status
register too, and value of the stack pointer. </p>
<p>Following line shows indirect addressing registers X, Y, and Z as well
as pointed memory values. </p>
<p>Last line is disassembled instruction at PC. </p>
<h5>Registers of Z80 family</h5>
<pre>$ <font color="#118811">ucsim_z80</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">i r</font>
SZ-A--P-C Flags= 0x00 0 . A= 0x00 0 .
00-0--0-0
BC= 0x0000 [BC]= 00 0 . DE= 0x0000 [DE]= 00 0 . HL= 0x0000 [HL]= 00 0 .
IX= 0x0000 [IX]= 00 0 . IY= 0x0000 [IY]= 00 0 . SP= 0x0000 [SP]= 00 0 .
? 0x0000 00 NOP
0&gt;
</pre>
<h5>Registers of XA family</h5>
<pre>$ <font color="#118811">ucsim_xa</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The XA Simulator is in development, UNSTABLE, DEVELOPERS ONLY!
0&gt; <font color="#118811">i r</font>
CA---VNZ | R0:0100 R1:0302 R2:0504 R3:0706
00---000 | R4:0908 R5:0b0a R6:0d0c SP:0100 ES:0000 DS:0000
? 0x0302 02 03 ADD R0l,[R3]
0&gt;
</pre>
<h5>Registers of HC08 family</h5>
<pre>$ <font color="#118811">ucsim_m68hc08</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">i r</font>
V--HINZC Flags= 0x60 96 ` A= 0x00 0 .
0--00000 H= 0x00 0 . X= 0x00 0 .
SP= 0x00ff [SP+1]= 00 0 .
? 0x0000 00 01 02 brset #0,*0x01,0x0005
0&gt;
</pre>
<hr>
<h4><a name="info_hardware">info hardware|hw <i>identifier</i></a></h4>
This subcommand prints out information about a unit of the controller. <b>identifier</b>
specifies hardware element. One form of it is a name. Names of hardware
elements can be checked by <a href="#conf">conf</a> command. This form is
accepted only when name is unique. If more than one element exists with
the same name then name must be followed by id number in square brackets
in same form as it is listed by <a href="#conf">conf</a> command.
<p>Output format of this command depends on CPU family and type of the CPU
too because requested unit can be different in different type of
controller even in the same CPU family. </p>
<pre>$ <font color="#118811">ucsim_51 -t 51</font>
ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">conf</font>
ucsim version 0.5.0-pre3
Type of microcontroller: 51 CMOS
Controller has 8 hardware element(s).
timer0[0]
timer1[1]
uart[0]
port[0]
port[1]
port[2]
port[3]
irq[0]
_51_dummy[0]
0&gt; <font color="#118811">i h port[2]</font>
port[2]
P2 11111111 0xff 255 . (Value in SFR register)
Pin2 11111111 0xff 255 . (Output of outside circuits)
Port2 11111111 0xff 255 . (Value on the port pins)
0&gt; <font color="#118811">i h t[0]</font>
timer0[0] 0x0000 13 bit timer OFF irq=0 dis prio=0
0&gt; <font color="#118811">i h u</font>
uart[0] Shift, fixed clock MultiProc=none irq=dis prio=0
Receiver OFF RB8=0 irq=0
Transmitter TB8=0 irq=0
0&gt;
</pre> Timer #2 differs a little bit from other timers of MCS51:
<pre>$ <font color="#118811">ucsim_51 -t 52</font>
ucsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">i h timer0</font>
timer0[0] 0x0000 13 bit timer OFF irq=0 dis prio=0
0&gt; <font color="#118811">i h t[2]</font>
timer2[2] 0x0000 reload 0x0000 timer OFF irq=0 dis prio=0
0&gt;
</pre>
<hr>
<!--
<h4><a name="info_stack">info stack</a></h4> This command prints out information about data stored in the CPU's stack and operations which put them there. <pre>$ <font color="#118811">ucsim_51 ~/remo.hex</font>uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.This is free software, and you are welcome to redistribute itunder certain conditions; type `show c' for details.55470 words read from /home/staff/drdani/remo.hex0&gt; <font color="#118811">set opt irq_stop true</font>0&gt; <font color="#118811">r</font>Simulation started, PC=0x000000Stop at 0x000023: (2) InterruptF 0x0000230&gt; <font color="#118811">i s</font>OP SP before-after L DATA/ADDR INSTRUCTION
call 0x000022-0x000024 2 0x002976 0x022a 12 29 76 LCALL 2976call 0x000024-0x000026 2 0x002379 0x2976 12 23 79 LCALL 2379call 0x000026-0x000028 2 0x003612 0x2517 12 36 12 LCALL 3612intr 0x000028-0x00002a 2 0x000023 0x366f 20 0c 02 JB 21.4,36740&gt; </pre> First column shows the operation which can be <b>call</b> or <b>push</b> or <b>intr</b> (interrupt call). Next column contains value of the SP register before and after the operation. Column "L" shows size of the data, and the next column the data itself. Note, that for call operations (call, and intr) the <b>called</b> address is printed, not the pushed one! Last column is the instruction which has been executed when the operation occurred.<hr>-->
<h4><a name="info_memory">info memory</a></h4>
This command shows information about <a href="memory.html">memory system</a>:
chips, address spaces and address decoders.
<pre>$ <font color="#118811">ucsim_51</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">i m</font>
Memory chips:
0x000000-0x010000 65536 rom_chip (8,%02x,0x%04x)
0x000000-0x000080 128 iram_chip (8,%02x,0x%02x)
0x000000-0x010000 65536 xram_chip (8,%02x,0x%04x)
0x000000-0x000080 128 sfr_chip (8,%02x,0x%02x)
Address spaces:
0x000000-0x010000 65536 rom (8,%02x,0x%04x)
0x000000-0x000080 128 iram (8,%02x,0x%02x)
0x000080-0x000080 128 sfr (8,%02x,0x%02x)
0x000000-0x010000 65536 xram (8,%02x,0x%04x)
Address decoders:
0 rom 0x0000 0xffff -&gt; rom_chip 0x0000 activated
0 iram 0x00 0x7f -&gt; iram_chip 0x00 activated
0 sfr 0x80 0xff -&gt; sfr_chip 0x00 activated
0 xram 0x0000 0xffff -&gt; xram_chip 0x0000 activated
0&gt;
</pre> First column shows address ranges, next one is the size followed by the
name of the memory. This name can be used in other commands (such as <a href="cmd_dump.html#dump">dump</a>,
<a href="#set_memory">set memory</a>, etc.). Last column shows some
technical information (width in bits, format specifier to print out
content and address).
<p>Address decoders are associated with address spaces. Each address space
has a list of decoders. First column of the address decoder information
is the number of the decoder. Next three columns specifies name and area
of the address space which is handled by the decoder. After "-&gt;" sign
the name and the address of the memory chip is printed where the decoder
maps the area of the address space. </p>
<p>Memory system of other controller family can be different. </p>
<pre>$ <font color="#118811">savr</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">i m</font>
Memory chips:
0x000000-0x00ffff 65536 rom_chip (16,%04x,0x%04x)
0x000000-0x00007f 128 iram_chip (8,%02x,0x%02x)
Address spaces:
0x000000-0x00ffff 65536 rom (16,%04x,0x%04x)
0x000000-0x00ffff 65536 iram (8,%02x,0x%04x)
Address decoders:
0 rom 0x0000 0xffff -&gt; rom_chip 0x0000 activated
0 iram 0x0000 0x007f -&gt; iram_chip 0x00 activated
0&gt;
</pre>
<hr>
<h4><a name="info_variables">info variables [[/filter] search]</a></h4>
Print out information about variables. Variable is memory location which
has a name. It can be created by <a href="cmd_memory.html#var">var</a>
command and several variables are created by the simulator. Optionally the
search string can be specified in the command to search for it in variable
names.
<p>Optional /filter parameter can be used to select variables according
to place where they were defined:</p>
<ul><li>/p List predefined variables only,</li>
<li>/u Print user defined variables,</li>
<li>/d List variables from debug info (cdb) file</li>
</ul>
<pre>0&gt; <font color="#118811">info var a</font>
pa rom[0xf000] = 00000000
Data register of pa
sim_real_time simif_0_cfg[0xa] = 00000000
Real time since reset in msec (int, RO)
sim_reason simif_0_cfg[0x5] = 00000000
Reason of last stop (int, RO)
sim_start simif_0_cfg[0x2] = 00000000
WR: start simulation, RD: true if running
sim_xtal simif_0_cfg[0x6] = 00a8c000
Xtal frequency in Hz (int, RW)
0&gt; <font color="#118811">var abc</font>
0&gt; <font color="#118811">i v a</font>
abc variables[0x00] = 00000000
pa rom[0xf000] = 00000000
Data register of pa
sim_real_time simif_0_cfg[0xa] = 00000000
Real time since reset in msec (int, RO)
sim_reason simif_0_cfg[0x5] = 00000000
Reason of last stop (int, RO)
sim_start simif_0_cfg[0x2] = 00000000
WR: start simulation, RD: true if running
sim_xtal simif_0_cfg[0x6] = 00a8c000
Xtal frequency in Hz (int, RW)
0&gt;
</pre>
First word is the name of the variable, followed by memory and the
address, last word is the actual value in hexadecimal. Predefined
variables have a short description which is printed in next line.
<hr>
<h4><a name="info_history">info history</a></h4>
This command is the same as <a href="cmd_exec.html#history_information">history
information</a>. </blockquote>
<hr>
<h3><a name="timer">timer</a></h3>
Handling of timers. Don't be confused! This command doesn't handle timer
element of the controller. It manages "clock counters" which can be used to
profile applications.
<p>Known subcommands are: </p>
<p>timer <a href="#timer_add">add</a> <br>
timer <a href="#timer_delete">delete</a> <br>
timer <a href="#timer_get">get</a> <br>
timer <a href="#timer_start">start</a> <br>
timer <a href="#timer_stop">stop</a> <br>
timer <a href="#timer_set">set</a> </p>
<p>Each subcommand can (some must) be followed by a timer id which can be a
number or a string. Timers are numbered from 1. You can use any number
greater than 0 to identify a timer. Or you can use a symbolic name, in
this case simulator uses the first unused number to allocate a new timer.
</p>
<blockquote>
<h4><a name="timer_add">timer add|create|make <i>id [direction [in_isr]]</i></a></h4>
To create a new timer. New timers are turned ON by default and initialized
to value 0. <b>Direction</b> is an integer (can be positive or negative)
number which is added to the actual value in every step. If <b>in_isr</b>
is TRUE the timer counts only when execution is in an interrupt handler.
<hr>
<h4><a name="timer_delete">timer delete|remove <i>id</i></a></h4>
To remove a timer if you don't need it any more.
<hr>
<h4><a name="timer_get">timer get <i>[id]</i></a></h4>
To get value of timers. If you don't use timer id in this command
simulator prints out value of all timers including predefined ones. See
example below.
<hr>
<h4><a name="timer_start">timer start|run <i>id</i></a></h4>
To turn a timer ON.
<hr>
<h4><a name="timer_stop">timer stop <i>id</i></a></h4>
To turn a timer OFF. It still exist but doesn't count xtal periods.
<hr>
<h4><a name="timer_set">timer set|value <i>id value</i></a></h4>
To set value of the timer (number of xtal periods). <b>value</b> is the
new value.
<pre>0&gt; <font color="#118811">tim a 3</font>
0&gt; <font color="#118811">tim g</font>
timer #0("time") ON: 0.463255 sec (5123232 clks)
timer #0("isr") ON: 0.0051888 sec (57384 clks)
timer #0("idle") ON,ISR: 0 sec (0 clks)
timer #3("unnamed") ON: 0 sec (0 clks)
0&gt; <font color="#118811">tim a "a"</font>
0&gt; <font color="#118811">tim g</font>
timer #0("time") ON: 0.463255 sec (5123232 clks)
timer #0("isr") ON: 0.0051888 sec (57384 clks)
timer #0("idle") ON,ISR: 0 sec (0 clks)
timer #1("a") ON: 0 sec (0 clks)
timer #3("unnamed") ON: 0 sec (0 clks)
0&gt;
</pre> </blockquote>
<hr>
</body>
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<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>Memory manipulation commands of &#956;Csim</title>
</head>
<body style=" background-color: white;">
<h2>Memory manipulation commands of &#956;Csim</h2>
Every command which changes content of ROM area such as <b><a href="#dl">dl</a></b>
or <b><a href="cmd_general#set_memory">set memory</a></b> deletes result of
<a href="analyzer.html">code analyser</a> and causes to re-analyse the code.
<hr> <a name="file">
<h3>file,load <i>"file"</i></h3>
</a> Loads file named file into the simulated code memory. File must contain
data in Intel HEX format.
<pre>&gt; <font color="#118811">file "../../remo.hex"</font>
55470 words read from ../../remo.hex
&gt;
</pre> Don't forget to enclose file name in quotes to make the parameter to be a
string.
<hr> <a name="dl">
<h3>download,dl</h3>
</a> Download command. It is same as <a href="#l">load</a> above but it
reads information from command console which is standard input by default.
This command stops read records when it detects an "END" record which is
normally the last record. This command has two equivalent forms <b>download</b>
and <b>dl</b>.
<pre>$ <font color="#118811">ucsim_51 -V</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">do
:03000000020003F8
:1000030075812078207600D8FC900000AE83AF8203
:100013009000001200416005E4F0A380F690009F79
:1000230012004A9000A312004A9000A712006890A1
:1000330000AD12006875D0001200B50200B3EF6581
:10004300827003EE658322E493F8740193F97402DA
:1000530093FE740393F5828E83E869700122E4931F
:10006300F6A30880F4E493FC740193FD740293FEF9
:10007300740393FF740493F8740593F582888312D1
:100083000041700122E493A3A883A9828C838D820B
:10009300F0A3AC83AD828883898280E3212100B5FC
:1000A300212100B5000000B500B5000000B500B582
:0200B30080FECD
:1000B5007520117501AA850120750102850120228F
:00000001FF</font>
197 bytes loaded
&gt; </pre>
<hr> <a name="fill">
<h3>fill <i>memory_type start end data</i></h3>
</a> Fill memory region with specified data. First parameter specifies
memory. Name of the memory must be used, it can be checked using <a href="cmd_general.html#info_memory">info
memory</a> command which lists size and name of all available memories.
<p><b>start</b> and <b>end</b> parameters specify first and last address of
the memory region to be filled. </p>
<p><b>data</b> parameter specifies the data which is used to fill the memory
region. </p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">fill xram 12 0x12 0x56</font>
&gt; <font color="#118811">dump xram 0 0x20</font>
0x0000 00 00 00 00 00 00 00 00 ........
0x0008 00 00 00 00 56 56 56 56 ....VVVV
0x0010 56 56 56 00 00 00 00 00 VVV.....
0x0018 00 00 00 00 00 00 00 00 ........
0x0020 00 .
&gt; </pre>
<hr> <a name="where">
<h3>where,Where <i>memory_type data...</i></h3>
</a> Searching for some data in memory. First parameter specifies memory.
Name of the memory must be used, it can be checked using <a href="cmd_general.html#info_memory">info
memory</a> command which lists size and name of all available memories.
<p>Other parameters can be mixed list of strings (characters between " and
") and numbers. Strings can contain escape sequences. &#956;Csim merges all
parameters together and will search for merged list of values in specified
memory. </p>
<p><b>where</b> command do case unsensitive search while <b>Where</b>
command is for case sensitive search. </p>
<p>Search is done in whole memory and all matches are dumped out. </p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.38-pre2, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">set mem xram 20 "Dani d ani D ani dani Dani"</font>
0x0014 44 61 6e 69 20 64 20 61 Dani d a
0x001c 6e 69 20 44 20 61 6e 69 ni D ani
0x0024 20 64 61 6e 69 20 44 61 dani Da
0x002c 6e 69 ni
&gt; <font color="#118811">where xram "dani"</font>
0x0014 44 61 6e 69 Dani
0x0025 64 61 6e 69 dani
0x002a 44 61 6e 69 Dani
&gt; <font color="#118811">Where xram "d ani"</font>
0x0019 64 20 61 6e 69 d ani
&gt; </pre>
<hr> <a name="hole">
<h3>hole <i>[memory [length [value]]]</i></h3>
</a>
<p>Searching for a memory area where all locations are filled with value. By
default this command searches rom but any memory can be specified. Areas
shorter than specified length (default is 100) will not be listed.
Searched value is 0 (zero) by default but other can be specified as the
last parameter. </p>
<pre>$ <font color="#118811">ucsim_51</font>
uCsim 0.6-pre55, Copyright (C) 1997 Daniel Drotos.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; hole
0x0000 65535
0&gt; <font color="#118811">hole xram</font>
0&gt; <font color="#118811">fill xram 0x100 0x1ff 11</font>
0&gt; <font color="#118811">hole xram 50 11</font>
0x0100 255
0&gt; <font color="#118811">fill xram 0x500 0x600 11</font>
0&amp;ht; <font color="#118811">hole xram 50 11</font>
0x0100 255
0x0500 256
0&gt; <font color="#118811">rom[0x200]=1</font>
1
0&gt; <font color="#118811">hole</font>
0x0000 511
0x0201 65022
0&gt; </pre>
<p> Data of found areas are listed in two columns. First column is the start
address of the area in hexadecimal and the second column is area length
(in decimal). </p>
<hr> <a name="memory">
<h3>memory</h3>
</a> This set of commands can be used to manipulate <a href="memory.html">memory
system</a> including <a href="memory.html#chip">chips</a>, <a href="memory.html#address_space">address
spaces</a> and <a href="memory.html#address_decoder">address decoders</a>.
<p>Subcommands are: </p>
<p><a href="#memory_create">memory create</a><br>
<a href="#memory_remove">memory remove</a><br>
<a href="#memory_info">memory info</a><br>
memory cell</p>
<a name="memory_create">
<h3>memory create</h3>
</a>
<p>This set of commands can be used to create new memory objects. It
requires a subcommand, which can be:</p>
<p><a href="#memory_create_chip">memory create chip</a><br>
<a href="#memory_create_addressspace">memory create addressspace</a><br>
<a href="#memory_create_addressdecoder">memory create addressdecoder</a><br>
<a href="#memory_create_banker">memory create banker</a><br>
<a href="#memory_create_bank">memory create bank</a><br>
<a href="#memory_create_bander">memory create bander</a></p>
<p><a name="memory_createchip"></a></p>
<blockquote><a name="memory_createchip"> </a><a name="memory_create_chip">
<h4>memory create chip <i>id size cellsize</i></h4>
</a> This command creates a chip (array of storage elements). <b>id</b>
must be a unique name which will be used to identify the chip in other
commands. <b>size</b> is number of storage elements, <b>cellsize</b> is
number of bits stored in one element.
<hr> <a name="memory_create_addressspace">
<h4>memory create as|addressspace|addr|addrs|addrspace|aspace <i>id
startaddr size</i></h4>
</a> This command should never be used. It defines an address space, names
it as <b>id</b>, sets its starting address and size. Simulator programs (<b>ucsim_51</b>,
<b>ucsim_avr</b>, etc.) define necessary address spaces for themself, so
this command is not needed.
<hr> <a name="memory_create_addressdecoder">
<h4>memory create
ad|addrdec|addrdecoder|addressdec|addressdecoder|adec|adecoder <i>addressspace
begin end chip begin</i></h4>
</a> Address decoder maps a part of the address space to a chip area. <b>addressspace</b>
parameter is name of the address space, <b>begin</b> and <b>end</b>
specify address range of the address space to be mapped. <b>chip</b>
parameter is name of the memory chip and the second <b>begin</b>
parameter is the (start of the) chip address where the area is mapped to.
<p>Address space will be split if a "middle" area is mapped: </p>
<pre>$ <font color="#118811">ucsim_51</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">i m</font>
Memory chips:
0x000000-0x00ffff 65536 rom_chip (8,%02x,0x%04x)
0x000000-0x00007f 128 iram_chip (8,%02x,0x%02x)
0x000000-0x00ffff 65536 xram_chip (8,%02x,0x%04x)
0x000000-0x00007f 128 sfr_chip (8,%02x,0x%02x)
Address spaces:
0x000000-0x00ffff 65536 rom (8,%02x,0x%04x)
0x000000-0x00007f 128 iram (8,%02x,0x%02x)
0x000080-0x0000ff 128 sfr (8,%02x,0x%02x)
0x000000-0x00ffff 65536 xram (8,%02x,0x%04x)
Address decoders:
0 rom 0x0000 0xffff -&gt; rom_chip 0x0000 activated
0 iram 0x00 0x7f -&gt; iram_chip 0x00 activated
0 sfr 0x80 0xff -&gt; sfr_chip 0x00 activated
0 xram 0x0000 0xffff -&gt; xram_chip 0x0000 activated
0&gt; <font color="#118811">mem cchip myram 0x1000 8</font>
0&gt; <font color="#118811">mem createaddressdecoder xram 1234 2000 myram 15</font>
0&gt; <font color="#118811">i m</font>
Memory chips:
0x000000-0x00ffff 65536 rom_chip (8,%02x,0x%04x)
0x000000-0x00007f 128 iram_chip (8,%02x,0x%02x)
0x000000-0x00ffff 65536 xram_chip (8,%02x,0x%04x)
0x000000-0x00007f 128 sfr_chip (8,%02x,0x%02x)
0x000000-0x000fff 4096 myram (8,%02x,0x%03x)
Address spaces:
0x000000-0x00ffff 65536 rom (8,%02x,0x%04x)
0x000000-0x00007f 128 iram (8,%02x,0x%02x)
0x000080-0x0000ff 128 sfr (8,%02x,0x%02x)
0x000000-0x00ffff 65536 xram (8,%02x,0x%04x)
Address decoders:
0 rom 0x0000 0xffff -&gt; rom_chip 0x0000 activated
0 iram 0x00 0x7f -&gt; iram_chip 0x00 activated
0 sfr 0x80 0xff -&gt; sfr_chip 0x00 activated
0 xram 0x0000 0x04d1 -&gt; xram_chip 0x0000 activated
1 xram 0x04d2 0x07d0 -&gt; myram 0x00f activated
2 xram 0x07d1 0xffff -&gt; xram_chip 0x07d1 activated
0&gt;
</pre> It is easy to share chip area between address spaces:
<pre>$ <font color="#118811">ucsim_51</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0&gt; <font color="#118811">mem createaddressdecoder rom 0 0xfff xram_chip 0xf000</font>
0&gt; <font color="#118811">i m</font>
Memory chips:
0x000000-0x00ffff 65536 rom_chip (8,%02x,0x%04x)
0x000000-0x00007f 128 iram_chip (8,%02x,0x%02x)
0x000000-0x00ffff 65536 xram_chip (8,%02x,0x%04x)
0x000000-0x00007f 128 sfr_chip (8,%02x,0x%02x)
Address spaces:
0x000000-0x00ffff 65536 rom (8,%02x,0x%04x)
0x000000-0x00007f 128 iram (8,%02x,0x%02x)
0x000080-0x0000ff 128 sfr (8,%02x,0x%02x)
0x000000-0x00ffff 65536 xram (8,%02x,0x%04x)
Address decoders:
0 rom 0x0000 0x0fff -&gt; xram_chip 0xf000 activated
1 rom 0x1000 0xffff -&gt; rom_chip 0x1000 activated
0 iram 0x00 0x7f -&gt; iram_chip 0x00 activated
0 sfr 0x80 0xff -&gt; sfr_chip 0x00 activated
0 xram 0x0000 0xffff -&gt; xram_chip 0x0000 activated
0&gt; <font color="#118811">rom[0]=0xab</font>
171
0&gt; <font color="#118811">xram[0xf000]</font>
171
0&gt;
</pre>
<hr> <a name="memory_create_banker">
<h4>memory create banker <i>switcher_addressspace switcher_address
switcher_mask banked_addressspace start end</i></h4>
</a>This command creates a "banker", which is a controllable dynamic
address decoder. This means that some part of an address space can be
mapped to different chips and the actual map is controlled by a memory
location.<br>
This command specifies the range of the address space and the control.<br>
Following parameters specify the controller:<br>
<ul>
<li><b>switcher_addressspace</b> address space where the controller
memory location is.</li>
<li><b>switcher_address</b> address of the controller.</li>
<li><b>switcher_mask</b> mask of the bits which select a chip. This
parameter specifies, how many banks will be used, so how many chips
will be needed. </li>
</ul>
Following parameters specify the address space and range which is covered
by this address decoder:<br>
<ul>
<li><b>banked_asddressspace</b> name of the address space which will be
banked.</li>
<li><b>start</b> start address of the area, and</li>
<li><b>end</b> and address of the area which will be banked.</li>
</ul>
<hr> <a name="memory_create_bank">
<h4>memory create bank <i>addressspace begin bank_nr chip begin</i></h4>
</a> Bank.
<hr> <a name="memory_create_bander">
<h4>memory create bander <i>addressspace begin end chip begin
bits_per_chip [distance]</i></h4>
</a> Bander. </blockquote>
<hr>
<a name="memory_remove">
<h3>memory remove|rm|del</h3>
</a>
This set of commands can be used to remove some memory object. It
requires a subcommand, which can be:
<p><a href="#memory_remove_chip">memory remove chip</a> </p>
<blockquote>
<a name="memory_remove_chip">
<h4>memory remove chip <i>id</i></h4>
</a>
This command deletes the specified memory chip from the
simulator. All address decoders that points to this chip will be
deleted too.
</blockquote>
<hr>
<a name="memory_info">
<h3>memory info</h3>
</a> This command is same as <a href="cmd_general.html#info_memory">info
memory</a>.
<hr> <a name="var">
<h3>var name [memory addr]</h3>
</a> This command assigns a name to a memory location. This name can be used
in <a href="cmd_general.html#expression">expression</a>s as variable. If
memory is not specified, next yet unnamed location will be used from a
special address space, called <b>variables</b>. This address space have 256
locations by default (32 bit each), but the size can be specified using <a
href="invoke.html">-a option</a> of the simulator program.
<pre>0&gt; <font color="#118811">var abc</font>
0&gt; <font color="#118811">i v abc</font>
abc variables[0x00] = 00000000
0&gt; <font color="#118811">abc=12</font>
12
0&gt; <font color="#118811">expr /b abc</font>
00000000000000000000000000001100
0&gt;
</pre>
Memory location can be specified in two forms:
<pre>0&gt; <font color="#118811">var vname rom 45</font>
0&gt; <font color="#118811">i var vname</font>
vname rom[0x002d] = 73d4d3c4
0&gt; <font color="#118811">var other rom[45]</font>
0&gt; <font color="#118811">i v other</font>
other rom[0x002d] = 73d4d3c4
0&gt;
</pre>
<hr> <a name="var">
<h3>rmvar name</h3>
</a> This command removes a variable.
<pre>0&gt; <font color="#118811">rmvar abc</font>
No such variable
</pre>
</body>
</html>

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<html>
<head>
<meta content="text/html; charset=ISO-8859-2" http-equiv="content-type">
<title>Removed commands of &mu;Csim</title>
</head>
<body bgcolor="white">
<h2>Removed commands of &mu;Csim</h2>
<font color="gray">
<a name="bse">
<h3>bse wi|ri|wx|rx|ws|rs|rc f|d addr [hit]</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_bp.html#break">break</a>
or <a href="cmd_bp.html#tbreak">tbreak</a> instead!!</font>
<p>Set event breakpoint. First parameter specifies type of event. See <a
href="#breakpoints">general description of event breakpoints</a> above
about meaning of event identifiers. Second parameter specify if the
breakpoint will be fix (<b>f</b>) or dynamic (<b>d</b>). Third
parameter specifies address. Remember that this is not an instruction
address, it is address of the memory cell where specified event should
occur.
</p>
<p>Forth parameter is optional and it specifies the hit number. It is
1 by default.
</p>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">dis</font>
00d47e 22 RET
000000 02 01 60 LJMP 0160
000160 c2 90 CLR P1.0
000162 c2 97 CLR P1.7
000164 d2 b5 SETB P3.5
000166 d2 b4 SETB P3.4
000168 75 81 22 MOV SP,#22
00016b 75 d0 00 MOV PSW,#00
00016e 7e 00 MOV R6,#00
000170 7f 00 MOV R7,#00
000172 79 04 MOV R1,#04
000174 12 0d b8 LCALL 0db8
000177 0f INC R7
000178 d9 fa DJNZ R1,0174
00017a 75 0b 00 MOV 0b,#00
00017d 75 0c 00 MOV 0c,#00
000180 02 02 2a LJMP 022a
000183 78 22 MOV R0,#22
000185 76 00 MOV @R0,#00
000187 d8 fc DJNZ R0,0185
&gt; <font color="#118811">bse wi f 6</font>
&gt; <font color="#118811">g</font>
4
000170 7f 00 MOV R7,#00
&gt; </pre>
<a name="bde">
<h3>bde wi|ri|wx|rx|ws|rs|rc addr</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_bp.html#delete">delete</a>
instead!!</font>
<p>Delete event breakpoint. First parameter must be given to specify type
of event. Second parameter is address of memory cell which the
breakpoint is associated to. Continuing example given above:
</p>
<pre>&gt; <font color="#118811">bl</font>
D 2(2) 000180 02 LJMP 022a
F 1(1) 000006 wi
&gt; <font color="#118811">bde ri 6</font>
No ri breakpoint at 000006
&gt; <font color="#118811">bde wi 6</font>
&gt; <font color="#118811">bl</font>
D 2(2) 000180 02 LJMP 022a
&gt; </pre>
<a name="ba">
<h3>ba</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_bp.html#delete">delete</a>
instead!!</font>
<p>Delete all breakpoints. This command deletes all fetch as well as
event breakpoints. Be carefull because it does not ask you to confirm
your intention.
</p>
<pre>&gt; <font color="#118811">bl</font>
F 1(1) 000160 c2 CLR P1.0
D 2(2) 000180 02 LJMP 022a
F 1(1) 000006 wi
&gt; <font color="#118811">ba</font>
&gt; <font color="#118811">bl</font>
&gt; </pre>
<a name="dp">
<h3>dp</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#info_hw">info
hardware</a> instead!!</font>
<p>Dump out ports. This command shows actual value of ports.
</p>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">sopt stopit 1</font>
&gt; <font color="#118811">g</font>
5
* 000023 02 01 1c LJMP 011c
&gt; <font color="#118811">dp</font>
P0 11111111 0xff 255 . P1 11111110 0xfe 254 .
Pin0 11111111 0xff 255 . Pin1 11111111 0xff 255 .
Port0 11111111 0xff 255 . Port1 11111110 0xfe 254 .
P2 11111111 0xff 255 . P3 11111111 0xff 255 .
Pin2 11111111 0xff 255 . Pin3 11111111 0xff 255 .
Port2 11111111 0xff 255 . Port3 11111111 0xff 255 .
&gt; </pre>
First lines on the list (labeled with Px) are value of SFRs which are
internal latch registers. Second lines (labeled with Pinx) are outputs
of external devices connected to port pins of the
microcontroller. These values can be set by you using <a href="#sp"><b>sp</b></a>
command. Third lines (labeled with Portx)
show actual values can be measured on pins of the device. These values
are calculated with following pseudo formula:
<p><tt>Portx= Px AND Pinx</tt>
</p>
<p>All three values are displayed in binary, hexadecimal, decimal form
and then the ASCII character of the value is shown.
<a name="ds"></a></p>
<h3><a name="ds">ds [addr...]</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_dump.html#dump">dump</a>
instead!!</font>
Print out SFR. This command can be used to get value of all or some
SFRs. If you do not specify any parameter the <b>ds</b> command simply
dumps out full SFR area 16 bytes per line.
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">sopt stopit 1</font>
&gt; <font color="#118811">g</font>
5
* 000023 02 01 1c LJMP 011c
&gt; <font color="#118811">ds</font>
000080 ff 2a ba 16 00 00 00 00 55 a1 d7 fe 50 fd 00 00 .*......U...P...
000090 fe 00 00 00 00 00 00 00 7e 00 00 00 00 00 00 00 ........~.......
0000a0 ff 00 00 00 00 00 00 00 97 00 00 00 00 00 00 00 ................
0000b0 ff 00 00 00 00 00 00 00 15 00 00 00 00 00 00 00 ................
0000c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0000d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0000e0 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0000f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
&gt; <font color="#118811">ds p1 0x87</font>
P1 fe 254 .
000087 00 0 .
&gt; <font color="#118811">ds p2 ip scon</font>
P2 ff 255 .
IP 15 21 .
SCON 7e 126 ~
&gt; </pre>
If you specify one or more parameter the <b>ds</b> command prints out
value of registers specified by parameters. Parameter can be an
address or a symbolic name of the register. Note that the simulator
implements a register at all address in the address space which is not
true in real microcontroller where reading of an unimplemented
register gets undefined value. Value of the registers printed out in
hexadecimal, decimal, and ASCII form.
<p>Note that different type of controllers can implement different
registers:
</p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">ds rcap2l</font>
&gt; <font color="#118811">q</font>
$ <font color="#118811">ucsim_51 -t 52</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">ds rcap2l</font>
RCAP2L 00 0 .
&gt; </pre>
<a name="db">
<h3>db addr...</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_dump.html#dump">dump</a>
instead!!</font>
Dump bits. This command can be used to get value of bits. At least one
parameter must be given. Bit address can be specified in three
forms. First of all name of the bit can be used if it has any. Direct
bit address is accepted too and it can be specified by address of IRAM
or SFR which contains the bit and bit number within the byte separated
by a dot. If the requested bit is in an SFR the address of the
register can be specified by its name.
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">db it1 0x20.3 0x43 p2.5</font>
000088 IT1 0
000020 20.3 0
000028 28.3 0
0000a0 P2.5 1
&gt; </pre>
Value of bits are printed out one per line. The list starts direct
address of the bit followed by bit name or address of the memory cell
or SFR which contains the displayed bit and bit number within the byte
separated by a dot. At last the value of the bit is shown. Displaying
a port bit you get value of SFR latch:
<pre>&gt; <font color="#118811">sp 1 0x0f</font>
&gt; <font color="#118811">ss p1 0x55</font>
000090 55 U
&gt; <font color="#118811">dp</font>
P0 11111111 0xff 255 . P1 01010101 0x55 85 U
Pin0 11111111 0xff 255 . Pin1 00001111 0x0f 15 .
Port0 11111111 0xff 255 . Port1 00000101 0x05 5 .
P2 11111111 0xff 255 . P3 11111111 0xff 255 .
Pin2 11111111 0xff 255 . Pin3 11111111 0xff 255 .
Port2 11111111 0xff 255 . Port3 11111111 0xff 255 .
&gt; <font color="#118811">db p1.2 p1.3 p1.4 p1.5 p1.6</font>
000090 P1.2 1
000090 P1.3 0
000090 P1.4 1
000090 P1.5 0
000090 P1.6 1
&gt; </pre>
<a name="g">
<h3>g [start [stop]]</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_exec.html#run">run</a>
instead!!</font>
<p>Go, start execution. Parameters are optional. First parameter
specifies start address of the execution. By default execution starts
at address specified by actual value of the PC. This can be overridden
by first parameter. If second parameter is specified it places a
dynamic breakpoint at specified address which stops the execution. If
stop address is not given the simulator stops if it reaches a
breakpoint, or the CPU accepts an interrupt and <b>stopit</b> option
is TRUE, or fatal error occurres or <a href="#stop">stop</a> command is
used. Note that first instruction is executed without effect of
breakpoints. It means that if there is a breakpoint at start address
then it will not be hit.
</p>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
55755 bytes read from remoansi.hex
&gt; <font color="#118811">b 0x187</font>
&gt; <font color="#118811">sopt stopit y</font>
&gt; <font color="#118811">g</font>
Simulation started, PC=0x000000
Stop at 000187: (4) Breakpoint
F 000187
&gt; </pre>
After execution is started the <tt>Simulation started</tt> message
appears with value of PC where the execution started and the simulator
is ready to accept other commands while the simulation is running in
background.
<!--If execution stops the simulator first writes out a number which is
the reason of the stop (this is a diagnostic feature, it will beimproved in future versions). Reason can be:
<dl><dt>0
<dd>There is no reason to stop. This number should never appear.
<dt>1
<dd>Serious error for example unknown instruction code which is
impossible to execute.
<dt>2
<dd>Invalid address used in an instruction. For example indirectaddress is bigger then 127 in 51 type of controller. Execution can be
continued but result will be undefined.
<dt>3
<dd>Stack overflow. Execution can be continued but result will be undefined.
<dt>4
<dd>Breakpoint has been reached.
<dt>5
<dd>Interrupt accepted. It only stops the execution if <b>stopit</b>
option is set to TRUE. See <a href="#sopt">sopt</a> command.
</dl>
After this diagnostic message the simulator prints out instruction at the PC in disassembled form. See <a href="#dis"><b>dis</b></a>
commands for description of disassembled form.-->
<a name="wi">
<h3>wi,Wi string</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#where">where,Where</a>
instead!!</font>
<p>Searching for specified string in internal RAM area. String is
interpreted from first non-space character until end of the command
including spaces. <b>wi</b> command makes case insensitive search and
<b>Wi</b> can be used to make case sensitive search. Result is a hexa
dump of memory areas that match with specified string. Most of C-style
escape sequences can be used in the string: <tt>\f</tt>, <tt>\n</tt>,
<tt>\r</tt>, <tt>\t</tt>, <tt>\v</tt>, <tt>\a</tt>, <tt>\b</tt>,
<tt>\0</tt>, and <tt>\0xxx</tt> where <tt>xxx</tt> is an octadecimal
number of the code of the character.
</p>
<pre>$ <font color="#118811">ucsim_51 remoansi.hex</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
58659 bytes read from remoansi.hex
&gt; <font color="#118811">g</font>
Simulation started, PC=0x000000
Stop at 00019c: (7) User stopped
F 00019c
&gt; <font color="#118811">si 20 Dani DAni</font>
000014 44 61 6e 69 44 41 6e 69 DaniDAni
&gt; <font color="#118811">wi dani</font>
000014 44 61 6e 69 Dani
000018 44 41 6e 69 DAni
&gt; <font color="#118811">Wi Dani</font>
000014 44 61 6e 69 Dani
&gt; <font color="#118811">wi dani\0</font>
000018 44 41 6e 69 00 DAni.
&gt; </pre>
<a name="wx">
<h3>wx,Wx string</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#where">where,Where</a>
instead!!</font>
<p>Search commands. These commands are similar to <a href="#wi"><b>wi,
Wi</b></a> commands the only difference is that <b>wx,Wx</b> are
used
to search for a string in external memory.
<a name="wc"></a></p>
<h3><a name="wc">wc,Wc string</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#where">where,Where</a>
instead!!</font>
<p>Search commands. These commands are similar to <a href="#wi"><b>wi,
Wi</b></a> commands the only difference is that <b>wx,Wx</b> are
used
to search for a string in code memory area.
<a name="gopt"></a></p>
<h3><a name="gopt">gopt [opt]</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#get_option">get_option</a>
instead!!</font>
<p>Get actual value of option(s). Some options can be set by <a href="#sopt"><b>sopt</b></a>
to modify behavior of the
simulator. Using <b>gopt</b> you can get actual value of these
options. If you use this command without parameter you get list of all
options known by the program. In this way you can figure out which
options can be used.
</p>
<pre>$ <font color="#118811">ucsim_51 -V</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">gopt</font>
verbose TRUE Verbose flag.
stopit FALSE Stop if interrupt accepted.
debug FALSE Debug flag.
&gt; <font color="#118811">gopt stopit</font>
stopit FALSE Stop if interrupt accepted.
&gt; </pre>
This version of the simulator knows about three options. First element
of the list is name of the option (<b>verbose</b>, <b>debug</b> and
<b>stopit</b>). This name can be used to identify the option in
<b>gopt</b> and <a href="#sopt"><b>sopt</b></a> command. Second
element of the list is the value of the option. In this case type of
both options is boolean, their value can be TRUE or FALSE. Third
element is a short description of the option.
<dl>
<dt><b>verbose</b> </dt>
<dd>?
</dd>
<dt><b>debug</b> </dt>
<dd>Debug flag can be set by <b>-V</b> option of the
program to TRUE otherwise its default value is FALSE. If it is TRUE,
the simulator prints out short messages about important events.
</dd>
<dt><b>stopit</b> </dt>
<dd>Setting this option to TRUE (default value is
FALSE) forces execution to stop every time when CPU accepts an
interrupt. You do not have to use breakpoints to inspect interrupts.
</dd>
</dl>
<a name="sopt">
<h3>sopt opt value</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_option">set_option</a>
instead!!</font>
<p>Set option value. Options described at previous command (<a href="#gopt"><b>gopt</b></a>)
can be set using this command. First
parameter must be an option name and second the new
value. Interpretation of the value depends on type of the
option. Value for a boolean type of option interpreted as follows: if
first character of the value is one of <tt>1</tt>, <tt>t</tt>,
<tt>T</tt>, <tt>y</tt>, <tt>Y</tt> then value will be TRUE otherwise
it will be FALSE.
</p>
<pre>$ <font color="#118811">ucsim_51 -V</font>
ucsim 0.2.24, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">gopt</font>
verbose TRUE Verbose flag.
stopit FALSE Stop if interrupt accepted.
debug FALSE Debug messages appears on this console.
&gt; <font color="#118811">sopt debug t</font>
&gt; <font color="#118811">gopt</font>
verbose TRUE Verbose flag.
stopit FALSE Stop if interrupt accepted.
debug TRUE Debug messages appears on this console.
&gt; </pre>
<a name="si">
<h3>si addr data...</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_memory">set
memory</a> instead!!</font>
<p>Write data into internal RAM area. First parameter specifies start
address of memory area to set and other parameters are data to set.
</p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">si 10 dani\040hej-ho</font>
00000a 64 61 6e 69 20 68 65 6a 2d 68 6f dani hej-ho
&gt; </pre>
Result of the command is a memory dump of area which has been modified
by the command. If there is syntax error in a data parameter then
remaining parameters are dropped out.
<pre>&gt; <font color="#118811">si 20 1 2 0xi 3 4</font>
Bad data 0xi
000014 01 02 ..
&gt; </pre>
<a name="sx">
<h3>sx addr data...</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_memory">set
memory</a> instead!!</font>
<p>This command is similar to <a href="#si"><b>si</b></a> command
described above but it is used to modify external RAM.
<a name="sc"></a></p>
<h3><a name="sc">sc addr data...</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_memory">set
memory</a> instead!!</font>
<p>This command is similar to <a href="#si"><b>si</b></a> command
described above but it is used to modify code memory area (ROM).
<a name="ss"></a></p>
<h3><a name="ss">ss addr data...</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_memory">set
memory</a> instead!!</font>
<p>This command is similar to <a href="#si"><b>si</b></a> command
described above but it is used to modify SFR. Other difference is that
first parameter (<b>start</b> address) can be specified by name of SFR
not by address only.
</p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">ss p1 0</font>
000090 00 .
&gt; </pre>
<a name="sb">
<h3>sb addr data...</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_bit">set
bit</a> instead!!</font>
<p>Modify bit(s). First parameter is address of first bit to modify. See
description of <a href="#db"><b>db</b></a> command how bit address can
be specified. If first character of data parameter is <tt>0</tt> it
means <i>zero</i> otherwise it means <i>one</i>.
</p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">sb 0x23.5 1</font>
&gt; <font color="#118811">db 0x23.5</font>
000023 23.5 1
&gt; <font color="#118811">sb p3.3 0</font>
&gt; <font color="#118811">dp</font>
P0 11111111 0xff 255 . P1 11111111 0xff 255 .
Pin0 11111111 0xff 255 . Pin1 11111111 0xff 255 .
Port0 11111111 0xff 255 . Port1 11111111 0xff 255 .
P2 11111111 0xff 255 . P3 11110111 0xf7 247 .
Pin2 11111111 0xff 255 . Pin3 11111111 0xff 255 .
Port2 11111111 0xff 255 . Port3 11110111 0xf7 247 .
&gt; <font color="#118811">sb tr1 0</font>
&gt; <font color="#118811">db tr1</font>
000088 TR1 0
&gt; <font color="#118811">sb tr1 1</font>
&gt; <font color="#118811">db tr1</font>
000088 TR1 1
&gt; </pre>
<a name="sp">
<h3>sp port data</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#set_port">set
port</a> instead!!</font>
<p>This command can be used to set up output values of external circuits
connected to port pins. If a port bit is used as output to drive
external circuits, do not set corresponding pin bit to zero because
read back value of the port can be false. First parameter must be
number of the port between 0 and 3.
</p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">dp</font>
P0 11111111 0xff 255 . P1 11111111 0xff 255 .
Pin0 11111111 0xff 255 . Pin1 11111111 0xff 255 .
Port0 11111111 0xff 255 . Port1 11111111 0xff 255 .
P2 11111111 0xff 255 . P3 11111111 0xff 255 .
Pin2 11111111 0xff 255 . Pin3 11111111 0xff 255 .
Port2 11111111 0xff 255 . Port3 11111111 0xff 255 .
&gt; <font color="#118811">ss p1 0x55</font>
000090 55 U
&gt; <font color="#118811">sp 1 0x0f</font>
&gt; <font color="#118811">dp</font>
P0 11111111 0xff 255 . P1 01010101 0x55 85 U
Pin0 11111111 0xff 255 . Pin1 00001111 0x0f 15 .
Port0 11111111 0xff 255 . Port1 00000101 0x05 5 .
P2 11111111 0xff 255 . P3 11111111 0xff 255 .
Pin2 11111111 0xff 255 . Pin3 11111111 0xff 255 .
Port2 11111111 0xff 255 . Port3 11111111 0xff 255 .
&gt; </pre>
<a name="fi">
<h3>fi start stop data</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#fill">fill</a>
instead!!</font>
<p>Fill command. It can be used to fill up an area of internal RAM with a
specified data.
</p>
<pre>$ <font color="#118811">ucsim_51</font>
ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt; <font color="#118811">fi 11 0x34 44</font>
&gt; <font color="#118811">di</font>
000000 00 00 00 00 00 00 00 00 ........
000008 00 00 00 2c 2c 2c 2c 2c ...,,,,,
000010 2c 2c 2c 2c 2c 2c 2c 2c ,,,,,,,,
000018 2c 2c 2c 2c 2c 2c 2c 2c ,,,,,,,,
000020 2c 2c 2c 2c 2c 2c 2c 2c ,,,,,,,,
000028 2c 2c 2c 2c 2c 2c 2c 2c ,,,,,,,,
000030 2c 2c 2c 2c 2c 00 00 00 ,,,,,...
000038 00 00 00 00 00 00 00 00 ........
000040 00 00 00 00 00 00 00 00 ........
000048 00 00 00 00 00 00 00 00 ........
&gt; </pre>
<a name="fx">
<h3>fx start stop data</h3>
</a>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#fill">fill</a>
instead!!</font>
<p>Fill command. It works similar to <a href="#fi"><b>fi</b></a> but it
puts data into external RAM instead of internal RAM.
<a name="fs"></a></p>
<h3><a name="fs">fs start stop data</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#fill">fill</a>
instead!!</font>
<p>Fill command. It works similar to <a href="#fi"><b>fi</b></a> but it
puts data into SFR instead of internal RAM.
<a name="fc"></a></p>
<h3><a name="fc">fc start stop data</a></h3>
<font color="#ff2211">Removed 0.2.38, use <a href="cmd_general.html#fill">fill</a>
instead!!</font>
</font>
<p><font color="gray">Fill command. It works similar to <a href="#fi"><b>fi</b></a>
but it
puts data into code memory (ROM) instead of internal RAM.
</font>
</p>
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>&#956;Csim: CPU types</title>
</head>
<body bgcolor="white">
<h1>Select type of CPU</h1>
The simulator supports following type of microprocessors from MCS51 family:
<p><a href="#51">8051/8031</a> <br>
<a href="#52">8052/8032</a> <br>
<a href="#ds390">DS390</a> <br>
<a href="#51r">8051R</a> <br>
<a href="#89c51r">89C51R</a> <br>
<a href="#251">80251</a> </p>
<h3><a name="51">8051/8031</a></h3>
You can select this type of microcontroller using one of the following
parameter for -t option:
<ul>
<li>51 (HMOS type) </li>
<li>8051 (HMOS type) </li>
<li>8751 (HMOS type) </li>
<li>C51 (CMOS type) </li>
<li>80C51 (CMOS type) </li>
<li>87C51 (CMOS type) </li>
<li>31 (HMOS type) </li>
<li>8031 (HMOS type) </li>
<li>C31 (CMOS type) </li>
<li>80C31 (CMOS type) </li>
</ul>
It includes core 51 features:
<ul>
<li>64k external RAM </li>
<li>64k ROM </li>
<li>128 byte internal RAM </li>
<li>2 timers (timer #0, timer #1) </li>
<li>Serial interface </li>
<li>4 8-bit quasi bi-directional ports </li>
</ul>
CMOS types also include:
<ul>
<li>Idle mode </li>
<li>Power down mode </li>
</ul>
<h3><a name="52">8052/8032</a></h3>
You can select this type of microcontroller using one of the following
parameter for -t option:
<ul>
<li>52 (HMOS type) </li>
<li>8052 (HMOS type) </li>
<li>8752 (HMOS type) </li>
<li>C52 (CMOS type) </li>
<li>80C52 (CMOS type) </li>
<li>87C52 (CMOS type) </li>
<li>32 (HMOS type) </li>
<li>8032 (HMOS type) </li>
<li>C32 (CMOS type) </li>
<li>80C32 (CMOS type) </li>
</ul>
It includes same features as <a href="#51">8051/8031</a> microcontrollers
and additionally:
<ul>
<li>3 timers (timer #0, timer #1, timer #2) </li>
<li>256 bytes of internal RAM </li>
</ul>
<h3><a name="ds320">DS320</a></h3>
You can select this type of microcontroller using <b>DS320</b> as parameter
for -t option (this is a CMOS type). It includes same features as <a href="#52">8052</a>
and adds:
<ul>
<li>support for dual DPTR register </li>
</ul>
<h3><a name="ds390">DS390</a></h3>
You can select this type of microcontroller using <b>DS390</b> as parameter
for -t option (this is a CMOS type). It includes same features as <a href="#52">8052</a>
and adds:
<ul>
<li>24 bit flat mode </li>
<li>support for dual DPTR register </li>
<li>128k external RAM </li>
<li>128k ROM </li>
<li>4k internal SRAM usable </li>
<li>10 bit stack mode </li>
<li>"timed access" of SFRs </li>
</ul>
<h3><a name="51r">8051R</a></h3>
You can select this type of microcontroller using one of the following
parameter for -t option (all are CMOS types):
<ul>
<li>51R </li>
<li>51RA </li>
<li>51RB </li>
<li>51RC </li>
<li>C51RA </li>
<li>C51RB </li>
<li>C51RC </li>
</ul>
It includes all features that <a href="#52">8052/8032</a> does and
additionally:
<ul>
<li>Extended interrupt priority system (4 priority levels) </li>
<li>Extended serial line interface (automatic address recognition) </li>
<li>Watchdog timer </li>
</ul>
<h3><a name="89c51r">89C51R</a></h3>
You can select this type of microcontroller using <tt>89C51R</tt> parameter
for -t option (this CPU is always CMOS). This is a Philips clone, excluding
duplicated DPTR it is similar to 8051XR from Intel.
<p>It includes all features that <a href="#51r">8051R</a> does and
additionally: </p>
<ul>
<li>PCA (Programmable Counter Array): 5 16-bit counter, one of them can
act as watchdog timer. </li>
<li>Duplicated DPTR. </li>
</ul>
<h3><a name="251">80251</a></h3>
You can select this type of microcontroller using one of the following
parameter for -t option (all are CMOS types):
<ul>
<li>251 </li>
<li>C251 </li>
</ul>
<p>It includes all features that <a href="#89c51r">89C51R</a> does and
additionally: </p>
<ul>
<li>Nothing implemented yet. </li>
</ul>
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=UTF-8">
<title>Mikrocontroller Simulator</title>
</head>
<body style=" background-color: white;"> [ <a href="news.html">News</a> ]
[ <a href="#download">Download</a> ] [ <a href="#install">Installation</a>
] [ <a href="#use">Usage</a> ] [ <a href="mailto:drdani@mazsola.iit.uni-miskolc.hu">Mail
to developer</a> ]
<p> </p>
<pre><tt><font size="+1">
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/ ____| (_)
_ _| | ___ _ _ __ ___
| | | | | / __| | '_ ` _ \
| |_| | |____\__ \ | | | | | |
\ ._,_|\_____|___/_|_| |_| |_|
| |
|_|
</font></tt></pre>
<h1>Software simulator for microcontrollers</h1>
<b><i>μCsim</i></b> can be used to simulate microcontrollers. It supports
MCS51 family, AVR core, Z80, HC08, ST7, STM8, TLCS90, XA51 and Padauk. It can
run on Linux, Windows, OSX, BSD, and other systems.<br>
<br>
See <a href="news.html">what's new</a> in current version.<br>
<h2><a name="download">Download</a></h2>
There are two places where you can download <i>μCsim</i> from:<br>
<ol>
<li>SDCC homepage. <i>μCsim</i> is part of the SDCC (Small Device C
Compiler) project. You can download source of SDCC and precompiled
binaries from <a href="http://sdcc.sf.net">http://sdcc.sf.net</a>.</li>
<li><i>μCsim</i> site. Standalone source package is available on the <i>μCsim</i>
web site:<br>
<a href="http://mazsola.iit.uni-miskolc.hu/ucsim/download">http://mazsola.iit.uni-miskolc.hu/ucsim/download</a>
</li>
</ol>
<p><!-- INSTALL --></p>
<h2><a name="install">How to install</a></h2>
UNIX version is distributed in source.
<ol>
<li>Get archive file, uncompress and untar it. These steps will produce a
directory <b>ucsim-X.Y.Z</b> where X.Y.Z is the version number. </li>
<li>Make sure, that following packages are installed on your system: <b>make</b>,
<b>bison</b> (or yacc), <b>flex</b> (or lex), <b>libncurses-dev</b>.
You will need a C and a C++ compiler as well.</li>
<li>Go to the directory and configure the package. Issue <tt><b>configure</b></tt>
command. It will determine your system and produce <b>Makefile</b>.
Installation directory can be specified with <b><tt>--prefix=<i>dir</i></tt></b><!-- -- -->
option to the <tt><b>configure</b></tt>. Default directory is <tt>/usr/local</tt>.
Executable file will be placed in <tt>bin</tt> subdirectory. </li>
<li>Compile the package with <tt><b>make</b></tt> command. </li>
<li>Install executables <b>ucsim_51</b>, <b>ucsim_avr</b>, <b>ucsim_hc08</b>, <b>ucsim_xa</b>,
<b>ucsim_z80, etc.</b> to any directory you want. It can be done with <tt><b>make
install</b></tt> command which will place files in installation
directory specified with <tt><b>--prefix=<i>dir</i></b><!-- --
--></tt> option of <tt><b>configure</b></tt>. Note that you may have to have
special privilege to do this if installation directory is not writable
by you. </li>
</ol>
<!-- USE -->
<h2><a name="use">How to use</a></h2>
<ul>
<li> <a href="invoke.html">Invocation</a>.<br>
Starting the simulator program. </li>
</ul>
<p><b>Features of the simulator</b> </p>
<ul>
<li><a href="analyzer.html">Code analyzer</a>. <br>
The simulator tries to figure out places of valid instructions in code
area.</li>
<li><a href="cpu_types.html">Processor types</a>. <br>
The simulator can simulate different type of microcontrollers. </li>
<li><a href="mulcons.html">Multiple consoles</a>. <br>
The simulator can handle more than one command consoles and accepts
command from multiple sources. It also can be driven by other programs
such as debugger interfaces. </li>
<li><a href="serial.html">Serial interfaces</a>. <br>
The simulator can virtually connect a terminal to serial interface of
the simulated CPU. </li>
<li><a href="memory.html">Memory simulation</a>. <br>
Simulated CPU provides address spaces, storage is simulated by memory
chips, address decoders connects them together. </li>
<li><a href="simif.html">Simulator interface</a>.<br>
This is a special interface which provides services for the simulated
program. This services can be used to control the simulator (for example
run/stop) and access some host features (print, file I/O).</li>
<li><a href="vcd.html">VCD file I/O</a>.<br>
This is a special virtual hardware peripheral which can monitor changes
of a memory location (or a bit in MCS51 where bit address space is
available) and write out changes to a VCD file. It can also be used to
replay events from a VCD file in order to simulate external events.</li>
<li><a href="syntax.html">Command syntax</a> and <a href="cmd.html">command
reference</a>. <br>
The simulator can be controlled via a command line interface. It accepts
simple commands. </li>
</ul>
<p><b>Microcontroller specific features</b> </p>
<ul>
<li><a href="stm8/index.html">STM8</a></li>
</ul>
<h2><a name="dev">Developers</a></h2>
<ul>
<li><a href="testing.html">Regression Testing</a></li>
</ul>
<hr>
<table border="0">
<tbody>
<tr>
<td><a href="mailto:drdani@mazsola.iit.uni-miskolc.hu"><img src="post.jpg"
border="0" align="top"></a></td>
<td><i>© 1997,99 Dániel Drótos, Talker Bt.</i> <br>
<a href="mailto:drdani@mazsola.iit.uni-miskolc.hu">drdani@mazsola.iit.uni-miskolc.hu</a></td>
</tr>
</tbody>
</table>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>&#956;Csim: Invokation</title>
</head>
<body style=" background-color: white;">
<h1>Starting the simulator</h1>
There are separate programs to simulate different microcontroller families:
<p>Intel MCS51 family is simulated by <b>ucsim_51</b> <br>
Philips XA processor is simulated by <b>ucsim_xa</b> <br>
Atmel AVR processor is simulated by <b>ucsim_avr</b> <br>
Zilog Z80 family is simulated by <b>ucsim_z80</b> <br>
Toshiba TLCS90 processor is simulated by <b>ucsim_tlcs</b> <br>
Rabbit family is simulated by <b>ucsim_rxk</b> <br>
Motorola M68HC08 processor is simulated by <b>ucsim_m68hc08</b> <br>
Motorola MC6800 processor is simulated by <b>ucsim_m6800</b> <br>
Motorola MC6809 processor family is simulated by <b>ucsim_m6809</b><br>
Motorola MC68HC11 processor is simulated by <b>ucsim_m68hc11</b> <br>
Motorola MC68HC12 processor is simulated by <b>ucsim_m68hc12</b> <br>
MOS MOS6502 processor is simulated by <b>ucsim_mos6502</b> <br>
ST ST7 processor is simulated by <b>ucsim_st7</b> <br>
ST STM8 family is simulated by <b>ucsim_stm8</b> <br>
Padauk family is simulated by <b>ucsim_pdk</b><br>
p1516 processor is simulated by <b>ucsim_p1516</b>
</p>
<p>The simulator can be started in the following way: </p>
<p><tt><font color="blue">$</font> ucsim_51 [-hHVvPgGwlbB] [-p prompt] [-t CPU] [-X
freq[k|M]] [-R seed] [-C cfg_file] [-e command] [-c file] [-s file] [-S
optionlist] [-I if_optionlist] [-a nr] [-Z portnum] [-k portnum] [-o colorlist] [files...]</tt> </p>
<p>Specified files must be names of Intel hex files. Simulator loads them in
the specified order into the ROM of the simulated system. If the file is
specified without extension, the simulator will try to find intel hex file
(filename extended with .hex), omf file (with .omf) and cdb file (with
.cdb extension). Simulator can interpret content of these SDCC output
files and reads information from them.</p>
<p>Options: </p>
<dl>
<dt><tt><b>-t CPU</b></tt> </dt>
<dd>Type of CPU. Recognized types are different for different simulators,
for example MCS51 simulator recognizes 51, 8051, 8751, C51, 80C51,
87C51, 31, 8031, C31, 80C31, 52, 8052, 8752, C52, 80C52, 87C52, 32,
8032, C32, 80C32, 51R, 51RA, 51RB, 51RC, C51R, C51RA, C51RB, C51RC,
89C51R, 251, C251, DS390, DS390F. Note that recognition of a CPU type as
option does not mean that the simulator can simulate that kind of CPU.
Default type is C51. <br>
DS390 supports Dallas DS80C390 24 bit flat mode, dual-dptr operations,
etc. DS390F is the same as DS390, but it starts already in 24 bit flat
mode (ACON = 0xFA instead of 0xF8). DS390F is needed to run programs
compiled with sdcc -mds390.<br>
<span style="font-family: monospace;">-H</span> option can be used to
list all of recognized CPU types.<br>
See <a href="cpu_types.html">how to select CPU type</a>. </dd>
<dt><tt><b>-X freq[k|M]</b></tt> </dt>
<dd>XTAL frequency is <b>freq</b> Hertz. <b>k</b> or <b>M</b> can be
used to specify frequency in kHZ or MHz. Space is not allowed between
the number and the <b>k</b> or <b>M</b>. Default value is 11059200 Hz.
<a name="coption"></a></dd>
<dt><tt><b>-R seed</b></tt></dt>
<dd>Set seed value for the random number generator.</dd>
<dt><span style="font-family: monospace;"><b>-C cfg_file</b></span></dt>
<dd>Read and execute initial commands from specified file.</dd>
<dt><b><span style="font-family: monospace;">-e command</span></b></dt>
<dd>Execute command at program startup (before config file).</dd>
<dt><a name="coption"><tt><b>-c file</b></tt></a> </dt>
<dd>Open command console on <b>file</b>. Command consoles are on standard
input and output by default. Using this option the console can be opened
on any file for example on the serial interface of the computer. <a name="Zoption"></a></dd>
<dt><a name="Zoption"><tt><b>-Z portnum</b></tt></a> </dt>
<dd>Listen for incoming connections on port <b>portnum</b>. Using this
option <i>&#956;Csim</i> can serve multiple consoles. You can get a console
by simply telnet into machine running <i>&#956;Csim</i> to port <b>portnumber</b>.
This option is not available on platforms which doesn't support BSD
networking. <br>
See <a href="mulcons.html">how to use multiple consoles</a>. </dd>
<dt><tt><b>-k portnum</b></tt></dt>
<dd>Listen for incoming connections on port <b>portnum</b>. When this
port connected, the connection will be attached to simulated UART0.This
option is not useful for other UARTs, so it is better to use the more
general -S option. </dd>
<dt><tt><b>-s file</b></tt> </dt>
<dd>Connect serial interface (UART0) of the simulated microcontroller to
the <b>file</b>. Nothing is used by default which means that characters
transmitted by serial interface of the simulated microcontroller go to
nowhere and it will never receive anything. If you are going to
communicate with serial interface interactively the best idea is to
specify a terminal with -s option. </dd>
<dt><tt><b>-S uart=nr,in=file,out=file,port=nr,iport=nr,oport=nr,raw</b></tt>
</dt>
<dd>Using this option you can specify different files for input and output
streams that <i>&#956;Csim</i> uses to simulate microprocessor's serial
interface. <br>
See <a href="serial.html">more about serial interface simulation</a>. </dd>
<dt><span style="font-family: monospace;"><b>-I
if=memory[address],in=file,out=file</b></span></dt>
<dd>Specify options (as comma separated list) for the simulator interface.
<b>if</b> option turns on the interface and specifies address space and
location for use by the interface. <b>in</b> and <b>out</b> can be
used to specify file names to use for file IO.
<br>See <a href="simif.html">more about simulator interface</a>.</dd>
<dt><tt><b>-p prompt</b></tt> </dt>
<dd>Using this option you can specify any string to be the prompt of
command interpreter, for example:
<pre><font color="blue">$</font> ucsim_51 -p "s51&gt; "
<font color="green">ucsim 0.2.12, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
0s51&gt; </font></pre>
</dd>
<dt><tt><b>-P</b></tt> </dt>
<dd>Prompt will be a null ('\0') character. This feature can be useful for
programs which controls simulator through a pipe. </dd>
<dt><span style="font-family: monospace;"><b>-o colorsetting,...<br>
</b></span></dt>
<dd>List of color settings in form: <span style="font-family: monospace;">what=colspec,...</span>
where <i>what</i> specifies object to be colored and <i>colspec</i> is
: separated list of color options e.g.: prompt=b:white:black (bold white
on black).<br>
<i>what</i> can be:<br>
<ul>
<li><span style="font-family: monospace;">prompt</span> prompt color,</li>
<li><span style="font-family: monospace;">prompt_console</span>
console number in front of the prompt,</li>
<li><span style="font-family: monospace;">command</span> color of
entered command,</li>
<li><span style="font-family: monospace;">answer</span> default color
for answers printed by commands,</li>
<li><span style="font-family: monospace;">result</span> color of
expression result,</li>
<li><span style="font-family: monospace;">dump_address</span> address
color in memory dump (1<sup>st</sup> column)</li>
<li><span style="font-family: monospace;">dump_label</span> label
color in memory dump (2<sup>nd</sup> column)</li>
<li><span style="font-family: monospace;">dump_number</span> color of
numerical part of the dump (3<sup>rd</sup> column)</li>
<li><span style="font-family: monospace;">dump_char</span> color of
textual part of the dump (4<sup>th</sup> column)</li>
<li><span style="font-family: monospace;">error</span> color of error
messages</li>
<li><span style="font-family: monospace;">debug</span> color of debug
messages</li>
<li><span style="font-family: monospace;">ui_mkey</span> menu-key
color on UI display</li>
<li><span style="font-family: monospace;">ui_mitem</span> menu-item
color on UI display</li>
<li><span style="font-family: monospace;">ui_label</span> label color
on UI display</li>
<li><span style="font-family: monospace;">ui_time</span> color of
time-value on UI display</li>
<li><span style="font-family: monospace;">ui_title</span> title color
on UI display</li>
<li><span style="font-family: monospace;">ui_run</span> run-state
color on UI display</li>
<li><span style="font-family: monospace;">ui_stop</span> stop-state
color on UI display</li>
</ul>
<i>colspec</i> can be a rendering option, or a color name. First color
name is used for foreground color and the last one will be the color of
background. Rendering options are:<br>
<ul>
<li><span style="font-family: monospace;">b</span> bold</li>
<li><span style="font-family: monospace;">f</span> faint</li>
<li><span style="font-family: monospace;">i</span> italic</li>
<li><span style="font-family: monospace;">u</span> undelined</li>
<li><span style="font-family: monospace;">d</span> double underlined</li>
<li><span style="font-family: monospace;">c</span> crossed over</li>
<li><span style="font-family: monospace;">o</span> overlined</li>
<li><span style="font-family: monospace;">k</span> or <span style="font-family: monospace;">l</span>
blink</li>
</ul>
Color name can be a predefined name, or an RGB value. Known names are:<br>
<ul>
<li><span style="font-family: monospace;">black</span></li>
<li><span style="font-family: monospace;">bblack</span> (bright black,
this is grey on some terminals)</li>
<li><span style="font-family: monospace;">red</span></li>
<li><span style="font-family: monospace;">bred</span> (bright red)</li>
<li><span style="font-family: monospace;">green</span></li>
<li><span style="font-family: monospace;">bgreen</span> (bright green)</li>
<li><span style="font-family: monospace;">yellow</span></li>
<li><span style="font-family: monospace;">byellow</span> (bright
yellow)</li>
<li><span style="font-family: monospace;">blue</span></li>
<li><span style="font-family: monospace;">bblue</span> (bright blue)</li>
<li><span style="font-family: monospace;">magenta</span></li>
<li><span style="font-family: monospace;">bmagenta</span> (bright
magenta)</li>
<li><span style="font-family: monospace;">cyan</span></li>
<li><span style="font-family: monospace;">bcyan</span> (bright cyan)</li>
<li><span style="font-family: monospace;">white</span></li>
<li><span style="font-family: monospace;">bwhite</span> (bright white)</li>
</ul>
How the named colors appear on the screen depends on the terminal
emulator program.<br>
RGB values can be specified as <span style="font-family: monospace;">#RRGGBB</span>
where components are two character hexadecimal values of the red, green
and blue.<br>
Example (set prompt to blinking bold white on green, and set command to
underlined bright green on black):<br>
<span style="font-family: monospace;">-o
prompt=lb:white:green,command=u:bgreen:black</span></dd>
<dt><b><tt>-l</tt></b></dt>
<dd>Use colors of light theme (default is dark)</dd>
<dt><b><span style="font-family: monospace;">-b</span></b></dt>
<dd>Black &amp; white (non-color) console.</dd>
<dt><tt><b>-B</b></tt></dt>
<dd>Beep on breakpoints. Print out a beep character to the
console when a breakpoint hits.</dd>
<dt><span style="font-family: monospace;"><b>-g</b></span></dt>
<dd>Go, start simulation when the program is loaded.</dd>
<dt><span style="font-family: monospace;"><b>-G</b></span></dt>
<dd>Start simulation when the program is loaded and terminate the
simulator when the simulation stops (maybe on breakpoint).</dd>
<dt><span style="font-family: monospace;"><b>-a nr</b></span></dt>
<dd>Set size of variable space. Default is 256.</dd>
<dt><span style="font-family: monospace;"><b>-w</b></span></dt>
<dd>Writable flash.</dd>
<dt><tt><b>-V</b></tt> </dt>
<dd>Verbose mode. The simulator notifies you about some kind of internal
actions for example interrupts. Messages are printed on command console.
</dd>
<dt><tt><b>-v</b></tt> </dt>
<dd>Print out version number and stop. </dd>
<dt><tt><b>-H</b></tt> </dt>
<dd>Print out types of known CPUs. Names printed out by this option can be
used to determine CPU type using <tt><b>-t</b></tt> option. </dd>
<dt><tt><b>-h</b></tt> </dt>
<dd>Print out a short help about the options and stop. </dd>
</dl>
<hr>
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<html>
<head>
<meta content="text/html; charset=ISO-8859-2" http-equiv="content-type">
<title>Memory simulation in &mu;Csim</title>
</head>
<body>
<h1>Memory simulation in <i>&mu;Csim</i></h1>
Typical microprocessor system can look like this:
<p><img src="cpu-mem.svg" alt="[CPU-memory connection]" border="0"></p>
<h3><a name="address_space">Address space</a></h3>
In our terminology "<b>address space</b>" means a set of:
<ul>
<li>address bus lines </li>
<li>data bus lines </li>
<li>control (read/write) lines</li>
</ul>
Bus lines can be shared by address spaces, in this case number of control
line sets specifies the address spaces.
<p>Microcontrollers usually have more address spaces. Some is used inside
only, some can be used for external memories. </p>
<p>Address space does not store any value. It just specifies range of
addresses by <i>start address</i> (which is not necessarily zero) and <i>size</i>
which the CPU can provide when it tries to access a memory location.</p>
<h3><a name="chip">Memory chip</a></h3>
"<b>Memory chip</b>" is a circuit which can hold values in cells. Cells are
indexed from 0 up to size-1. Each cell stores some (usually 8) bits.
<p><img src="chip.svg" alt="[Memory chip]" border="0"></p>
<h3><a name="address_decoder">Address decoder</a></h3>
Addresses coming from an address space via address bus must be routed to
memory and translated to cell indexes. This is done by the "<b>address
decoder</b>". It listens addresses on the bus and control lines and
enables exactly one memory chip. This way cells of the memory chip appear in
the address space.
<p><img src="decoded.svg" boder="0" alt="[Decoded addresses]"> </p>
<p>It is possible that some addresses are not decoded. Writing to
such an address results data to be lost. Reading of a
non-decoded address results random value. Pullup or pulldown
resistors can be applied to data bus lines to provide a specific
value for read operations. </p>
<p>As it shown above, it is also possible that some cells of a chip is not
mapped to any address. </p>
<h3><a name="shared_chips">Mixed address spaces (shared chips)</a></h3>
Decoder connects an address of an address space to a cell of a
memory chip. Only one cell can be connected to each addresses but
same cell can be connected to more than one address spaces. This
is done by routing different control lines to the same chip
through logic <b>L</b>:
<p><img src="share-chip.svg" alt="[Sharing memchip]" border="0"> </p>
<p>Because each cell of a memory chip uses same read/write
control, in real world it is not possible to share individual
cells of a chip between address spaces. In &mu;Csim simulator we
can define as many address decoders as we want so it is possible
to map any cell to any address. </p>
<h3><a name="banking">Memory banking</a></h3>
<p>Memory banking (or bank-switching) is a method to extend amount
of memory accessible by the CPU. Full amount of the memory which
is available for the CPU at a time is limited by the size if the
address space and can not be enlarged. But the address decoder can
dynamically change the map between some part of addresses and
memory chips. Dynamically mapped part of the address space becomes
<i>banked</i> this way. Banked addresses can be mapped to
different memory chips (or different part of a bigger chip)
according to an extra information called bank
selection. Selection is stored in a register and writable by the
software. Selector register should be at an address which is
non-banked. Selection is defined by a binary coded data, and
size of this data determines how many banks available behind the
banked addresses. Banks can store either code or data but using
them need support by the compiler.
</p>
<p>Banks in separate chips:</p>
<p><img src="bank_multichip.svg" alt="[Banks in multi chips]" border="0"></p>
<p>Banks in a single chip:</p>
<p><img src="bank_bigchip.svg" alt="[Banks in big chip]" border="0"></p>
<h3><a name="banding">Bit banding</a></h3>
<p>Banding...</p>
<hr>
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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>&#956;Csim: Multiple Consoles</title>
</head>
<body bgcolor="white">
<h1>Using multiple consoles</h1>
<h3>Why?</h3>
Using more than one console can be useful if you want to issue a command
during the simulated program is executed.
<h3>How?</h3>
<p>To get multiple consoles you have to execute the simulator in the <i>background</i>
like daemons run in UNIX systems. The simulator then will listen and wait
for network connection requests and provide console functions for network
connections. </p>
<p>To run <i>&#956;Csim</i> in the background you have to use <a href="invoke.html#Zoption">-Z</a>
option for the simulator: </p>
<pre><font color="blue">pigmy$</font> ucsim_51 -Z 5555 foo.hex
</pre> In this case ucsim_51 runs in foreground in your command interpreters point of
view. Of course you can run the program really in the background:
<pre><font color="blue">pigmy$</font> ucsim_51 -Z 5555 foo.hex &amp;
</pre> The parameter of the <a href="invoke.html#Zoption">-Z</a> option is a
port number. This can be number of any unused port of your machine. If the
specified port is already occupied then following message appears:
<pre><font color="blue">pigmy$</font> ucsim_51 -Z 5555
<font color="red">bind: Address already in use</font>
</pre> In this case you have to use an other number.
<p>Let's suppose you have found a free port number and the simulator listens
on it. Now go to somewhere else, at least to an other window and connect
to the simulator: </p>
<pre><font color="blue">other_machine$</font> telnet pigmy 5555
</pre> First parameter to the telnet command is the name of the machine where
the simulator is running on. It can be <tt>localhost</tt> if you are on the
same machine or the fully qualified host name if you are at the other end of
the world. Second parameter is the number of the port where the simulator is
listening. It must be the same number which was specified as parameter of
the <a href="invoke.html#Zoption">-Z</a> option when the simulator was
started (see above).
<p>Connecting to the simulator you get a command console: </p>
<pre><font color="blue">pigmy$</font> telnet pigmy 5555
<font color="green">Trying 127.0.0.1...
Connected to pigmy.talker.bt.
Escape character is '^]'.
ucsim 0.2.21, Copyright (C) 1997 Daniel Drotos, Talker Bt.
ucsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
&gt;
</font>
</pre>
<h3>What to do with it?</h3>
Obviously you can telnet into the simulator as many times as many command
consoles you want. You can start the execution using one console and while
the program is executed you can, for example, modify ports on the other
console.
<h3>Stop</h3>
Using <a href="cmd.html#q">quit (q)</a> command you can not stop the
simulator. It just stops the actual console and the simulator continues to
listen for incoming network connections.
<p>To stop the simulator completely you have to use <a href="cmd.html#kill">kill</a>
command. Note that if you stop the simulator (by kill) then all the active
network connections (all other consoles) will stop. </p>
<h3>Tricks</h3>
You can get a console on the terminal where you started the simulator. To do
this you must explicitly ask the simulator to open a console on the standard
input/output. You can do this using <a href="invoke.html#coption">-c</a>
option and specify the actual terminal as parameter for it:
<pre><font color="blue">pigmy$</font> ucsim_51 -Z 5555 foo.hex -c /dev/tty
</pre>
<hr>
</body>
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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=iso-8859-2">
<title>&#956;Csim: News</title>
</head>
<body>
<h1>News</h1>
<h2>version 0.7</h2>
<ul>
<li>Bugfixes.</li>
<li>New <b style="font-family: monospace;">raw</b> suboption for -S, <a
href="invoke.html">see details</a>.</li>
</ul>
<h2>version 0.6</h2>
<ul>
<li>Command line editing</li>
<li>Command line history</li>
<li>New operators for expr and variables</li>
<li>New simulators: TLCS90, pdk, M6809</li>
<li>New simulators: PicoBlaze, MCS6502, MC6800, Rabbit</li>
<li>Simulator interface</li>
<li>Memory banking</li>
<li>Bit banding</li>
<li>Serial line simulation for STM8</li>
<li>Conditional breakpoints</li>
<li>Breakpoint script</li>
<li>Built-in terminal for UART with simulator control</li>
<li>Built-in display and control for MCS51 ports</li>
<li>Dump changes of values to VCD file</li>
<li>Read information from SDCC outputs: cdb and omf files</li>
<li>Variables</li>
<li>Colors</li>
<li>Execution history</li>
</ul>
<hr>
</body>
</html>

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<html>
<head>
<meta content="text/html; charset=ISO-8859-2" http-equiv="content-type">
</head>
<body><a name="bl">
<h3>bl</h3>
</a>
List breakpoints. This command prints out information about every
fetch and then event breakpoints.
<pre>&gt; <font color="#118811">bl</font>
F 1(1) 000160 c2 CLR P1.0
D 2(2) 000180 02 LJMP 022a
F 1(1) 000006 wi
&gt; </pre>
First character on the list shows permanency of the
breakpoint. <b>F</b> means fix and <b>D</b> means dynamic. Second item
on the list is the hit number associated to breakpoint. After that
between the parentheses there is the actual value of the hit
counter. If hit counter reaches zero, breakpoint is activated and hit
counter is preset with value of hit number. Next item is the
address. Next items are different for fetch and event breakpoints.
<p>Fetch breakpoints list hexadecimal code of instruction at
breakpoint's address and then disassembled instruction.
</p>
<p>Event breakpoints list identification of the event's type.
</p>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>&#956;Csim: Serial Interfaces</title>
</head>
<body style="background-color: white;">
<h1>Using serial interfaces</h1>
<h3>Connecting a terminal</h3>
You can easily connect a terminal to the serial interface of the simulated
microcontroller. This terminal is just a file so it can be anything which is
represented as a file. It even can be a real serial line of the computer:
<pre><font color="blue">$</font> ucsim_51 -s/dev/ttyS1
</pre>
<p><img src="serial_comport.svg"></p>
<p>Of course you must use the actual device name of your operating system.
Device name <tt>ttyS1</tt> above is used in Linux systems. Your system
can use other names. </p>
<p>You can use a terminal of your system. It can be a virtual console if
your system provides such as Linux does for example. On X Windows you can
use <b>xterm</b> windows as terminals, one for running the simulator and
one as a terminal on CPU's serial line. Here is a sample how to do this: </p>
<ol>
<li>Prepare the terminal window which will be connected to the serial
line:
<p></p>
<ul>
<li>Check the device name which represents the terminal:
<pre><font color="blue">$</font> tty
<font color="green">/dev/ttyp1</font>
</pre> </li>
<li>Disconnect the shell from the terminal. Usually I use the <b>tail</b>
command and any existing text file:
<pre><font color="blue">$</font> tail -f $HOME/.profile
</pre> </li>
</ul>
</li>
<li>Run the simulator in the other window:
<pre><font color="blue">$</font> ucsim_51 -s/dev/ttyp1 program.hex
</pre> Use the output of the <b>tty</b> command above as the parameter of the <tt>-s</tt>
option. </li>
</ol>
<p> Every character sent out by the simulated program appears in the
"terminal" window and every character you type in there will be received
by the simulated controller's serial line.</p>
<p><b><i>Notes</i></b></p>
<p>-s option is deprecated, it is recommended to use -S instead. Option -S
provides more features and flexibility but it requires to use different
syntax:</p>
<p>-S subopt1,subopt2,...</p>
<p>Known suboptions are:</p>
<ul>
<li>uart=nr<br>
This option specifies ID of the uart that following options will be
attached to. Default is 0.</li>
<li>in=filename<br>
Specified file will be used as input for the uart. When simulated uart
is able to receive, it will get content of this file.</li>
<li>out=filename<br>
Specified file will be used as output for the uart. When simulated uart
sends a byte, it will be written into this file.</li>
<li>port=nr<br>
Specified port number will be listened for incoming connections (TCP
server) and if connected, the socket will be used as both input and
output for the uart.</li>
<li>iport=nr<br>
Specified port number will be listened for incoming connections (TCP
server) and if connected, the socket will be used as input of the uart.</li>
<li>oport=nr<br>
Specified port number will be listened for incoming connections (TCP
server) and if connected, the socket will be used as output of the uart.</li>
<li>raw<br>
Raw, non-interactive communication will be performed on both input and
output files. Default is interactive (non-raw) mode.</li>
</ul>
Input and output file can be a regular file or a special one, for example
pipe (fifo) or a TCP socket. If a file is a tty, the simulator will assume
that a terminal is connected and will start an interactive session. TCP
socket is treated as a tty, and telnet protocol is used to control the
terminal settings. This can be turned off by <b>raw</b> suboption. If <b>raw</b>
is used, simulator will not perform any terminal control and will not
use/interpret telnet protocol commands.<br>
<br>
<h3>Connecting two instances of simulator</h3>
Executing two instances of the simulator, serial lines of two simulators
(micros) can be connected together so they can talk to each other over their
serial interface. It is because you can specify separate files for serial
input and output. For example you run two simulators "1" and "2", here is
the sample how to connect them:
<p><img src="serial1.svg"> </p>
<ol>
<li>Make two FIFOs to represent physical wires in serial cable connecting
two micros:
<pre><font color="blue">$</font> mkfifo 1-2 2-1 <font color="magenta"># 1-2: 1-&gt;2 and 2-1: 2-&gt;1</font>
</pre> </li>
<li>Start two simulators and specify the FIFOs as input and output of
serial interface:
<pre><font color="blue">term1 $</font> <font color="magenta"># start sim "1"</font>
<font color="blue">term1 $</font> ucsim_51 -Sin=2-1,out=1-2,raw program_1_.hex
<font color="blue">term2 $</font> <font color="magenta"># start sim "2"</font>
<font color="blue">term2 $</font> ucsim_51 -Sout=2-1,in=1-2,raw program_2_.hex
</pre> Because opening a pipe blocks the program until other direction is
opened, the order of arguments above is <b>important</b>!
<p> </p>
</li>
<li>Debug programs as usual. </li>
</ol>
Using the most useful unix commands <b>cat</b> and <b>tee</b> and just
some more FIFOs you can monitor serial communication, here is a sample:
<p><img src="serial2.svg"> </p>
<ol>
<li>Make some FIFOs to use between simulators and tee "monitors":
<pre><font color="blue">$</font> mkfifo 1_tee tee_2 2_tee tee_2
</pre> </li>
<li>Run monitoring programs (in two xterms for example):
<pre><font color="blue">xterm1 $</font> cat 1_tee|tee /dev/tty &gt;tee_2 # monitor 1-&gt;2
<font color="blue">xterm2 $</font> cat 2_tee|tee /dev/tty &gt;tee_1 # monitor 2-&gt;1
</pre> </li>
<li>Now you can start simulators (on two other terminals:)
<pre><font color="blue">xterm3 $</font> ucsim_51 -Sin=tee_1,out=1_tee,raw program_1_.hex
<font color="blue">xterm4 $</font> ucsim_51 -Sin=tee_2,out=2_tee,raw program_2_.hex
</pre> </li>
<li>Start your apps and listen what they are talking about. </li>
</ol>
<hr>
</body>
</html>

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<!DOCTYPE html>
<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=iso-8859-2">
<title>&#956;Csim: Simulator interface</title>
</head>
<body>
<h1>Simulator interface</h1>
<p>Using the simulator interface the simulated program can control the
simulation, it can get information about the interface, stop simulation
and it can do console and file io.<br>
</p>
<p> <img src="sif_work.svg" border="0"></p>
<p>Interface is available behind a memory location, which can be any data
memory location which is readable and writable by the program. Program can
send command to the interface by writing one character command code into
the memory location (although some of them needs parameter) and can read
back answer from the same location.</p>
<p>The interface must be turned on before use. It means that you must
specify the address of the memory location to use. It can be done in two
ways.</p>
<p><b>Using -I option of the simulator program</b></p>
<p>-I option accepts a list of settings in form: setting=value. Know
settings are:</p>
<dl>
<dt><span style="font-family: monospace;">if</span></dt>
<dd>this setting is used to turn on the interface. Its value must be a
memory name and the address, like:<br>
<code>ucsim_51 -I if=xram[0xffff]<br>
</code>memory name must be followed by the address in square brackets.
Address can be specified in decimal, octal or hexadecimal.</dd>
<dt><span style="font-family: monospace;">in</span></dt>
<dd>value specifies name of the file which will be used by READ command.</dd>
<dt><span style="font-family: monospace;">out</span></dt>
<dd>value specifies name of the file which will be used by WRITE command.</dd>
</dl>
<p><b>Configuring virtual simif peripheral</b></p>
<p>If you check hardware elements of simulated processor with <a href="cmd_general.html#conf">conf</a>
commmand, you will see one called <b>simif</b>. Setting of this
peripheral will setup the simulator interface:</p>
<pre>0&gt; <span style="color: #009900;">conf</span>
ucsim version 0.6-pre56
Type of microcontroller: C52 CMOS cmos
Controller has 12 hardware element(s).
on <b>simif[0]</b>
on vcd[0]
on timer0[0]
on timer1[1]
on uart[0]
on dport[0]
on port[0]
on port[1]
on port[2]
on port[3]
on irq[0]
on timer2[2]
0&gt; </pre>
<p>Using info command you can get state of the interface, known commands,
and other information:</p>
<pre>0&gt; <span style="color: #009900;">info hw simif</span>
uCsim simulator interface, version 1, at (null)[0x0]
Active command: none.
Known commands:
0x5f/_ if_detect: Detect existence of interface
0x69/i commands: Get information about known commands
0x76/v if_ver: Get version of simulator interface
0x56/V sim_ver: Get version of simulator
0x40/@ if_reset: Reset interface to default state
0x49/I cmdinfo: Get information about a command
0x68/h cmdhelp: Get help about a command
0x73/s stop: Stop simulation
0x70/p print: Print character
0x78/x print_hex: Print character in hex
0x66/f fin_check: Check input file if input available
0x72/r read input file: Read character from input file
0x77/w write to output file: Write character to output file
Input file:
Output file:
...</pre>
<p>Use <a href="cmd_general.html#set_hardware">set hardware</a> command to
setup the interface:</p>
<pre>0&gt; <span style="color: #009900;">set hw simif</span>
set hardware simif memory address
set hardware simif fin "input_file_name"
set hardware simif fout "output_file_name"
0&gt;
</pre>
<p>To turn on the interface, use following command:</p>
<pre>0&gt; <span style="color: #009900;">set hw simif xram 0xffff</span>
0&gt; <span style="color: #009900;">i h simif</span>
uCsim simulator interface, version 1, at <b>xram[0xffff]</b><br>... </pre>
<p></p>
<p>following commands can be used to specify input and output files:</p>
<pre>0&gt; <span style="color: #009900;">set hw simif fin "infile.txt"</span>
0&gt; <span style="color: #009900;">set hw simif fout "outfile.txt"</span>
0&gt; <span style="color: #009900;">i h simif</span>
...
Input file: <b>infile.txt</b>
Output file: <b>outfile.txt</b>
...
</pre>
<p></p>
<p><b>Access interface from simulated program</b></p>
<p>To access memory content, you have to use C variable. If address is
already known, you can setup a pointer with that address to access the
content:</p>
<pre>#define SIF_ADDRESS_SPACE_NAME "xram"
#define SIF_ADDRESS_SPACE __xdata
#define SIF_ADDRESS 0xffff
volatile unsigned char SIF_ADDRESS_SPACE * sif;<br><br>void
main(void)
{
sif= (unsigned char SIF_ADDRESS_SPACE *) SIF_ADDRESS;
... </pre>
<p></p>
<p>this example can be compiled with SDCC for MSC51 processor. Do not forget
the <b>volatile</b> keyword! You can define names for command characters:</p>
<pre>enum sif_command {
DETECT_SIGN = '!', // answer to detect command
SIFCM_DETECT = '_', // command used to detect the interface
SIFCM_COMMANDS = 'i', // get info about commands
SIFCM_IFVER = 'v', // interface version
SIFCM_SIMVER = 'V', // simulator version
SIFCM_IFRESET = '@', // reset the interface
SIFCM_CMDINFO = 'I', // info about a command
SIFCM_CMDHELP = 'h', // help about a command
SIFCM_STOP = 's', // stop simulation
SIFCM_PRINT = 'p', // print character
SIFCM_FIN_CHECK = 'f', // check input file for input
SIFCM_READ = 'r', // read from input file
SIFCM_WRITE = 'w', // write to output file
};
</pre>
<p></p>
<p><b>Command: detect</b></p>
<p>Command character: _<br>
Answer: !</p>
<p>Following function can be used to detect if the interface is turned on or
not:</p>
<pre>char
detect(void)
{
*sif= SIFCM_DETECT;
return *sif == DETECT_SIGN;
}
</pre>
<p></p>
<p><b>Command: commands</b></p>
<p>Command character: i<br>
Answer: nuof_commands, command_char_1, command_char_2, ...</p>
<p>This command can be used to retrieve all know command characters. First
answer is the number of known commands, further reads will get command
characters. Following example will read all commands:</p>
<pre>int nuof_commands;
unsigned char commands[100];
void
get_commands(void)
{
int i;
*sif= SIFCM_COMMANDS;
nuof_commands= *sif;
for (i= 0; i &lt; nuof_commands; i++)
commands[i]= *sif;
}
</pre>
<p></p>
<p><b>Command: ifver</b></p>
<p>Command character: v<br>
Answer: 1 byte version number</p>
<p>Following simple example is a function which returns the interface
version:</p>
<pre>int
get_ifversion(void)
{
*sif= SIFCM_IFVER;
return(*sif);
}
</pre>
<p></p>
<p><b>Command: simver</b></p>
<p>Command character: V<br>
Answer: string</p>
<p>First byte of the string answer will be the length of the string, and
after the last character a zero byte will arrive. Following function can
be used to read string answer and store it (up to some limited length):</p>
<pre>unsigned char sim_version[15];
void
get_sim_version()
{
unsigned char c, i, n;
*sif= SIFCM_SIMVER;
sim_version[0]= 0;
n= *sif;
if (n)
{
i= 0;
c= *sif;
while (c &amp;&amp; (i&lt;14))
{
sim_version[i++]= c;
c= *sif;
}
while (c)
c= *sif;
sim_version[i]= 0;
}
}
</pre>
<p></p>
<p><b>Command: ifreset</b></p>
<p>Command character: @<br>
Answer: -</p>
<p>This command resets the interface to default state.</p>
<p><b>Command: cmdinfo</b></p>
<p>Command character: I followed by a command character (which you would
like to get info about)<br>
Answer: array</p>
<dl>
<dt>1st byte of the answer</dt>
<dd>full length of the answer</dd>
<dt>2nd byte of the answer</dt>
<dd>number of parameters that the command needs</dd>
<dt>3rd byte of the answer</dt>
<dd>type of the answer that the command replies<br>
<dl>
<dt>0</dt>
<dd>unknown</dd>
<dt>1</dt>
<dd>one byte</dd>
<dt>2</dt>
<dd>array (of bytes): length, followed by bytes</dd>
<dt>3</dt>
<dd>string: length, characters and one zero byte</dd>
<dt>4</dt>
<dd>no answer</dd>
</dl>
</dd>
</dl>
<div><b>Command: cmdhelp</b></div>
<div><br>
</div>
<div>Command character: h followed by a command character (which you would
like to get info about)<br>
Answer: string</div>
<div><br>
</div>
<div>Returns textual information about. Following function prints
information about all commands (retrieved by "i" command, see above):</div>
<div>
<pre>enum sif_answer_type {
SIFAT_UNKNOWN = 0x00, // we don't know...
SIFAT_BYTE = 0x01, // just a byte
SIFAT_ARRAY = 0x02, // array of some bytes
SIFAT_STRING = 0x03, // a string
SIFAT_NONE = 0x04 // no answer at all
};
void
print_cmd_infos(void)
{
int i, j;
unsigned char inf[5];
for (i= 0; i &lt; nuof_commands; i++)
{
printf("Command '%c' info:\n", commands[i]);
*sif= SIFCM_CMDINFO;
*sif= commands[i];
inf[0]= *sif;
for (j= 0; j &lt; inf[0]; j++)
{
inf[j+1]= *sif;
//printf(" 0x%02x", inf[j+1]);
}
printf(" need %d params, answers as ", inf[1]);
switch (inf[2])
{
case SIFAT_UNKNOWN : printf("unknown"); break;
case SIFAT_BYTE : printf("byte"); break;
case SIFAT_ARRAY : printf("array"); break;
case SIFAT_STRING : printf("string"); break;
case SIFAT_NONE : printf("none"); break;
}
printf(": ");
*sif= SIFCM_CMDHELP;
*sif= commands[i];
if (*sif)
{
j= *sif;
while (j)
{
putchar(j);
j= *sif;
}
}
printf("\n");
}
}
</pre> </div>
<div><br>
</div>
<div><b>Command: stop</b></div>
<div><br>
</div>
<div>Command character: s<br>
Answer: -</div>
<div><br>
</div>
<div>Sending this command stops the simulation.</div>
<div><br>
</div>
<div><b>Command: print</b></div>
<div><br>
</div>
<div>Command character: p followed by a character to print<br>
Answer: -</div>
<div><br>
</div>
<div>This command can be used to print out a character on the simulator
console. Following functions can be used to print a character and a
string:</div>
<div>
<pre>void
sif_putchar(char c)
{
*sif= SIFCM_PRINT;
*sif= c;
}
void
sif_print(char *s)
{
while (*s)
sif_putchar(*s++);
}
</pre> </div>
<div><br>
</div>
<div><b>Command: fin_check</b></div>
<div><br>
</div>
<div>Command character: f</div>
<div>Answer: 0 (if input file is not readable), or 1 (if input file is
readable)</div>
<div><br>
</div>
<div>This command checks if the input file is readable or not.Here is a
simple function which can be used to check readability of the input file:</div>
<div>
<pre>char
sif_fin_avail()
{
return sif_get(SIFCM_FIN_CHECK);
}
</pre><br>
</div>
<div><b>Command: read</b></div>
<div><br>
</div>
<div>Commad character: r</div>
<div>Answer: next byte from input file</div>
<div><br>
</div>
<div>This command can be used to read next byte from the input file.
Remember, name of the input file must be set before use.</div>
<div><br>
</div>
<div>Following demonstration code prints out content of the input file:</div>
<div>
<pre>void
fin_demo()
{
char i, c;
printf("Reading input from SIMIF input file:\n");
while (i= sif_fin_avail())
{
c= sif_read();
if (c &gt; 31)
putchar(c);
}
printf("\nRead demo finished\n");
}
</pre></div>
<div><b>Command: write</b></div>
<div><br>
</div>
<div>Command character: w, followed by a byte to write to output file</div>
<div>Answer: -</div>
<div><br>
</div>
<div>Following function can be used to write a string to the output file:</div>
<div>
<pre>void
fout_demo(char *s)
{
while (*s)
{
*sif= SIFCM_WRITE;
*sif= *s++;
}
}
</pre>Do not forget to specify name of the output file via setting of the
simulator interface. Be careful, simulator will overwrite content of the
output file!<br>
</div>
<hr>
</body>
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en-GB" lang="en-GB">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
<title>Features of the STM8 Simulator</title>
</head>
<body>
<h1>Features of the STM8 Simulator</h1>
<h2>Cycle Counts</h2>
Instruction timings are correct and take into account pipeline overlaps
and stall cycles. The only known exceptions are HALT, WFI and WFE which
are either not yet implemented or, in the case of HALT, only partially
and minimally implemented.
<h3>Notes on Documention</h3>
<h4>PM0044 Section 5.3 Pipelined execution examples</h4>
<p>There are some errors in these tables. See the trace outputs in the
<a href="#exanal">Example Analyses</a> section below for details.</p>
<h4>PM0044 Section 7.4 Instruction Set</h4>
<p>The cycle counts shown for instructions in PM0044 section 7 are one less
than the actual counts because the first decode cycle of an instruction
normally overlaps with the last execution cycle of the preceding
instruction.</p>
<h3>Stall Cycle Detection</h3>
<p>Error/warning event reporting of stall cycles is available should timings
be important in your application.
<pre>0&gt; <font color="#118811">show error</font>
Error: non-classified [on/ON]
[...]
Error: stm8 [off/OFF]
Warning: pipeline [unset/OFF]
Warning: decode_stall [unset/OFF]
Warning: fetch_stall [unset/OFF]
[...]</pre>
<p>These are off by default but may be enabled as required either as a group:
<pre>0&gt; <font color="#118811">set error pipeline</font></pre>
or individually:
<pre>0&gt; <font color="#118811">set error decode_stall on</font>
0&gt; <font color="#118811">set error fetch_stall on</font></pre>
</p>
<h3>Cycle and Pipeline Analysis</h3>
<p>The simulator is able to generate detailed analyses of execution showing timings
for each instruction executed including pipeline overlaps and stalls. This is controlled
via the <em>pipetrace</em> feature of the STM8 CPU module. The output is in the form
of a self-contained HTML document that can be opened with a browser or imported into
other application documentation.</p>
<p>To generate a pipeline analysis:</p>
<ul>
<li>Set the title for the next pipetrace to be opened.
<pre>0&gt; <font color="#118811">set hw cpu pipetrace title "..."</font></pre>
</li>
<li>Replace the embedded default styling with a stylesheet link to the given URL.
<pre>0&gt; <font color="#118811">set hw cpu pipetrace style "<i>url</i>"</font></pre>
</li>
<li>Open the given file, write the header (including title and stylesheet) and
continue writing the pipeline analysis as instructions are executed.
<pre>0&gt; <font color="#118811">set hw cpu pipetrace start "<i>path</i>"</font></pre>
</li>
<li>Set folding of the analysis on (the default) or off. Folding causes the cycle
count to be reset to zero (moving the output back to the left) after every
pipeline flush (i.e. after every branch, jump or call). It is recommended you
leave this on unless you have <em>very</em> wide paper or are single stepping
and annotating the analysis between steps.
<pre>0&gt; <font color="#118811">set hw cpu pipetrace fold [on|off]</font></pre>
</li>
<li>Pause writing the pipeline analysis. The output file remains open but nothing
will be written to as instructions are executed.
<pre>0&gt; <font color="#118811">set hw cpu pipetrace pause</font></pre>
</li>
<li>Insert the given text into the current pipeline analysis. The text is
inserted verbatim and may contain HTML markup. If the output is not
paused the cycle count for the analysis is set back to zero so that the
next instruction output will be moved back to the left (the first cycle
after the inserted text does however overlap the last cycle before the
inserted text as normal).
<pre>0&gt; <font color="#118811">set hw cpu pipetrace data "<i>text</i>"</font></pre>
</li>
<li>Resume a paused pipeline analysis. Instruction execution will update the
analysis output again. Resuming a paused analysis resets the cycle count
to zero so that the next instruction output is moved back to the left.
(The next cycle may or may not overlap the last cycle before the pause
depending on whether or not any instructions were executed while the
output was paused.)
<pre>0&gt; <font color="#118811">set hw cpu pipetrace resume</font></pre>
</li>
<li>Stop the pipeline analysis and close the output file. No further analysis will
occur until a new analysis file is started.
<pre>0&gt; <font color="#118811">set hw cpu pipetrace stop</font></pre>
</li>
</ul>
<a name="exanal"></a>
<h3>Example Analyses</h3>
<h4>Documented Examples</h4>
<p>These are taken from the examples in ST's &ldquo;PM0044 Programming Manual&rdquo;
section &ldquo;5.3 Pipelined execution examples&rdquo; and are generated by
the test <a href="test.asm">stm8.src/test/stm8-cycles/test.asm</a>
using the &ldquo;pipetrace&rdquo;functionality described above.</p>
<p>Note that there are some errors in the examples in section 5.3. These are noted in
the output below and the differences confirmed on HW.</p>
<ul>
<li><a href="test.table3.html">
PM0044 5.4 Table 3. Example with exact number of cycles
</a>
<li><a href="test.table6.html">
PM0044 5.4.1 Table 8. Optimized pipeline example - execution from Flash
</a>
<li><a href="test.table8.html">
PM0044 5.4.2 Table 6. Optimized pipeline example - execution from RAM
</a>
<li><a href="test.table10.html">
PM0044 5.4.3 Table 10. Pipeline with Call/Jump
</a>
<li><a href="test.table12.html">
PM0044 5.4.4 Table 12. Example of stalled pipeline
</a>
</ul>
<h4>Additional Examples</h4>
<p>The DIV instruction is special in that it takes a variable number of cycles and
is interruptible.</p>
<ul>
<li><a href="test.div.html">
Examples of DIV execution
</a>
<li><a href="test.int_div.html">
Examples of interrupted DIV execution
</a> (not currently implemented)
</ul>
<p>Other instructions, each run individually starting from an empty pipeline and
showing the overlap with the following instruction.</p>
<ul>
<li><a href="test.instrs.html">
Examples of individual instruction execution
</a>
</ul>
<h3>Hardware Cycle Counting</h3>
<p>Actual cycle counts may be obtained from hardware for comparison using a combination
of <a href="https://stm8-binutils-gdb.sourceforge.io">stm8-gdb</a>, openocd and an STLink
or other openocd/SWIM compatible debugger. Set the master and CPU clocks to be equivalent
and use one of the target's timers to count cycles.</p>
<p>For instance:</p>
<blockquote><pre>
$ openocd -f interface/stlink.cfg -f target/stm8s003.cfg &amp;
$ stm8-gdb
[...]
(gdb) target extended-remote :3333
(gdb) set $DM_CSR2 = 0x7f99
(gdb) set $DM_ENFCTR = 0x7f9a
(gdb) set $CLK_CKDIVR = 0x50c6
(gdb) set $CLK_PCKENR1 = 0x50c7
(gdb) set $TIM2_CR1 = 0x5300
(gdb) set $TIM2_EGR = 0x5306
(gdb) set $TIM2_CNTRH = 0x530c
(gdb) set $TIM2_CNTRL = 0x530d
(gdb) set $TIM2_PSCR = 0x530e
(gdb) define cycles
dont-repeat
# Freeze TIM2 when CPU is stalled by DM
set {unsigned char}$DM_ENFCTR = 0xfd
# Set HSIDIV = 0, CPUDIV = 0
set {unsigned char}$CLK_CKDIVR = 0x00
# Set TIM2 prescalar to 0 so f_CK_CNT matches f_MASTER (and hence f_CPU)
set {unsigned char}$TIM2_PSCR = 0x00
# Clear count and update config
set {unsigned char}$TIM2_EGR = 1
set {unsigned char}$TIM2_CNTRH = 0xff
set {unsigned char}$TIM2_CNTRL = 0xff
# Enable counter
set {unsigned char}$TIM2_CR1 = 0x01
# Enable clock gate
set {unsigned char}$CLK_PCKENR1 = 0x20
# Set PC
# N.B. Do not attempt to flush the decoder by writing to DM_CSR2. It upsets
# openocd which is then unable to set breakpoints.
set $pc = $arg0
#set {unsigned char}$DM_CSR2 = 0x81
# Set a HW breakpoint, run, then clear
monitor bp $arg1 1 hw
cont
monitor rbp $arg1
set $_tmp = {unsigned short}$TIM2_CNTR
disass/r $arg0,$arg1
printf "%u cycles\n", $_tmp
end
(gdb) document cycles
Set PC to the first address, set a HW break at the second address,
run and report how many cycles (as reported by $TIM2_CNTR) it took.
The target is assumed to be halted initially.
end
(gdb) monitor reset halt
target halted due to debug-request, pc: 0x00008000
(gdb) x/3i 0x811c
0x811c: ldw X,#0xfc00 ;0xfc00
0x811f: ld A,#0x80 ;0x80
0x8121: div X,A
(gdb) cycles 0x811c 0x8122
target halted due to debug-request, pc: 0x00008000
breakpoint set at 0x00008122
Program received signal SIGTRAP, Trace/breakpoint trap.
0x00008122 in ?? ()
Dump of assembler code from 0x811c to 0x8122:
0x0000811c: ae fc 00 ldw X,#0xfc00 ;0xfc00
0x0000811f: a6 80 ld A,#0x80 ;0x80
0x00008121: 62 div X,A
End of assembler dump.
14 cycles
</pre></blockquote>
<p>Don't forget that there will be an initial pipeline fetch cycle
before the first instruction can be decoded, there may be stall
cycles, multiple instructions (mostly) overlap by one cycle (which is
assumed in the timings given by PM0044), and you may have interrupts
that should be disabled.</p>
</body>
</html>

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; For an STM8S003
TIM4_CR1 =: 0x5340
TIM4_IER =: 0x5343
TIM4_EGR =: 0x5345
TIM4_ARR =: 0x5348
.macro codebndry
.$.end =: .
.bndry 4
.$.diff =: . - .$.end
. = . - .$.diff
.rept .$.diff
nop
.endm
.endm
.macro areabndry n
.$.end =: .
.bndry n
.ifne . - .$.end
. = . - 1
.byte 0
.endif
.endm
.area _CODE (REL,CON)
int reset
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
int no_action
no_action:
iret
codebndry
.area INITIALIZER (REL,CON)
.area CODE (REL,CON)
codebndry
reset:
; PM0044 5.4 Conventions, table 3
; N.B. PM004 cannot be right. Table 3 disagrees with the section 7 documentation for ADDW.
; Table 4 has cycle counts for ADDW that disagree with the time graph on the right.
jra table3
codebndry
table3: ldw x,[0x50]
addw x,#20
ld a,[0x30]
table3_end:
; PM0044 5.4.1 Optimized pipeline example, table 6
; N.B. Table 6 has the final F3 load one cycle too early surely?
jra table6
codebndry
table6: neg a
xor a, 0x10
ld a, #20
sub a, 0x1000
inc a
ld xl, a
srl a
swap a
sla 0x15
cp a, #0xfe
mov 0x100, #11
mov 0x101, #22
table6_end:
; PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8 (requires copy to RAM)
table8_copy:
ldw x, #table8_end - table8_start
jreq table8_copy_end
table8_copy_loop:
ld a, (table8_start - 1, x)
ld (0x100 - 1, x), a
decw x
jrne table8_copy_loop
table8_copy_end:
call 0x100
codebndry
.area INITIALIZER
codebndry
table8_start:
jra table8
codebndry
table8: neg a
xor a, 0x10
ld a, #20
sub a, 0x1000
inc a
ld xl, a
srl a
swap a
sla 0x15
cp a, #0xfe
ret
table8_end:
codebndry
.area CODE
codebndry
; PM0044 5.4.3 Pipeline with Call/Jump, table 10
jra table10
codebndry
table10:
inc a
jp label
ldw x, [0x5432]
label: neg a
call label2
ldw x, [0x5432]
ldw x, [0x7895]
label2: incw x
table10_end:
; PM0044 5.4.4 Pipeline stalled, table 12
clr a
ld 0x10, a
ld 0x20, a ; Table 12 doesn't include any setup...
jra table12
codebndry
table12:
sub sp, #20
ld a, #20
btjt 0x10, #5, to ; Table 12 assumes not taken
inc a
btjf 0x20, #3, to ; Table 12 assumes taken
nop
ldw x, [0x5432]
ldw x, [0x1234]
to: incw y
ld a, (x)
table12_end:
; DIV tests - available ST docs simply say "2-17 cycles"
.macro timed_div dividend divisor ?aligned
jra aligned
codebndry
aligned:
ldw x, #dividend
ld a, #divisor
div x, a
end_'aligned:
.endm
timed_div 0x8000,0x80
timed_div 0x8000,0x40
timed_div 0x8000,0x20
timed_div 0x8000,0x10
timed_div 0x8000,0x08
timed_div 0x8000,0x04
timed_div 0x8000,0x02
timed_div 0x8000,0x01
timed_div 0x8000,0x80
timed_div 0x4000,0x80
timed_div 0x2000,0x80
timed_div 0x1000,0x80
timed_div 0x0800,0x80
timed_div 0x0400,0x80
timed_div 0x0200,0x80
timed_div 0x0100,0x80
timed_div 0x0080,0x80
timed_div 0x0040,0x80
timed_div 0x0020,0x80
timed_div 0x0010,0x80
timed_div 0x0008,0x80
timed_div 0x0004,0x80
timed_div 0x0002,0x80
timed_div 0x0001,0x80
timed_div 0x0000,0x80
timed_div 63, 8
timed_div 64, 8
timed_div 65, 8
.macro timed_divw dividend divisor ?aligned
jra aligned
codebndry
aligned:
ldw x, #dividend
ldw y, #divisor
divw x, y
end_'aligned:
.endm
timed_divw 0x8000, 1
; Interrupted div
jra test_idiv
codebndry
test_idiv:
bset TIM4_IER, #0
bset TIM4_EGR, #0
mov TIM4_ARR, #8
ldw x, #255
ld a, #10
mov TIM4_CR1, #0x0f
div x, a
; Exercising all code in stm8.cc + inst.cc
.macro timed_op op operand1 operand2a operand2b ?aligned
jra aligned
codebndry
aligned:
.narg .narg
.ifeq .narg - 4
op operand1,operand2a,operand2b
.else
.ifeq .narg - 3
op operand1,operand2a
.else
.ifeq .narg - 2
op operand1
.else
op
.endif
.endif
.endif
end_'aligned:
.endm
; a, shortmem, longmem,
; (X), (shortoff,X), (longoff,X)
; (Y), (shortoff,Y), (longoff,Y)
; (shortoff,SP)
; ([shortptr.w],X), ([longptr.w],X)
; ([shortptr.w],X), ([longptr.w],X)
; ([shortptr.w],Y)
.macro timed_class_1 op
timed_op op a
timed_op op 0xf5
timed_op op 0xf5c2
.irp reg,X,Y
timed_op op (reg)
timed_op op (0xf5,reg)
timed_op op (0xf5c2,reg)
.endm
timed_op op (0xf5,SP)
timed_op op [0xf5]
timed_op op [0xf5c2]
timed_op op ([0xf5],X)
timed_op op ([0xf5c2],X)
timed_op op ([0xf5],Y)
.endm
; a <- #byte, shortmem, longmem,
; (X), (shortoff,X), (longoff,X)
; (Y), (shortoff,Y), (longoff,Y)
; (shortoff,SP)
; ([shortptr.w],X), ([longptr.w],X)
; ([shortptr.w],X), ([longptr.w],X)
; ([shortptr.w],Y)
.macro timed_class_2 op
timed_op op a,#0x55
timed_op op a,0x10
timed_op op a,0x1000
.irp reg,X,Y
timed_op op a,(reg)
timed_op op a,(0x10,reg)
timed_op op a,(0x1000,reg)
.endm
timed_op op a,(0x10,SP)
timed_op op a,[0x10]
timed_op op a,[0x1000]
timed_op op a,([0x10],X)
timed_op op a,([0x1000],X)
timed_op op a,([0x10],Y)
.endm
; SP <- #byte
.macro timed_class_sp_imm op
timed_op op sp,#0x55
.endm
; X, Y
.macro timed_class_xy op
timed_op op X
timed_op op Y
.endm
; Bit addressed
.macro timed_class_bit op
timed_op op 0x1000,#2
.endm
; Inherent
.macro timed_class_inh op
timed_op op
.endm
timed_class_2 adc
timed_class_2 add
timed_op addw X,#0x1000
timed_op addw X,0x1000
timed_op addw X,(0x10,SP)
timed_op addw Y,#0x1000
timed_op addw Y,0x1000
timed_op addw Y,(0x10,SP)
timed_class_sp_imm addw
timed_class_2 and
timed_class_bit bccm
timed_class_2 bcp
timed_class_bit bcpl
;break
timed_class_bit bres
timed_class_bit bset
;btjf - covered by table 12 above
;btjt - covered by table 12 above
;call - uses common fetchea code
;callf
;callr
timed_class_inh ccf
timed_class_1 clr
timed_class_xy clrw
timed_class_2 cp
timed_op cpw X,#0x55
timed_op cpw X,0x10
timed_op cpw X,0x1000
timed_op cpw X,(Y)
timed_op cpw X,(0x10,Y)
timed_op cpw X,(0x1000,Y)
timed_op cpw X,(0x10,SP)
timed_op cpw X,[0x10]
timed_op cpw X,[0x1000]
timed_op cpw X,([0x10],Y)
timed_op cpw Y,([0x1000],X)
timed_class_1 cpl
timed_class_xy cplw
timed_class_1 dec
timed_class_xy decw
; ;div - covered above
; ;divw - covered above
timed_op exg a,xl
timed_op exg a,yl
timed_op exg a,0x1000
timed_op exgw x,y
;halt
timed_class_1 inc
timed_class_xy incw
;int
;iret
;jp -covered by table 10 above
;jpf
;jra
;jrxx
timed_class_2 ld
timed_op ld 0x10,a
timed_op ld 0x1000,a
timed_op ld (X),a
timed_op ld (0x10,X),a
timed_op ld (0x1000,X),a
timed_op ld (Y),a
timed_op ld (0x10,Y),a
timed_op ld (0x1000,Y),a
timed_op ld (0x10,SP),a
timed_op ld [0x10],a
timed_op ld [0x1000],a
timed_op ld ([0x10],X),a
timed_op ld ([0x1000],X),a
timed_op ld ([0x10],Y),a
timed_op ldf a,0x500000
timed_op ldf a,(0x500000,X)
timed_op ldf a,(0x500000,Y)
timed_op ldf a,([0x5000],X)
timed_op ldf a,([0x5000],Y)
timed_op ldf a,[0x5000]
timed_op ldw X,#0x55
timed_op ldw X,0x10
timed_op ldw X,0x1000
timed_op ldw X,(X)
timed_op ldw X,(0x10,X)
timed_op ldw X,(0x1000,X)
timed_op ldw X,(0x10,SP)
timed_op ldw X,[0x10]
timed_op ldw X,[0x1000]
timed_op ldw X,([0x10],X)
timed_op ldw X,([0x1000],X)
timed_op mov 0x8000,#0xAA
timed_op mov 0x80,0x10
timed_op mov 0x8000,0x1000
timed_op mul x,a
timed_class_1 neg
timed_class_xy negw
timed_op nop
timed_class_2 or
;pop
;popw
;push
;pushw
timed_class_inh rcf
;ret
;retf
; timed_class_inh rim
timed_class_1 rlc
timed_class_xy rlcw
timed_class_xy rlwa
timed_class_1 rrc
timed_class_xy rrcw
timed_class_xy rrwa
timed_class_inh rvf
timed_class_2 sbc
timed_class_inh scf
; timed_class_inh sim
timed_op subw X,#0x5500
timed_op subw X,0x1000
timed_op subw X,(0x10,SP)
timed_op ldw Y,X
timed_op ldw 0x10,X
timed_op ldw 0x1000,X
timed_op ldw (X),Y
timed_op ldw (0x10,X),Y
timed_op ldw (0x1000,X),Y
timed_op ldw (0x10,SP),X
timed_op ldw [0x10],X
timed_op ldw [0x1000],X
timed_op ldw ([0x10],X),Y
timed_op ldw ([0x1000],X),Y
timed_class_1 sla
timed_class_xy slaw
timed_class_1 sll
timed_class_xy sllw
timed_class_1 sra
timed_class_xy sraw
timed_class_1 srl
timed_class_xy srlw
timed_class_2 sub
timed_class_sp_imm sub
timed_class_1 swap
timed_class_xy swapw
timed_class_1 tnz
timed_class_xy tnzw
;trap
;wfe
;wfi
timed_class_2 xor
dividend = 0x8000
.rept 15
timed_div dividend,0x02
dividend = dividend >> 1
.endm
dividend = 0x10000
.rept 15
timed_div dividend-1,0x02
dividend = dividend >> 1
.endm
timed_div 0x2000 0x02
timed_div 0x2040 0x02
timed_div 0x2048 0x02
timed_div 0x2148 0x02
timed_div 0x21c8 0x02
timed_div 45831 94
end:
halt
.area _DATA

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<html>
<head>
<title>DIV tests - available ST docs simply say '2-17 cycles'</title>
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<h1>DIV tests - available ST docs simply say '2-17 cycles'</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<p>The stated cycle count would seem to imply binary long division and
this is how the STM8 emulator in ucsim currently treats div for.
cycle counting. However the cycles measured on actual hardware
suggest this is not correct.
</p>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08100</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08103</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08105</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08108</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0810b</td><td class="instr">ld A,#0x40</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0810d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08110</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08113</td><td class="instr">ld A,#0x20</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08115</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08118</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0811b</td><td class="instr">ld A,#0x10</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0811d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08120</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08123</td><td class="instr">ld A,#0x08</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08125</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08128</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0812b</td><td class="instr">ld A,#0x04</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0812d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08130</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08133</td><td class="instr">ld A,#0x02</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08135</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08138</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0813b</td><td class="instr">ld A,#0x01</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0813d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08140</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08143</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08145</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08148</td><td class="instr">ldw X,#0x4000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0814b</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0814d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08150</td><td class="instr">ldw X,#0x2000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08153</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08155</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08158</td><td class="instr">ldw X,#0x1000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0815b</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0815d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08160</td><td class="instr">ldw X,#0x0800</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08163</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08165</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08168</td><td class="instr">ldw X,#0x0400</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0816b</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0816d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08170</td><td class="instr">ldw X,#0x0200</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08173</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08175</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08178</td><td class="instr">ldw X,#0x0100</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0817b</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0817d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08180</td><td class="instr">ldw X,#0x0080</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08183</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08185</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08188</td><td class="instr">ldw X,#0x0040</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0818b</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0818d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08190</td><td class="instr">ldw X,#0x0020</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08193</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08195</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08198</td><td class="instr">ldw X,#0x0010</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0819b</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0819d</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081a0</td><td class="instr">ldw X,#0x0008</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081a3</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081a5</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081a8</td><td class="instr">ldw X,#0x0004</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081ab</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081ad</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081b0</td><td class="instr">ldw X,#0x0002</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081b3</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081b5</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081b8</td><td class="instr">ldw X,#0x0001</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081bb</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081bd</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081c0</td><td class="instr">ldw X,#0x0000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081c3</td><td class="instr">ld A,#0x80</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081c5</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081c8</td><td class="instr">ldw X,#0x003f</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081cb</td><td class="instr">ld A,#0x08</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081cd</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081d0</td><td class="instr">ldw X,#0x0040</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081d3</td><td class="instr">ld A,#0x08</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081d5</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081d8</td><td class="instr">ldw X,#0x0041</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081db</td><td class="instr">ld A,#0x08</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081dd</td><td class="instr">div X,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th>
</thead>
</table>
</a>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x081e0</td><td class="instr">ldw X,#0x8000</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x081e3</td><td class="instr">ldw Y,#0x0001</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E"></td><td class=" E" /></tr>
<tr><td>0x081e7</td><td class="instr">divw X,Y</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th>
</thead>
</table>
</a>
</body>
</html>

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OperatingSystem/.unused/cmon/sdcc/share/doc/ucsim/stm8/test.int_div.html Normal file
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<html>
<head>
<title>Interrupted div</title>
<script>
function toggle(id) {
var obj = document.getElementById(id);
if (obj.style.display === 'none')
obj.style.display = 'block';
else
obj.style.display = 'none';
}
</script>
<style>
.pipetrace { margin: 1em 0; }
.pipetrace, .pipetrace td { border: 1px solid black; border-collapse: collapse; padding: 0 0.2em; white-space: nowrap; }
.pipetrace thead { background-color: #d2d2d2; position: sticky; top: 0; }
.pipetrace thead th { border: none; box-shadow: inset -1px -1px #000; }
.pipetrace tr:nth-child(even) { background-color: #f2f2f2; }
.pipetrace td { min-width: 1.6em; }
.pipetrace td.instr:before { content: ""; }
.pipetrace td.instr { width: 9.5em; }
.pipetrace td.Sbus:before { content: " S₀"; }
.pipetrace td.Sfetch:before { content: " S₁"; }
.pipetrace td.Sraw:before { content: " S₂"; }
.pipetrace td:before { content: attr(class); }
.pipetrace td.D { background-color: lawngreen; }
.pipetrace td.E { background-color: navajowhite; }
.pipetrace td.Sbus { background-color: red; }
.pipetrace td.Sfetch { background-color: red; }
.pipetrace td.Sraw { background-color: red; }
.pipetrace td.X, .pipetrace td.Flushed { background-color: red; }
.pipetrace td span:after { content: attr(class); }
.pipetrace td span { padding: 0 0.2em; margin: 0 0 0 0.1em; }
.pipetrace td span.FS { background-color: lightgrey; }
.pipetrace td span.F { background-color: lightskyblue; }
#pipetrace_legend { border: none; background-color: white; position: fixed; bottom: 0; right: 0; }
#pipetrace_legend tr:first-of-type { font-weight: bold; }
#pipetrace_legend td { text-align: center; }
#pipetrace_legend td.defn { text-align: left; }
#pipetrace_legend td.defn:before { content: ""; }
</style>
</head>
<body onload="toggle('pipetrace_legend')">
<h1>Interrupted div</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<p>(Not currently implemented.)</p>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td>0x08201</td><td class="instr">div X,A</td><td class=" D"></td><td class=" E"></td><td class=" E"></td><td class=" E"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th>
</thead>
</table>
</a>
</body>
</html>

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<html>
<head>
<title>PM0044 5.4.3 Pipeline with Call/Jump, table 10</title>
<script>
function toggle(id) {
var obj = document.getElementById(id);
if (obj.style.display === 'none')
obj.style.display = 'block';
else
obj.style.display = 'none';
}
</script>
<style>
.pipetrace { margin: 1em 0; }
.pipetrace, .pipetrace td { border: 1px solid black; border-collapse: collapse; padding: 0 0.2em; white-space: nowrap; }
.pipetrace thead { background-color: #d2d2d2; position: sticky; top: 0; }
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#pipetrace_legend td.defn:before { content: ""; }
</style>
</head>
<body onload="toggle('pipetrace_legend')">
<h1>PM0044 5.4.3 Pipeline with Call/Jump, table 10</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<p>PM0044 table 10 shows a fetch stall in the first execution cycle
of the call (cycle 7) however it should be possible for a fetch
to take place since pushing the return address only busies the
data bus (and STM8 is a Harvard architecture with unified address
space so the data and program are separate buses).</p>
<p>Also note that since the flush happens on the last execute cycle
of the call (unlike the jp) there is no overlap and we mark
the following cycle as a decode stall. Technically this is correct
but table 10 does not and says the call takes 3 cycles which
ignores the unavoidable stall cycle. The later instruction documentation
for call says it takes 4 cycles which is presumed to include the
stall cycle that follows it.</p>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x080c4</td><td class="instr">inc A</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080c5</td><td class="instr">jp 0x80cc</td><td class="" /><td class="" /><td class=" D X"></td><td class=" E" /></tr>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x080cc</td><td class="instr">neg A</td><td class="" /><td class="" /><td class="" /><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080cd</td><td class="instr">call 0x80d8</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E X" /></tr>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x080d8</td><td class="instr">incw X</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=""></td><td class=" D Sfetch"><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th><th class="n">10</th><th class="n">11</th>
</thead>
</table>
</a>
</body>
</html>

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<html>
<head>
<title>PM0044 5.4.4 Pipeline stalled, table 12</title>
<script>
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<body onload="toggle('pipetrace_legend')">
<h1>PM0044 5.4.4 Pipeline stalled, table 12</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<h2>Errata</h2>
<ul>
<li>Table 12 shows the BTJT as taking 1 decode, 2 execute cycles but the
later documention for the instruction implies the second execution
cycle is only used if the branch is taken - and this isn't.
</li>
<li>Table 12 has a jump in time (cycles) from 4 straight to 7.
</li>
<li>The last instruction is shown one cycle early in table 12. The decode stall
should line up with the execution cycle of the previous instruction
as the description above the table says.
</li>
</ul>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x080e0</td><td class="instr">sub SP,#0x14</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080e2</td><td class="instr">ld A,#0x14</td><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080e4</td><td class="instr">btjt 0x0010,#5,0x80f8</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080e9</td><td class="instr">inc A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080ea</td><td class="instr">btjf 0x0020,#3,0x80f8</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E X"></td><td class=" E" /></tr>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x080f8</td><td class="instr">incw Y</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080fa</td><td class="instr">ld A,(X)</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D Sraw"><span class="F" /></td><td class=" D"></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th><th class="n">10</th><th class="n">11</th><th class="n">12</th>
</thead>
</table>
</a>
</body>
</html>

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<html>
<head>
<title>PM0044 5.4 Conventions, table 3</title>
<script>
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var obj = document.getElementById(id);
if (obj.style.display === 'none')
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<body onload="toggle('pipetrace_legend')">
<h1>PM0044 5.4 Conventions, table 3</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<h2>Errata</h2>
<ul>
<li>The LDW shown in PM0044 table 3 is missing a decode cycle.
<br/>
(Confirmed on HW)
</li>
<li>The ADDW shown in PM0044 table 3 has one too many decode cycles.
<br/>
(Confirmed on HW)
</li>
<li>The LD shown in PM0044 table 3 is missing a decode cycle.
</ul>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x0808c</td><td class="instr">ldw X,[0x50.w]</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" D"></td><td class=" D"></td><td class=" D"></td><td class=" E" /></tr>
<tr><td>0x0808f</td><td class="instr">addw X,#0x0014</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E"></td><td class=" E" /></tr>
<tr><td>0x08092</td><td class="instr">ld A,[0x30.w]</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" D"></td><td class=" D"></td><td class=" D"><span class="FS" /></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th><th class="n">10</th><th class="n">11</th><th class="n">12</th><th class="n">13</th>
</thead>
</table>
</a>
</body>
</html>

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<html>
<head>
<title>PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6</title>
<script>
function toggle(id) {
var obj = document.getElementById(id);
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<body onload="toggle('pipetrace_legend')">
<h1>PM0044 5.4.1 Optimized pipeline example - execution from flash, table 6</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x08098</td><td class="instr">neg A</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x08099</td><td class="instr">xor A,0x10</td><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0809b</td><td class="instr">ld A,#0x14</td><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0809d</td><td class="instr">sub A,0x1000</td><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080a0</td><td class="instr">inc A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E" /></tr>
<tr><td>0x080a1</td><td class="instr">ld XL,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E" /></tr>
<tr><td>0x080a2</td><td class="instr">srl A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E" /></tr>
<tr><td>0x080a3</td><td class="instr">swap A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080a4</td><td class="instr">sla 0x15</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"></td><td class=" E" /></tr>
<tr><td>0x080a6</td><td class="instr">cp A,#0xfe</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080a8</td><td class="instr">mov 0x0100,#0x0b</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x080ac</td><td class="instr">mov 0x0101,#0x16</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th><th class="n">10</th><th class="n">11</th><th class="n">12</th><th class="n">13</th><th class="n">14</th>
</thead>
</table>
</a>
</body>
</html>

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<html>
<head>
<title>PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8</title>
<script>
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var obj = document.getElementById(id);
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#pipetrace_legend tr:first-of-type { font-weight: bold; }
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#pipetrace_legend td.defn:before { content: ""; }
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<body onload="toggle('pipetrace_legend')">
<h1>PM0044 5.4.2 Optimize pipeline example - execution from RAM, table 8</h1>
<table id="pipetrace_legend" class="pipetrace">
<tr><td colspan="2">Legend</td></tr>
<tr><td class="D" /><td class="defn">Decode</td></tr>
<tr><td class="E" /><td class="defn">Execute</td></tr>
<tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
<tr><td class="X" /><td class="defn">Flush</td></tr>
<tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
<tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
<tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
<tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>
<a title="Click for legend">
<table class="pipetrace" onclick="toggle('pipetrace_legend')">
<tbody>
<tr><td /><td class="Flushed" /></tr>
<tr><td>0x00104</td><td class="instr">neg A</td><td class=""><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x00105</td><td class="instr">xor A,0x10</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="FS" /></td><td class=" E" /></tr>
<tr><td>0x00107</td><td class="instr">ld A,#0x14</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D Sfetch"><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x00109</td><td class="instr">sub A,0x1000</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="FS" /></td><td class=" E" /></tr>
<tr><td>0x0010c</td><td class="instr">inc A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D Sfetch"><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D Sfetch"><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0010d</td><td class="instr">ld XL,A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0010e</td><td class="instr">srl A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x0010f</td><td class="instr">swap A</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E" /></tr>
<tr><td>0x00110</td><td class="instr">sla 0x15</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="FS" /></td><td class=" E" /></tr>
<tr><td>0x00112</td><td class="instr">cp A,#0xfe</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="FS" /></td><td class=" E" /></tr>
</tbody>
<thead>
<tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th><th class="n">10</th><th class="n">11</th><th class="n">12</th><th class="n">13</th><th class="n">14</th><th class="n">15</th><th class="n">16</th><th class="n">17</th><th class="n">18</th><th class="n">19</th><th class="n">20</th><th class="n">21</th>
</thead>
</table>
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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-2">
<title>Command syntax of &#956;Csim</title>
</head>
<body style=" background-color: white;"> Content:
<ul>
<li><a href="#syntax">Syntax</a> </li>
<li><a href="#expr">Expressions</a> </li>
<li><a href="#redir">Redirection</a> </li>
</ul>
<h2><a name="syntax">Command syntax of <i>&#956;Csim</i></a></h2>
<i>&#956;Csim</i> uses a very simple command interpreter. Command can be entered
after <i>&#956;Csim</i> displays the prompt and interpreted when ENTER key is
pressed. Commands must start with the name of the command following
parameters. Name of the command can be abbreviated if abbreviation is
unique. Some commands have more than one names.
<p>Syntactically parameters can be a string, bit name, array, number or
symbol. Interpretation of these syntactical elements depends on actual
command. </p>
<p>If the command line can not be recognized as a known command, <i>&#956;Csim</i>
tries to evaluate the command line as an <i>expression</i>. <a href="#expr">See
below</a> for information about operands and operators which can be used
in expressions. </p>
<h3><a name="command_name">Command names</a></h3>
Name of the command must be the first word of the command line. It is not
necessary to enter whole name if abbreviation is unique. Help command can be
used to check out if a command has more names:
<pre>&gt; <font color="green">help run</font>
run [start [stop]] Go
Names of command: <b>go r run</b>
...
</pre> Some commands just groups other commands. These commands have a set of
so-called <i>sub-commands</i>. Sub-command must be second word in the
command line. For example:
<pre>&gt; <font color="green">help set</font>
set <b>subcommand</b> Set, see `set' command for more help
Names of command: set
long help of set
&gt; <font color="green">set</font>
"set" must be followed by the name of a subcommand
List of subcommands:
<b>set option</b> name|nr value
Set value of an option
<b>set error</b> on|off|unset
Set value of an error
<b>set memory</b> memory_type address data... or bitspec data
Place list of data into memory
<b>set bit</b> bitspec data Set specified bit(s)
<b>set hardware</b> category params...
Set parameters of specified hardware element
</pre>
<h3>Type of parameters</h3>
<h4><a name="string_type">String type</a></h4>
To distinguish strings and symbols, strings can be surrounded by (double)
quotes. Quotes can be omitted if command parameter is interpreted as string
and actual parameter start with a letter (so it doesn't look to be a number)
and doesn't contain space. Let's look an example:
<pre>0&gt; <font color="green">set opt 7 <b>s51&gt;</b></font>
0s51&gt;<font color="green">set opt 7 <b>".s51&gt; "</b></font>
0.s51&gt;
</pre>
<h4><a name="bit_type">Bit type</a></h4>
If a parameter contains a dot (.) or a colon contained in square brackets ([...:...])
it is treated as a bit specification. If there is a dot the part before the dot gives
the memory address and part after the dot gives the bit number. The bracketed form is
used to specify a range of bits.
<pre>0&gt; <font color="green">dump <b>p1.1</b></font>
P1.1 0x90 ff 1
0&gt; <font color="green">dump <b>0x80.1</b></font>
P4.1 0x80 ff 1
0&gt;
</pre>
<h4><a name="array_type">Array type</a></h4>
Parameters contain [ character are treated as arrays. Arrays can be used to
specify hardware elements. Array index selects an object if more than one
exists:
<pre>0&gt; <font color="green">info hw <b>port[0]</b></font>
port[0]
P0 11111111 0xff 255 . (Value in SFR register)
Pin0 11111111 0xff 255 . (Output of outside circuits)
Port0 11111111 0xff 255 . (Value on the port pins)
0&gt;
</pre>
<h4><a name="number_type">Number type</a></h4>
Some commands accept parameters which in most cases can be numbers. Numbers
can be entered in C-style form. If the number begins with <tt><b>0x</b></tt>
or <tt><b>0X</b></tt> it is interpreted as a <i>hexadecimal</i> number. As
extension to C-style, number can be started by <b><span style="font-family: monospace;">0b</span></b>,
followed by <b><span style="font-family: monospace;">0</span></b> and <b><span
style="font-family: monospace;">1</span></b> characters. In this case it
is interpreted as <i>binary</i> number. If it begins with <tt><b>0</b></tt>
followed by digits it is interpreted as <i>octal</i> number. In other cases
it is interpreted as <i>decimal</i> number.<br>
<h4><a name="symbol_type">Symbol type</a></h4>
If a command parameter can not be classified in other ways (doesn't start
with a digit or a quote, doesn't contain dot or [) then it will be treated
as a <b>symbol</b>. Symbols can be interpreted in several ways.
<h3>Interpretation of parameters</h3>
<h4><a name="address_param">Address parameters</a></h4>
Many commands requires memory addresses as parameters. Addresses can be
specified using number or symbol type of parameters. Value of symbols
depends on processor type. For example MCS52 family of controllers defines
more symbols than MCS51 family.
<h4><a name="number_param">Number, data parameters</a></h4>
When a command expects a number it should get a number. <font color="red">Note</font>,
that symbols is not converted to number they can be used as address only!
<h4><a name="string_param">String parameters</a></h4>
Strings can be entered without quotes if they are recognized as strings (see
above) and do not contain spaces.
<h4><a name="data_list_param">Data list parameters</a></h4>
Data list can be any space separated list of numbers and strings. If you
include a string in the list, it is broken to list of bytes where every byte
is ASCII code of a string's character.
<pre>&gt; <font color="green">where xram "ab" 0x43</font>
0xf961 61 62 63 abc
&gt;
</pre>
<h4><a name="memory_param">Memory parameters</a></h4>
Where memory type is expected, name of the memory should be used. Most
commands accept memory chip and address space too. See <a href="memory.html">memory
simulation</a> for more information.
<h4><a name="hw_param">Hardware element parameters</a></h4>
Hardware elements can be specified by using arrays, where array name is name
of the element and the array index selects one if more than one exists.
<h4><a name="bit_param">Bit parameters</a></h4>
Bits can be specified by several ways. One way is using bit type of command
parameter:
<pre>0&gt; <font color="green">dump 0.2</font>
0x00000.2 0
0&gt; <font color="green">dump 0xc3.2</font>
0x000c3.2 1
0&gt; <font color="green">var a_reg rom[0x1000]</font>
0&gt; <font color="green">dump a_reg[7:0]</font>
0x01000 a_reg 0b11110111 0xf7 '.' 247 ( -9)
0&gt; <font color="green">dump a_reg[5:2]</font>
0x01000[5:2] a_reg[5:2] 0b--1101-- 0x0d '.' 13 ( -3)
0&gt; <font color="green">var some_bits rom[0x1000][5:2]</font>
0&gt; <font color="green">dump some_bits</font>
0x01000[5:2] some_bits 0b--1101-- 0x0d '.' 13 ( -3)
0&gt; <font color="green">dump some_bits[4:3]</font>
0x01000[4:3] a_reg[4:3] 0b---10--- 0x02 '.' 2 ( -2)
0&gt;
</pre>
<p>Note that in the above the <code>[4:3]</code> <em>overrides</em> the
<code>[5:2]</code> defined for the var and <code>some_bits[4:3]</code>means
bits 4 through 3 of the value stored at 0x1000. It does <em>not</em> mean
take the bits defined by the var and then take a subset of those bits.
Note also that the output does not tell us we are looking at <code>some_bit</code>
(because we're not) but since we have a var set for the address as a whole
it does tell us that we are looking at a subset of <code>a_reg</code>.</p>
<p>In this way, any IRAM or SFR location can be addressed as the above
example shows.</p>
<p>Other way is using bit address either by value or by symbolic name: </p>
<pre>0&gt; <font color="green">dump ea</font>
IE0.7 0xa8 00 0
0&gt; <font color="green">dump 34</font>
0x24.2 0x24 24 1
0&gt; <font color="green">dump 0xc7</font>
SCON1.7 0xc0 00 0
0&gt;
</pre> Of course, only addressable bits can be accessed in this way.
<hr>
<h2><a name="expr">Expressions</a></h2>
If first word of the command line is not recognized as a known command, the
command line will be evaluated as an expression and the result value printed
(in decimal):
<pre>0&gt; <font color="green">12*(34+56)</font>
1080
0&gt;
</pre>
<h3>Operands</h3>
Operands of the expressions can be
<ul>
<li>number; </li>
<li>memory (either address space, or memory chip); </li>
<li>or bit</li>
</ul>
<h4>Number operands</h4>
Numbers can be entered in decimal, octal (starting with 0 followed by a
number), or hexadecimal (started with 0x), or binary (started with 0b):
<pre>0&gt; <font color="green">12</font>
12
0&gt; <font color="green">012</font>
10
0&gt; <font color="green">0x12</font>
18
0&gt; <font color="green">0b010101</font>
21
0&gt;
</pre> Numbers must be integers (floating point is not supported) and not bigger
than the value which can be stored as <b>long int</b>. Numbers can be
specified in ascii form too: <b>'a'</b>, result will be ascii code of the
character. This form accepts C style escapes, for example: <b>'\n'</b> or <b>'\033'</b>.
<h4>Memory operands</h4>
Memory can be an address space location or a memory chip cell. It can be
specified in following form:
<pre>name[address]</pre>
where <i>name</i> is the name of the address space or memory chip and <i>address</i>
is an expression specifying location (index) of the cell.
<p>Registers in SFR address space can also be specified using pre-defined
names (symbols) of the registers. </p>
<pre>0&gt; <font color="green">xram[0x543]</font>
67
0&gt; <font color="green">xram_chip[1347]</font>
67
0&gt; <font color="green">rom[12*(34+56)]</font>
56
0&gt; <font color="green">sp</font>
7
0&gt; <font color="green">rom[256*dph+dpl]</font>
88
0&gt;
</pre> Value of the memory operand is always a positive integer number.
<h4>Bit operands</h4>
Bit operands are evaluated to 0 or 1. Any bit of any memory location can be
specified as bit using following form:
<pre>memory.bitnumber</pre>
where <i>memory</i> is a memory location as a memory operand and <i>bitnumber</i>
is number of the bit within the specified memory cell specified as an
expression. Note, that dot (.) is part of the syntax, not an operator.
<p>Alternatively, name of the bit can be used to specify named SFR bits. </p>
<pre>0&gt; <font color="green">p0.3</font>
1
0&gt; <font color="green">xram[12*(34+56)].9-2</font>
0
0&gt; <font color="green">it0</font>
0
0&gt;
</pre>
<h3>Operators</h3>
<table border="1">
<tbody>
<tr>
<th>Type</th>
<th>Operator</th>
<th>Meaning</th>
</tr>
<tr>
<td>Primary</td>
<td><span style="font-family: monospace;">( )</span></td>
<td>Group of sub-expressions</td>
</tr>
<tr>
<td>One operand</td>
<td><span style="font-family: monospace;">+ - &amp; ~ !</span></td>
<td>Unary plus, minus, address of, bit negate, logical not</td>
</tr>
<tr>
<td rowspan="3" colspan="1">Arithmetic</td>
<td><span style="font-family: monospace;">* / %</span></td>
<td>Multiply, divide, modulo</td>
</tr>
<tr>
<td><span style="font-family: monospace;">+ -</span></td>
<td>Add, substract</td>
</tr>
<tr>
<td><span style="font-family: monospace;">&lt;&lt; &gt;&gt;</span></td>
<td>shift left, right</td>
</tr>
<tr>
<td rowspan="2" colspan="1">Logical</td>
<td><span style="font-family: monospace;">&lt; &gt; &lt;= &gt;= == !=</span></td>
<td>Comparison of two values</td>
</tr>
<tr>
<td><span style="font-family: monospace;">&amp;&amp; || ^^</span></td>
<td>Logical and, or, xor</td>
</tr>
<tr>
<td>Bitwise</td>
<td><span style="font-family: monospace;">&amp; | ^</span></td>
<td>Bitwise and, or, xor</td>
</tr>
<tr>
<td>Assignment</td>
<td><span style="font-family: monospace;">= *= /= %= += -= &lt;&lt;=
&gt;&gt;= &amp;= |= ^=</span></td>
<td>Assign to</td>
</tr>
<tr>
<td>Increment, decrement</td>
<td><span style="font-family: monospace;">++ --</span></td>
<td>Can be used in prefix or postfix style</td>
</tr>
<tr>
<td>Conditional</td>
<td><span style="font-family: monospace;">?:</span></td>
<td>Works as in C</td>
</tr>
<tr>
<td>Comma</td>
<td><span style="font-family: monospace;">,</span></td>
<td>Evaluates expression in order, results last</td>
</tr>
</tbody>
</table>
Arithmetic operators and parenthesis work as usual.
<p>Assignment operator can be used to modify memory cells and bits of the
cells. Result will be the assigned value. </p>
<pre>0&gt; <font color="green">p0=23</font>
23
0&gt; <font color="green">i h port[0]</font>
port[0]
P0 00010111 0x17 23 . (Value in SFR register)
Pin0 11111111 0xff 255 . (Output of outside circuits)
Port0 00010111 0x17 23 . (Value on the port pins)
0&gt; <font color="green">p0.0= 0</font>
0
0&gt; <font color="green">i h p[0]</font>
port[0]
P0 00010110 0x16 22 . (Value in SFR register)
Pin0 11111111 0xff 255 . (Output of outside circuits)
Port0 00010110 0x16 22 . (Value on the port pins)
0&gt; <font color="green">xram[256*dph+dpl]= rom[0]</font>
108
0&gt; <font color="green">dump rom 0 0</font>
0x0000 6c l
0&gt; <font color="green">dump sfr dph dph</font>
0x83 00 .
0&gt; <font color="green">dump sfr dpl dpl</font>
0x82 00 .
0&gt; <font color="green">dump xram 0 0</font>
0x0000 6c l
0&gt; <font color="green">0x6c</font>
108
0&gt; <font color="green">dump ea</font>
IE0.7 0xa8 00 0
0&gt; <font color="green">ea= 1111</font>
1
0&gt; <font color="green">dump ea</font>
IE0.7 0xa8 80 1
0&gt;
</pre> When a symbolic name of the SFR is used, it results value of the named
register not the value of the symbol. "Address of" operator can be used to
get value of the symbol.
<pre>0&gt; <font color="green">dpl</font>
0
0&gt; <font color="green">&amp;dpl</font>
130
0&gt; <font color="green">ea</font>
1
0&gt; <font color="green">&amp;ea</font>
175
0&gt; <font color="green">256*dph+dpl</font>
46630
0&gt; <font color="green">&amp;xram[256*dph+dpl]</font>
46630
0&gt;
</pre>
<hr>
<h2><a name="redir">Redirection</a></h2>
Output of any command can be redirected to a file. Same syntax can be used
for this as for UNIX shell. The only difference is that <i>&#956;Csim</i>
doesn't allow to put redirection at the beginning of the command!
<pre>$ <font color="#118811">ucsim_51 remo.hex</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
55470 words read from remo.hex
0&gt; <font color="#118811">dump &gt;/tmp/rom.dump rom</font>
0&gt; <font color="#118811">quit</font>
$ <font color="#118811">cat /tmp/rom.dump</font>
0x0000 02 01 60 02 00 3c 06 07 ..`..&lt;..
0x0008 08 09 0a 02 2f 6b 0e 0f ..../k..
0x0010 10 11 12 02 00 ac 16 17 ........
0x0018 18 19 1a 1b 1c 1d 1e 1f ........
0x0020 20 21 22 02 01 1c 26 27 !"...&amp;'
0x0028 28 29 2a 32 2c 2d 2e 2f ()*2,-./
0x0030 02 0f a7 02 0e 9c 02 0d ........
0x0038 d2 02 08 41 c0 82 c0 83 ...A....
0x0040 c0 d0 c0 e0 c0 00 a2 90 ........
0x0048 c0 d0 c2 90 78 18 06 30 ....x..0
$ <font color="#118811">ucsim_51 remo.hex</font>
uCsim 0.5.0-pre3, Copyright (C) 1997 Daniel Drotos, Talker Bt.
uCsim comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
55470 words read from remo.hex
0&gt; <font color="#118811">dump rom 0x50 &gt;&gt;/tmp/rom.dump</font>
0&gt; <font color="#118811">quit</font>
$ <font color="#118811">cat /tmp/rom.dump</font>
0x0000 02 01 60 02 00 3c 06 07 ..`..&lt;..
0x0008 08 09 0a 02 2f 6b 0e 0f ..../k..
0x0010 10 11 12 02 00 ac 16 17 ........
0x0018 18 19 1a 1b 1c 1d 1e 1f ........
0x0020 20 21 22 02 01 1c 26 27 !"...&amp;'
0x0028 28 29 2a 32 2c 2d 2e 2f ()*2,-./
0x0030 02 0f a7 02 0e 9c 02 0d ........
0x0038 d2 02 08 41 c0 82 c0 83 ...A....
0x0040 c0 d0 c0 e0 c0 00 a2 90 ........
0x0048 c0 d0 c2 90 78 18 06 30 ....x..0
0x0050 03 4b 20 92 48 30 07 05 .K .H0..
0x0058 c2 07 02 00 9d 30 08 05 .....0..
0x0060 20 93 3a c2 08 90 08 60 .:....`
0x0068 e0 b4 ff 03 02 00 9d 04 ........
0x0070 f0 14 f8 03 03 03 54 1f ......T.
0x0078 90 08 62 25 82 f5 82 e5 ..b%....
0x0080 83 34 00 f5 83 e8 54 07 .4....T.
0x0088 f8 08 74 80 23 d8 fd f8 ..t.#...
0x0090 e0 30 93 07 c8 f4 58 f0 .0....X.
0x0098 02 00 9d 48 f0 d0 d0 92 ...H....
$
</pre>
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<html>
<head>
<meta content="text/html; charset=ISO-8859-2" http-equiv="content-type">
<title>&mu;Csim: Regression Testing</title>
</head>
<body bgcolor="white">
<h1>Regression Testing</h1>
<h2>Running Tests</h2>
<p>If you are making changes to &mu;Csim you should both run tests
to ensure nothing breaks and write new tests to ensure your changes
work and do not get broken in the future!</p>
<p>In all cases the tests are run using the locally built simulators.
i.e. you need to have completed a successful build before you can
test it! Tests produce output when run which is captured to a file
and compared with baseline output held in the source tree. If there
are any differences they are output and the test is considered
failed. In that case either the code needs to be changed to correct
the output or the baseline needs to be updated to reflect the new
expected output. Only when there are no differences to the baseline
can tests be said to have passed.</p>
<h3>All Tests</h3>
<p>To run all tests run <code>make test</code> in the top-level
<code>ucsim</code> directory.<br />
E.g.:
<pre>.../ucsim$ <font color="#118811">make test</font></pre>
</p>
<h3>For a Single MCU</h3>
<p>To run tests for a single MCU type run <code>make test</code>
in the directory for that simulator.<br />
E.g.:
<pre>.../ucsim/s51.src$ <font color="#118811">make test</font></pre>
or run <code>make</code> in the <code>test</code> subdirectory.<br />
E.g.:
<pre>.../ucsim/s51.src/test$ <font color="#118811">make</font></pre>
</p>
<p>Note that tests for functionality generic to all simulators and that
does not depend on a particular MCU type lives in
<code>sim.src/test</code> and should be run there. These tests require
at least one simulator to have been built but unless there is only one
it is indeterminate which simulator will be used.</p>
<h3>Running a Single Test</h3>
<p>To run a single test run <code>make <i>test_name</i></code>
in the <code>test</code> subdirectory of the relevant simulator. E.g.:
<pre>.../ucsim/s51.src/test$ <font color="#118811">make config</font></pre>
In this case the test is run verbosely and the commands executed by make
are displayed. In all other cases only the final differences to baseline
(if any) are displayed.</p>
<h3>Updating the Baselines</h3>
<p>If changes to the simulator code base lead to changes in test outputs
<em>and these changes are as expected</em> then the baselines should be
updated to match the new output by copying the contents of the <code>out</code>
directories to the corresponding <code>baseline</code> directories.</p>
<p>To update all baselines run <code>make baseline</code> in the top-level
<code>ucsim</code> directory.<br />
<p>To update baselines for a single MCU type run <code>make baseline</code>
in the directory for that simulator.<br />
<p>If you need to update the baseline for a single test you should copy the
relevant files manually.</p>
<p><em>Remember that the updated baselines form part of your changes and
need to be committed or submitted as part of your patch!</em></p>
<h2>Writing Tests</h2>
<ol>
<li>Create a directory named after your test under the relevant simulator's
<code>test</code> directory:
</li>
<li>Place the data needed for your test, <code>.cmd</code> files, <code>.asm</code>
or <code>C</code> files etc, in your test directory:
</li>
<li>Create a <code>baseline</code> directory in your test directory:
</li>
<li>Create an empty file in the <code>baseline</code> directory for each
output that your test generates:
</li>
<li>Create a <code>Makefile</code> that lists the output(s) to be generated,
the recipes to create them and which includes <code>test-lib.mk</code>:
</li>
<li>Run your test, verify the contents of the <code>out</code> directory
and then copy it to the <code>baseline</code> directory:
</li>
</ol>
<pre>
.../ucsim/s51.src/test$ <font color="#118811">mkdir <i>name</i></font>
.../ucsim/s51.src/test$ <font color="#118811">cd <i>name</i></font>
.../ucsim/s51.src/test/<i>name</i>$ <font color="#118811">vim test.{cmd,asm}</font>
.../ucsim/s51.src/test/<i>name</i>$ <font color="#118811">mkdir baseline</font>
.../ucsim/s51.src/test/<i>name</i>$ <font color="#118811">touch baseline/<i>stdout</i></font>
.../ucsim/s51.src/test/<i>name</i>$ <font color="#118811">cat &gt; Makefile &lt;&lt;EOF</font>
OUTPUTS = <i>stdout</i>
<i>stdout</i>: <i>mytest</i>.ihx <i>mytest</i>.cmd
$(call run-sim)
include test-lib.mk
EOF
.../ucsim/s51.src/test/<i>name</i>$ <font color="#118811">cd ..</font>
.../ucsim/s51.src/test$ <font color="#118811">make <i>name</i></font>
.../ucsim/s51.src/test$ <font color="#118811">cp -r <i>name</i>/out <i>name</i>/baseline/.</font></pre>
<p><code>test-lib.mk</code> takes care of building any <code>.ihx</code> files
needed from corresponding <code>.asm</code> or <code>.c</code> files.
The call to <code>run-sim</code> will invoke the simulator with the
<code>.ihx</code> and <code>.cmd</code> prerequisites, capturing the
output.</p>
<p>If there are no <code>.cmd</code> prerequisites and there is no
<code>-e</code> in the arguments to <code>run-sim</code> it
will add a <code>-g</code> argument to start the simulator running.
It is assumed there is at least one <code>.ihx</code> file in the
prerequisites in this case and that it places code at the reset
address.</p>
<p>If you wish to pass arguments of your own to the simulator these
can be given as arguments to run-sim. This can be used to pass commands
with the <code>-e</code> option rather than using a <code>.cmd</code> file
for instance, as is done with the config tests.</p>
<p>If you create any other output from within the simulator you should
specify a pathname starting with <code>out/</code>. Anything written
to the <code>out</code> directory will be compared to the baseline
when the test is complete.</p>
</p>
<hr>
</body>
</html>

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<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=iso-8859-2">
<title>&#956;Csim: VCD file dumper</title>
</head>
<body style="background-color: white;">
<h1>VCD file I/O</h1>
<p>Initially there is one vcd defined called "vcd[0]" (or just "vcd").
You can create an additional vcds with "set hw vcd[0] new <i>id</i>" and
configure it with "set hw vcd[<i>id</i>] ..." commands ("<i>id</i>" must
be an integer).</p>
<h2>Output (event logging)</h2>
<p>The vcd module creates VCD files compatible with industry standards and
readable with open source tools such as gtkwave and sigrok/pulseview.</p>
<p>(N.B. sigrok/pulseview only supports VCD files containing events that
are 1 bit wide only.)</p>
<ol>
<li>Specify output file<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] output "name.vcd"</font>
</pre>
<p>Alternatively specify no, or an empty, output file or use the
"view" command and the simulator will attempt to invoke
<a href="http://gtkwave.sourceforge.net/">gtkwave</a>
directly.</p>
<pre>
0&gt; <font color="#118811">set hw vcd[0] output ""</font>
0&gt; <font color="#118811">set hw vcd[0] view</font>
</pre>
</li>
<li>Add locations to dump<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] add pc_odr</font>
0&gt; <font color="#118811">set hw vcd[0] add rom[0x500a].3</font>
</pre>
You can set the name of the module if you want (set hw vcd[0] module
name), it will be ucsim_vcd_0 by default.<br>
<br>
</li>
<li>Check the configuration<br>
<pre>
0&gt; <font color="#118811">info hw vcd[0]</font>
vcd[0] value change dump
Modul: ucsim_vcd_0
Started: no
Paused: no
File: name.vcd
Mode: output
Time scale: auto set on start
Start time: 0.000000000000000 s
Last event: 0.000000000000000 s
Simul time: 0.000000000000000 s
Variables:
Address Symbol
rom[0x0500a][7:0] pc_odr
rom[0x0500a].3
</pre>
</li>
<li>Start recording<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] start</font>
</pre>
</li>
<li>Run the program<br>
<br>
</li>
<li>You can pause/resume recording<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] pause</font>
0&gt; <font color="#118811">set hw vcd[0] restart</font>
</pre>
<p>While the vcd is paused no changes are recorded in the
output and values will show as unknown when the VCD is viewed
by something such as
<a href="http://gtkwave.sourceforge.net/">gtkwave</a>.</p>
<p>If you set pausetime then the time recorded as unknown
will be limited to the specified time and time beyond that
will simply not exist as far as the VCD is concerned.
This may be used to compress pause gaps in the VCD for the
sake of viewers which are not able to do this themselves.</p>
<pre>
0&gt; <font color="#118811">set hw vcd[0] pausetime 300 ns</font>
</pre>
</li>
<li>Stop recording and close the VCD file<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] stop</font>
</pre>
</li>
</ol>
<h2>Input (event replay)</h2>
<ol>
<li>Define any variables used by the input file<br>
<pre>
0&gt; <font color="#118811">var loc1 rom[0x5001]</font>
</pre>
</li>
<li>Specify input file<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] input "name.vcd"</font>
</pre>
</li>
<li>Adjust the base time<br>
By default time 0 in the VCD file corresponds to the simulator time
when the vcd is started. You can adjust this by setting the start time
of the vcd. For instance, to move the VCD events 750 ns into the future
you would use
<pre>
0&gt; <font color="#118811">set hw vcd[0] starttime 750 ns</font>
</pre>
<p>This can be done at any time, regardless of whether the vcd is started,
paused or even part way through.</p>
<p>Note that the argument to starttime is the amount to add or subtract
from the current start time not an absolute time.</p>
<br>
</li>
<li>Start the replay<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] start</font>
<pre>
</li>
<li>Check the configuration<br>
N.B. The VCD file's header is only parsed when the vcd is started.
Until then the configuration details are unknown.<br>
<pre>
0&gt; <font color="#118811">info hw vcd[0]</font>
vcd[0] value change dump
Modul: ucsim_vcd_0
Started: YES
Paused: no
File: name.vcd
Mode: input
Break: disabled
Time scale: 1 ns
Start time: 0.000000000000000 s
Next event: 0.000000000000000 s
Simul time: 0.000000000000000 s
Variables:
Address Symbol
rom[0x0500a] pc_odr
rom[0x0500a].3
</pre>
</li>
<li>Run the program<br>
<br>
</li>
<li>Pause/resume replay<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] pause</font>
0&gt; <font color="#118811">set hw vcd[0] restart</font>
</pre>
<p>While the replay is paused any cycles used by the simulator
are ignored by vcd and do NOT advance you towards the next
event.</p>
<br>
</li>
<li>Toggle the break flag as required<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] break</font>
</pre>
<p>The break flag causes vcd to generate a break each an event
is replayed giving you the opportunity to check that your program
responds to it correctly.</p>
<br>
</li>
<li>Stop the replay and close the VCD file<br>
<pre>
0&gt; <font color="#118811">set hw vcd[0] stop</font>
</pre>
</li>
</ol>
</body>
</html>

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.TH SERIALVIEW 1
.SH NAME
serialview \- Terminal emulator for uCsim
.SH SYNOPSIS
.B serialview
\-i <filename> \-o <filename> \-L n \-a <pattern> \-A <answer> \-IOh
.SH DESCRIPTION
serialview is a simple terminal emulator which can be used with uCsim.
.SH OPTIONS
.TP
.B \-i filename
.I filename
is the pipe to the controllers's serial input. Characters typed into
the input panel will be written to this file.
.TP
.B \-o filename
.I filename
is the pipe to the controllers's serial output. Content of this file
is prosented on the output panel.
.TP
.B \-I
Use hexadecimal filter on input. Only hexadecimal characters are
accepted in input panel. Two characters are combined into a
hexadecimal code and value is written to the input pipe.
.TP
.B \-O
Use hexadecimal filter on output. Content of output pipe is presented
as a hexadecimal dump. \-L option can be used to set how many bytes
are printed in one line.
.TP
.B \-a pattern
.I pattern
is a string which is recognized in output stream and automaticaly
answered by sending an answer string (see \-A option). String can be
formatted as a C string, non-asci characters can be escaped in C
style.
.TP
.B \-A answer
.I answer
is a string which is sent when a pattern (see \-a option) is detected
in simulator's output. This answer string is written to the input pipe
but not shown in the input panel.
.TP
.B \-L n
Set line length of hexadecimal dump in output panel (default=8).
.TP
.B \-h
Show summary of options.
.PP
When no options are provided the input and output pipes are created in
.B /tmp
and named respectively
.B in
and
.B out
.SH "SEE ALSO"
sdcc(1), ucsim(1).
.SH AUTHOR
Timothy Hurman

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.TH UCSIM 1
.SH NAME
uCsim \- Micro\-controller simulator
.SH SYNOPSIS
.B ucsim_51
.br
.B ucsim_xa
.br
.B ucsim_z80
.br
.B ucsim_tlc
.br
.B ucsim_rxk
.br
.B ucsim_avr
.br
.B ucsim_pdk
.br
.B ucsim_st7
.br
.B ucsim_stm8
.br
.B ucsim_p1516
.br
.B ucsim_m6800
.br
.B ucsim_m6809
.br
.B ucsim_m68hc08
.br
.B ucsim_m68hc11
.br
.B ucsim_m68hc12
.br
.B ucsim_mos6502
.br
.B ucsim_plaze
.br
.RS
.B \-t cpu_type
.B \-X freq[k|M]
.B \-R seed
.B \-C cfg_file
.B \-e command
.B \-c file
.B \-Z portnum
.B \-k portnum
.B \-s file
.B \-S options
.B \-I options
.B \-p prompt
.B \-P
.B \-o colors
.B \-l
.B \-b
.B \-B
.B \-g
.B \-G
.B \-a nr
.B \-w
.B \-V
.B \-v
.B \-H
.B \-h
.RE
.SH DESCRIPTION
uCsim is a microcontroller, microprocessor simulator for several
processor familes. It can be started as
.B ucsim_XXXX
command, where XXXX specifies the simulated processor type. Eg.
.I ucsim_51
starts Intel MCS51 microcontroller simulator,
.I ucsim_z80
starts Zilog Z80 microprocessor simulator, etc.
.SH OPTIONS
.B Options of the command
.TP
.B \-t cpu_type
Specifies type of the controller. Use \-H to list possible values.
.TP
.B \-X freq[k|M]
XTAL frequency in Hz, Use
.I k
or
.I M
suffix to specify frequency in kHz or MHz.
.TP
.B \-R seed
Set the random number generator seed.
.TP
.B \-C file
Read initial commands from
.I file
and execute them.
.TP
.B \-e command
Execute
.I command
at program startup (before config file).
.TP
.B \-c file
Open command console on
.I file
(use \- for std in/out).
.TP
.B \-Z portnum
Use
.I localhost:portnum
for command console.
.TP
.B \-k portnum
Use
.I localhost:portnum
for serial I/O. This option is obsolete, use \-S instead.
.TP
.B \-s file
Connect serial interface uart0 to
.I file
This option is obsolete, use \-S instead.
.TP
.B \-S options
.I options
is a comma separated list of options according to serial interface. Know options are:
.br
.I uart=nr
number of uart (default=0)
.br
.I in=file
serial input will be read from file named `file'.
.br
.I out=file
serial output will be written to `file'.
.br
.I port=nr
use localhost:nr as server for serial line.
.br
.I iport=nr
use localhost:nr as server for serial input.
.br
.I oport=nr
use localhost:nr as server for serial onput.
.br
.I raw
perform non-interactive communication even on tty.
.TP
.B \-I options
.I options
is a comma separated list of options according to simulator
interface. Known options are:
.br
.I if=memory[address]
turn on interface on given memory location.
.br
.I in=file
specify input file for IO.
.br
.I out=file
specify output file for IO.
.PP
.TP
.B \-p prompt
Specify string for prompt.
.TP
.B \-P
Prompt is a null ('\\0') character.
.PP
.TP
.B \-o colors
List of color specification: what=colspec,... where colspec is :
separated list of color options e.g.: prompt=b:white:black (bold white
on black).
.TP
.B \-l
Use colors of the light theme (default is dark).
.PP
.TP
.B \-b
Black & white (non-color) console.
.TP
.B \-B
Beep on breakpoints.
.TP
.B \-g
Go, start simulation.
.TP
.B \-G
Go, start simulation, quit on stop.
.TP
.B \-a nr
Specify size of variable space (default=256).
.TP
.B \-w
Writable flash.
.TP
.B \-V
Verbose mode.
.TP
.B \-v
Print out version number and quit.
.TP
.B \-H
Print out types of known CPUs and quit.
.TP
.B \-h
Print out this help and quit.
.SH EXAMPLES
None yet.
.SH "SEE ALSO"
sdcc(1), sdcdb(1), serialview(1).
.SH BUGS
Probably many.
.SH AUTHORS, CONTRIBUTORS
Daniel Drotos,
Gunar Holm,
Sandeep Dutta,
Salvador Eduardo Tropea,
Josef Wolf,
Stephane Meyer,
Larry Doolittle,
Timothy Hurman,
Karl-Max Wagner,
Edmar Wienskoski Jr,
Alexandre Frey,
Kaido Karner,
Kalr Bongers,
Alexis Pavlov,
Davine Zanni,
Anton Persson,
Nicolas Lesser,
Mike Jagdis,
Jiri Simek,
Zbynek Krivka,
Vaclav Peroutka,
Valentin Dudouyt,
Erik Petrich,
Leland Morrison,
Johan Knol.

100
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2023-01-19 Philipp Klaus Krause <pkk AT spth.de>
* device/lib/*/crt0.s,
src/SDCCglue.c,
src/stm8/main.c,
.version:
Patch #453 by Basil Hussain to further harmonize __sdcc_external_startup (RFE #859).
* src/z80/gen.c,
src/ds390/gen.c,
src/mcs51/gen.c:
Type fixes for code generation (fixing regressions visible on 32-bit big-endian hosts).
* doc/sdccman.lyx:
Improve __sdcc_external_startup documentation.
2023-01-17 Philipp Klaus Krause <pkk AT spth.de>
* support/regression/tests/gcc-torture-execute-va-arg-5.c:
Disable Test for GCC up to 11, since it still fails on x86 hosts for that version.
* support/regression/cases/Makefile.in:
Disable Test that tests for GCC implementation-defined behaviour (GIMPLE memory model).
2023-01-10 Erik Petrich <epetrich AT ivorytower.norman.ok.us>
* src/SDCCcse.c: Improve pointer aliasing handling,
minor reduction in memory leakage
* support/regression/tests/bug-2957.c,
support/regression/tests/gcc-torture-execute-pr20466-1.c:
Reenable tests
2023-01-08 Benedikt Freisen <b.freisen AT gmx.net>
* src/SDCCmain.c:
Add "TD-" to the version string of treedec-less builds.
2023-01-08 Benedikt Freisen <b.freisen AT gmx.net>
* doc/sdccman.lyx:
Amend claims concerning intrinsic address space support.
2023-01-02 Philipp Klaus Krause <pkk AT spth.de>
* src/SDCCast.c,
support/regression/tests/bug-3504.c:
Fix bug #3504.
2022-12-31 Erik Petrich <epetrich AT ivorytower.norman.ok.us>
* src/SDCClabel.c (labelUnreach, deleteIfx),
src/SDCCcse.c (ifxOptimize): disable conditional flow change and
unreachable code warnings within function inlining
* src/SDCClabel.c (labelJumptable,iCodeLabelOptimize),
src/SDCCcse.c (cseBBlock): optimize jump tables
* src/SDCClabel.c (labelUnreach): clean up dead code def/use info
2022-12-24 Erik Petrich <epetrich AT ivorytower.norman.ok.us>
* support/cpp/gcc/configure.ac,
support/cpp/gcc/configure: disable some assembler and
target tests unneeded for the preprocessor
2022-12-16 Philipp Klaus Krause <pkk AT spth.de>
* doc/sdccman.lyx:
Fix bug #3500.
* src/stm8/gen.c,
src/pdk/gen.c:
Fix bug #3515.
2022-12-15 Philipp Klaus Krause <pkk AT spth.de>
* support/regression/tests/gcc-torture-execute-941021-1.c:
Remove a test that apparently relies on implementation-defined floating-point rounding behaviour.
2022-12-14 Philipp Klaus Krause <pkk AT spth.de>
* support/regression/tests/bug-2567.c,
support/regression/tests/bug-2752.c:
Provide external declaration of inline function to pass test-host for non-inlining host compilers.
* sdas/aspdk14/pdk14mch.c,
sdas/aspdk15/pdk15mch.c:
Fix bug #3376, patch by Free-PDK.
2022-12-13 Philipp Klaus Krause <pkk AT spth.de>
* device/lib/sm83/divint.s,
support/regression/tests/muldiv.c.in,
support/regression/tests/onebyte.c.in:
Fix a % sm83 library issue, patch by Job Bolle.
* src/stm8/main.c:
Fix __sdcc_external_startup handling for stm8 large memory model.
* src/z80/peeph.def:
Fix bug #3528.
2022-12-04 Philipp Klaus Krause <pkk AT spth.de>
* src/SDCCopt.c,
support/regression/tests/bug-3522.c:
Fix bug #3522.
2022-12-03 Philipp Klaus Krause <pkk AT spth.de>

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There is no documentation included in the snapshot archives.
You can download the full documentation archive at:
http://sdcc.sourceforge.net/snapshots/docs/sdcc-doc.tar.gz
For Windoze character set and line ending:
http://sdcc.sourceforge.net/snapshots/docs/sdcc-doc.zip
Online:
http://sdcc.sourceforge.net/doc/

37
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/default/features.h Normal file
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/*-------------------------------------------------------------------------
features.h - default features.
Copyright (C) 2001, Michael Hope
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDC51_ASM_FEATURES_H
#define __SDC51_ASM_FEATURES_H 1
#define _REENTRANT __reentrant
#define _CODE __code
#define _AUTOMEM
#define _STATMEM
#endif

74
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/ds390/features.h Normal file
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@@ -0,0 +1,74 @@
/*-------------------------------------------------------------------------
features.h - DS390/DS400 specific features.
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDC51_ASM_DS390_FEATURES_H
#define __SDC51_ASM_DS390_FEATURES_H 1
#define _REENTRANT __reentrant
#define _CODE __code
/* define _AUTOMEM to indicate the default storage class for
automatic variables. To be used with pointers to automatic variables.
Cannot be used in reentrant declared functions!
void foo(void)
{
char Ar[10];
char _AUTOMEM * pAr = Ar;
}
*/
#if defined(__SDCC_STACK_AUTO)
#if defined(__SDCC_USE_XSTACK)
#define _AUTOMEM __pdata
#elif defined(__SDCC_STACK_TENBIT)
#define _AUTOMEM __xdata
#else
#define _AUTOMEM __idata
#endif
#elif defined(__SDCC_MODEL_SMALL)
#define _AUTOMEM __data
#else
#define _AUTOMEM __xdata
#endif
/* define _STATMEM to indicate the default storage class for
global/static variables. To be used with pointers to static variables.
char Ar[10];
void foo(void)
{
char _STATMEM * pAr = Ar;
}
*/
#if defined(__SDCC_MODEL_SMALL)
#define _STATMEM __data
#else
#define _STATMEM __xdata
#endif
#endif

86
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/mcs51/features.h Normal file
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@@ -0,0 +1,86 @@
/*---------------------------------------------------------------------------
features.h: MCS51 specific features.
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDC51_ASM_MCS51_FEATURES_H
#define __SDC51_ASM_MCS51_FEATURES_H 1
#define _REENTRANT __reentrant
#define _CODE __code
/* define _AUTOMEM to indicate the default storage class for
automatic variables. To be used with pointers to automatic variables.
Cannot be used in reentrant declared functions!
void foo(void)
{
char Ar[10];
char _AUTOMEM * pAr = Ar;
}
*/
#if defined(__SDCC_STACK_AUTO)
#if defined(__SDCC_USE_XSTACK)
#define _AUTOMEM __pdata
#else
#define _AUTOMEM __idata
#endif
#elif defined(__SDCC_MODEL_SMALL)
#define _AUTOMEM __data
#elif defined(__SDCC_MODEL_MEDIUM)
#define _AUTOMEM __pdata
#else
#define _AUTOMEM __xdata
#endif
/* define _STATMEM to indicate the default storage class for
global/static variables. To be used with pointers to static variables.
char Ar[10];
void foo(void)
{
char _STATMEM * pAr = Ar;
}
*/
#if defined(__SDCC_MODEL_SMALL)
#define _STATMEM __data
#elif defined(__SDCC_MODEL_MEDIUM)
#define _STATMEM __pdata
#else
#define _STATMEM __xdata
#endif
/* define _RETURN for correct returning from inline asm functions
*/
#if defined(__SDCC_MODEL_HUGE)
#define _RETURN ljmp __sdcc_banked_ret
#else
#define _RETURN ret
#endif
#endif

40
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/pic14/features.h Normal file
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@@ -0,0 +1,40 @@
/*-------------------------------------------------------------------------
features.h - PIC16 port features.
Copyright (C) 2004, Vangelis Rokas <vrokas AT otenet.gr>
Adopted for pic14 port library by Raphael Neider <rneider at web.de> (2006)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __PIC14_ASM_FEATURES_H
#define __PIC14_ASM_FEATURES_H 1
#define _REENTRANT
#define _CODE __code
#define _DATA __data
#define _AUTOMEM
#define _STATMEM
#endif /* __PIC14_ASM_FEATURES_H */

43
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/pic16/features.h Normal file
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@@ -0,0 +1,43 @@
/*-------------------------------------------------------------------------
features.h - PIC16 port features.
Copyright (C) 2004, Vangelis Rokas <vrokas AT otenet.gr>
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __PIC16_ASM_FEATURES_H
#define __PIC16_ASM_FEATURES_H 1
#define _REENTRANT
#define _IL_REENTRANT
#define _FS_REENTRANT
#define _MATH_REENTRANT
#define _CODE __code
#define _DATA __data
#define _AUTOMEM
#define _STATMEM
#endif /* __PIC16_ASM_FEATURES_H */

41
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/r2k/features.h Normal file
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@@ -0,0 +1,41 @@
/*-------------------------------------------------------------------------
features.h - Z80 specific features.
Copyright (C) 2001, Michael Hope
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDCC_ASM_R2K_FEATURES_H
#define __SDCC_ASM_R2K_FEATURES_H 1
#define _REENTRANT
#define _CODE
#define _AUTOMEM
#define _STATMEM
#define _SDCC_MANGLES_SUPPORT_FUNS 1
#define _SDCC_Z80_STYLE_LIB_OPT 1
#endif

41
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/r3ka/features.h Normal file
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@@ -0,0 +1,41 @@
/*-------------------------------------------------------------------------
features.h - Rabbit 3000A specific features.
Copyright (C) 2001, Michael Hope
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDCC_ASM_R3KA_FEATURES_H
#define __SDCC_ASM_R3KA_FEATURES_H 1
#define _REENTRANT
#define _CODE
#define _AUTOMEM
#define _STATMEM
#define _SDCC_MANGLES_SUPPORT_FUNS 1
#define _SDCC_Z80_STYLE_LIB_OPT 1
#endif

41
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/sm83/features.h Normal file
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@@ -0,0 +1,41 @@
/*-------------------------------------------------------------------------
features.h - SM83 specific features.
Copyright (C) 2001, Michael Hope
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDC51_ASM_SM83_FEATURES_H
#define __SDC51_ASM_SM83_FEATURES_H 1
#define _REENTRANT
#define _CODE
#define _AUTOMEM
#define _STATMEM
#define _SDCC_MANGLES_SUPPORT_FUNS 1
#define _SDCC_Z80_STYLE_LIB_OPT 1
#endif

41
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/stm8/features.h Normal file
View File

@@ -0,0 +1,41 @@
/*-------------------------------------------------------------------------
features.h - STM8 specific features.
Copyright (C) 2001, Michael Hope, 2013, Philipp Klaus Krause
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDCC_ASM_STM8_FEATURES_H
#define __SDCC_ASM_STM8_FEATURES_H 1
#define _REENTRANT
#define _CODE
#define _AUTOMEM
#define _STATMEM
#define _SDCC_MANGLES_SUPPORT_FUNS 1
#define _SDCC_Z80_STYLE_LIB_OPT 1
#endif

41
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/tlcs90/features.h Normal file
View File

@@ -0,0 +1,41 @@
/*-------------------------------------------------------------------------
features.h - Z80 specific features.
Copyright (C) 2001, Michael Hope
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDCC_ASM_TLCS90_FEATURES_H
#define __SDCC_ASM_TLCS90_FEATURES_H 1
#define _REENTRANT
#define _CODE
#define _AUTOMEM
#define _STATMEM
#define _SDCC_MANGLES_SUPPORT_FUNS 1
#define _SDCC_Z80_STYLE_LIB_OPT 1
#endif

41
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/asm/z80/features.h Normal file
View File

@@ -0,0 +1,41 @@
/*-------------------------------------------------------------------------
features.h - Z80 specific features.
Copyright (C) 2001, Michael Hope
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDCC_ASM_Z80_FEATURES_H
#define __SDCC_ASM_Z80_FEATURES_H 1
#define _REENTRANT
#define _CODE
#define _AUTOMEM
#define _STATMEM
#define _SDCC_MANGLES_SUPPORT_FUNS 1
#define _SDCC_Z80_STYLE_LIB_OPT 1
#endif

52
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/assert.h Normal file
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@@ -0,0 +1,52 @@
/*-------------------------------------------------------------------------
assert.h - header file for assert ANSI routine
Copyright (C) 2018-2022, Philipp Klaus Krause . pkk@spth.de
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __STDC_VERSION_ASSERT_H__
#define __STDC_VERSION_ASSERT_H__ __STDC_VERSION__
#undef assert
#ifdef NDEBUG
/* Debugging disabled -- do not evaluate assertions. */
#define assert(...) ((void)0)
#else
/* Debugging enabled -- verify assertions at run time. */
void __assert(const char *expression, const char *functionname, const char *filename, unsigned int linenumber);
#define assert(...) ((__VA_ARGS__) ? (void)0 : __assert(#__VA_ARGS__, __func__, __FILE__, __LINE__))
#if __STDC_VERSION__ < 202311L
#define static_assert _Static_assert
#endif
#endif
#endif

97
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/ctype.h Normal file
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@@ -0,0 +1,97 @@
/*-------------------------------------------------------------------------
ctype.h
Philipp Klaus Krause, philipp@informatik.uni-frankfurt.de 2013
(c) 2013 Goethe-Universität Frankfurt
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __STDC_VERSION_CTYPE_H__
#define __STDC_VERSION_CTYPE_H__ __STDC_VERSION__
extern int isalnum (int c);
extern int isalpha (int c);
extern int iscntrl (int c);
extern int isgraph (int c);
extern int isprint (int c);
extern int ispunct (int c);
extern int isspace (int c);
extern int isalnum (int c);
extern int isalnum (int c);
extern int isxdigit (int c);
extern int tolower (int c);
extern int toupper (int c);
/* Provide inline versions for the most used functions for efficiency */
#if __STDC_VERSION__ >= 199901L
inline int isblank (int c)
{
return ((unsigned char)c == ' ' || (unsigned char)c == '\t');
}
#ifdef EOF
_Static_assert(!((unsigned char)EOF == ' ' || (unsigned char)EOF == '\t'), "EOF out of range - ");
#endif
inline int isdigit (int c)
{
return ((unsigned char)c >= '0' && (unsigned char)c <= '9');
}
#ifdef EOF
_Static_assert(!((unsigned char)EOF >= '0' && (unsigned char)EOF <= '9'), "EOF out of range - ");
#endif
inline int islower (int c)
{
return ((unsigned char)c >= 'a' && (unsigned char)c <= 'z');
}
#ifdef EOF
_Static_assert(!((unsigned char)EOF >= 'a' && (unsigned char)EOF <= 'z'), "EOF out of range - ");
#endif
inline int isupper (int c)
{
return ((unsigned char)c >= 'A' && (unsigned char)c <= 'Z');
}
#ifdef EOF
_Static_assert(!((unsigned char)EOF >= 'A' && (unsigned char)EOF <= 'Z'), "EOF out of range - ");
#endif
#else
extern int isblank (int c);
extern int isdigit (int c);
extern int islower (int c);
extern int isupper (int c);
#endif
#endif

35
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/ds390/serial390.h Normal file
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@@ -0,0 +1,35 @@
/*-------------------------------------------------------------------------
serial390.h
Copyright (C) 2000, Johan Knol <johan.knol AT iduna.nl>
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef SERIAL390_H
#define SERIAL390_H
#warning "Please use <tinibios.h> instead of <serial390.h>"
#include <tinibios.h>
#endif SERIAL390_H

61
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/ds400/ds400rom.h Normal file
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@@ -0,0 +1,61 @@
/*-------------------------------------------------------------------------
ds400rom.h - Interface to DS80C400 ROM functions
Copyright (C) 2000, Kevin Vigor
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef DS400ROM_H_
#define DS400ROM_H_
extern unsigned char init_rom(void __xdata *loMem,
void __xdata *hiMem) __naked;
extern unsigned long task_gettimemillis_long(void) __naked;
extern unsigned char task_getthreadID(void) __naked;
/** Timer reload value for 14.746 MHz crystal. */
#define RELOAD_14_746 0xfb33
/** Timer reload value for 18.432 MHz crystal. */
#define RELOAD_18_432 0xfa00
/** Timer reload value for 29.491 MHz crystal. */
#define RELOAD_29_491 0xfd99
/** Timer reload value for 36.864 MHz crystal. */
#define RELOAD_36_864 0xfd00
/** Timer reload value for 58.982 MHz crystal. */
#define RELOAD_58_982 0xfecc
/** Timer reload value for 73.728 MHz crystal. */
#define RELOAD_73_728 0xfe80
extern unsigned int task_gettickreload(void);
extern void task_settickreload(unsigned);
#endif

194
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/ds80c390.h Normal file
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@@ -0,0 +1,194 @@
/*-------------------------------------------------------------------------
ds80c390.h - Register Declarations for the DALLAS DS80C390 Processor
far from complete, e.g. no CAN
Copyright (C) 2000, Johan Knol <johan.knol AT iduna.nl>
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef DS80C390_H
#define DS80C390_H
__sfr __at (0x80) P4; /* ce3..ce0, a19..a16 */
__sfr __at (0x81) SP; /* stack pointer */
__sfr __at (0x82) DPL; /* data pointer 0 lsb */
__sfr __at (0x83) DPH; /* data pointer 0 msb */
__sfr __at (0x84) DPL1; /* data pointer 1 lsb */
__sfr __at (0x85) DPH1; /* data pointer 1 msb */
__sfr __at (0x86) DPS; /* data pointer select */
__sfr __at (0x87) PCON; /* power control */
__sfr __at (0x88) TCON; /* timer/counter control */
__sbit __at (0x88) IT0;
__sbit __at (0x89) IE0;
__sbit __at (0x8a) IT1;
__sbit __at (0x8b) IE1;
__sbit __at (0x8c) TR0;
__sbit __at (0x8d) TF0;
__sbit __at (0x8e) TR1;
__sbit __at (0x8f) TF1;
__sfr __at (0x89) TMOD; /* timer mode control */
__sfr __at (0x8a) TL0; /* timer 0 lsb */
__sfr __at (0x8b) TL1; /* timer 1 msb */
__sfr __at (0x8c) TH0; /* timer 0 msb */
__sfr __at (0x8d) TH1; /* timer 1 msb */
__sfr __at (0x8e) CKCON; /* clock control */
__sfr __at (0x90) P1;
__sbit __at (0x90) T2;
__sbit __at (0x91) T2EX;
__sbit __at (0x92) RXD1;
__sbit __at (0x93) TXD1;
__sbit __at (0x94) INT2;
__sbit __at (0x95) INT3;
__sbit __at (0x96) INT4;
__sbit __at (0x97) INT5;
__sfr __at (0x91) EXIF; /* external interrupt flag */
__sfr __at (0x92) P4CNT;
__sfr __at (0x93) DPX; /* extended datapointer 0 */
__sfr __at (0x95) DPX1; /* extended datapointer 1 */
__sfr __at (0x98) SCON0; /* serial 0 control */
__sbit __at (0x98) RI_0;
__sbit __at (0x99) TI_0;
__sbit __at (0x9a) RB8_0;
__sbit __at (0x9b) TB8_0;
__sbit __at (0x9c) REN_0;
__sbit __at (0x9d) SM2_0;
__sbit __at (0x9e) SM1_0;
__sbit __at (0x9f) SM0_0;
__sbit __at (0x9f) FE_0; /* depending on SMOD0 */
__sfr __at (0x99) SBUF0; /* serial 0 data buffer */
__sfr __at (0x9b) ESP; /* extended stack pointer */
__sfr __at (0x9c) AP; /* address page */
__sfr __at (0x9d) ACON; /* address control */
__sfr __at (0xa0) P2; /* never mind the sbits */
__sfr __at (0xa1) P5;
__sfr __at (0xa2) P5CNT;
__sfr __at (0xa8) IE; /* interrupt enable */
__sbit __at (0xa8) EX0;
__sbit __at (0xa9) ET0;
__sbit __at (0xaa) EX1;
__sbit __at (0xab) ET1;
__sbit __at (0xac) ES0;
__sbit __at (0xad) ET2;
__sbit __at (0xae) ES1;
__sbit __at (0xaf) EA;
__sfr __at (0xb0) P3;
__sbit __at (0xb0) RXD0;
__sbit __at (0xb1) TXD0;
__sbit __at (0xb2) INT0;
__sbit __at (0xb3) INT1;
__sbit __at (0xb4) T0;
__sbit __at (0xb5) T1;
__sbit __at (0xb6) WR;
__sbit __at (0xb7) RD;
__sfr __at (0xb8) IP; /* interupt priority */
__sbit __at (0xb8) PX0; /* external 0 */
__sbit __at (0xb9) PT0; /* timer 0 */
__sbit __at (0xba) PX1; /* external 1 */
__sbit __at (0xbb) PT1; /* timer 1 */
__sbit __at (0xbc) PS0; /* serial port 0 */
__sbit __at (0xbd) PT2; /* timer 2 */
__sbit __at (0xbe) PS1; /* serial port 1 */
__sfr __at (0xc0) SCON1; /* serial 1 control */
__sbit __at (0xc0) RI_1;
__sbit __at (0xc1) TI_1;
__sbit __at (0xc2) RB8_1;
__sbit __at (0xc3) TB8_1;
__sbit __at (0xc4) REN_1;
__sbit __at (0xc5) SM2_1;
__sbit __at (0xc6) SM1_1;
__sbit __at (0xc7) SM0_1;
__sbit __at (0xc7) FE_1; /* depending on SMOD0 */
__sfr __at (0xc1) SBUF1; /* serial 1 data buffer */
__sfr __at (0xc4) PMR; /* power managment */
__sfr __at (0xc6) MCON; /* memory control register */
__sfr __at (0xc7) TA; /* timed access register */
__sfr __at (0xc8) T2CON; /* timer 2 control */
__sbit __at (0xc8) CP_RL; /* capture/reload */
__sbit __at (0xc9) C_T; /* count/timer */
__sbit __at (0xca) TR2; /* stop/run */
__sbit __at (0xcb) EXEN2;
__sbit __at (0xcc) TCLK;
__sbit __at (0xcd) RCLK;
__sbit __at (0xce) EXF2;
__sbit __at (0xcf) TF2; /* overflow flag */
__sfr __at (0xc9) T2MOD; /* timer 2 mode */
__sfr __at (0xca) RCAP2L; /* timer 2 capture/reload */
__sfr __at (0xca) RTL2; /* depends on CP_RL */
__sfr __at (0xcb) RCAP2H;
__sfr __at (0xcb) RTH2;
__sfr __at (0xcc) TL2; /* timer 2 lsb */
__sfr __at (0xcd) TH2; /* timer 2 msb */
__sfr __at (0xd0) PSW; /* program status word (byte actually) */
__sbit __at (0xd0) P; /* parity */
__sbit __at (0xd1) F1; /* user flag 1 */
__sbit __at (0xd2) OV; /* overflow flag */
__sbit __at (0xd3) RS0; /* register select l */
__sbit __at (0xd4) RS1; /* register select h */
__sbit __at (0xd5) F0; /* user flag 0 */
__sbit __at (0xd6) AC; /* auxiliary carry flag */
__sbit __at (0xd7) CY; /* carry flag */
__sfr __at (0xd1) MCNT0; /* arithmetic accellerator */
__sfr __at (0xd2) MCNT1;
__sfr __at (0xd3) MA;
__sfr __at (0xd4) MB;
__sfr __at (0xd5) MC;
__sfr __at (0xd8) WDCON; /* watch dog */
__sbit __at (0xd8) RWT;
__sbit __at (0xd9) EWT;
__sbit __at (0xda) WDRF;
__sbit __at (0xdb) WDIF;
__sbit __at (0xdc) PFI;
__sbit __at (0xdd) EPFI;
__sbit __at (0xde) POR;
__sbit __at (0xdf) SMOD_1;
__sfr __at (0xe0) ACC; /* accumulator */
__sfr __at (0xe8) EIE; /* extended interrupt enable */
__sbit __at (0xe8) EX2;
__sbit __at (0xe9) EX3;
__sbit __at (0xea) EX4;
__sbit __at (0xeb) EX5;
__sbit __at (0xec) EWDI;
__sbit __at (0xed) C1IE;
__sbit __at (0xee) C0IE;
__sbit __at (0xef) CANBIE;
__sfr __at (0xea) MXAX; /* extended address register */
__sfr __at (0xf0) B; /* aux accumulator */
__sfr __at (0xf8) EIP; /* extended interrupt priority */
__sbit __at (0xf8) PX2;
__sbit __at (0xf9) PX3;
__sbit __at (0xfa) PX4;
__sbit __at (0xfb) PX5;
__sbit __at (0xfc) PWDI;
__sbit __at (0xfd) C1IP;
__sbit __at (0xfe) C0IP;
__sbit __at (0xff) CANBIP;
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2; /* TIMER 2 CAPTURE REGISTER WORD */
#endif /* DS80C390_H */

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/*-------------------------------------------------------------------------
errno.h: Error codes used in the math functions
Copyright (C) 2001, Jesus Calvino-Fraga, jesusc@ieee.org
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
/* Version 1.0 - Initial release */
#ifndef _INC_ERRNO
#define _INC_ERRNO
extern int errno;
/* Error Codes: */
#define EDOM 33 /* Math argument out of domain of functions */
#define ERANGE 34 /* Math result not representable */
#define EILSEQ 84 /* Illegal byte sequence */
/* Bounds-checking interfaces from annex K of the C11 standard. */
#if defined (__STDC_WANT_LIB_EXT1__) && __STDC_WANT_LIB_EXT1__
#ifndef __ERRNO_T_DEFINED
#define __ERRNO_T_DEFINED
typedef int errno_t;
#endif
#endif
#endif /* _INC_ERRNO */

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/*-------------------------------------------------------------------------
float.h - ANSI functions forward declarations
Copyright (C) 1998, Sandeep Dutta . sandeep.dutta@usa.net
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDC51_FLOAT_H
#define __SDC51_FLOAT_H 1
#include <limits.h>
#define FLT_RADIX 2
#define FLT_MANT_DIG 24
#define FLT_EPSILON 1.192092896E-07F
#define FLT_DIG 6
#define FLT_MIN_EXP (-125)
#define FLT_MIN 1.175494351E-38F
#define FLT_MIN_10_EXP (-37)
#define FLT_MAX_EXP (+128)
#define FLT_MAX 3.402823466E+38F
#define FLT_MAX_10_EXP (+38)
#if __STDC_VERSION__ >= 201112L
#define FLT_DECIMAL_DIG 9
#define FLT_TRUE_MIN 1.175494351E-38F
#define FLT_HAS_SUBNORM 0
#endif
#if __SIZEOF_DOUBLE__ == 4
#define DBL_MANT_DIG FLT_MANT_DIG
#define DBL_EPSILON FLT_EPSILON
#define DBL_DIG FLT_DIG
#define DBL_MIN_EXP FLT_MIN_EXP
#define DBL_MIN FLT_MIN
#define DBL_MIN_10_EXP FLT_MIN_10_EXP
#define DBL_MAX_EXP FLT_MAX_EXP
#define DBL_MAX FLT_MAX
#define DBL_MAX_10_EXP FLT_MAX_10_EXP
#if __STDC_VERSION__ >= 201112L
#define DBL_DECIMAL_DIG FLT_DECIMAL_DIG
#define DBL_TRUE_MIN FLT_TRUE_MIN
#define DBL_HAS_SUBNORM FLT_HAS_SUBNORM
#endif
#endif
/* the following deal with IEEE single-precision numbers */
#if defined(__SDCC_FLOAT_LIB)
#define EXCESS 126
#define SIGNBIT ((unsigned long)0x80000000)
#define __INFINITY ((unsigned long)0x7F800000)
#define __NAN ((unsigned long)0xFFC00000)
#define HIDDEN (unsigned long)(1ul << 23)
#define SIGN(fp) (((unsigned long)(fp) >> (8*sizeof(fp)-1)) & 1)
#define EXP(fp) (((unsigned long)(fp) >> 23) & (unsigned int) 0x00FF)
#define MANT(fp) (((fp) & (unsigned long)0x00FFFFFF) | HIDDEN)
#define NORM 0xff000000
#define PACK(s,e,m) ((s) | ((unsigned long)(e) << 23) | (m))
#endif
#ifdef __SDCC_mcs51
#define __SDCC_FLOAT_NONBANKED __nonbanked
#else
#define __SDCC_FLOAT_NONBANKED
#endif
float __uchar2fs (unsigned char) __SDCC_FLOAT_NONBANKED;
float __schar2fs (signed char) __SDCC_FLOAT_NONBANKED;
float __uint2fs (unsigned int) __SDCC_FLOAT_NONBANKED;
float __sint2fs (signed int) __SDCC_FLOAT_NONBANKED;
float __ulong2fs (unsigned long) __SDCC_FLOAT_NONBANKED;
float __slong2fs (signed long) __SDCC_FLOAT_NONBANKED;
unsigned char __fs2uchar (float) __SDCC_FLOAT_NONBANKED;
signed char __fs2schar (float) __SDCC_FLOAT_NONBANKED;
unsigned int __fs2uint (float) __SDCC_FLOAT_NONBANKED;
signed int __fs2sint (float) __SDCC_FLOAT_NONBANKED;
unsigned long __fs2ulong (float) __SDCC_FLOAT_NONBANKED;
signed long __fs2slong (float) __SDCC_FLOAT_NONBANKED;
float __fsadd (float, float) __SDCC_FLOAT_NONBANKED;
float __fssub (float, float) __SDCC_FLOAT_NONBANKED;
float __fsmul (float, float) __SDCC_FLOAT_NONBANKED;
float __fsdiv (float, float) __SDCC_FLOAT_NONBANKED;
_Bool __fslt (float, float) __SDCC_FLOAT_NONBANKED;
_Bool __fseq (float, float) __SDCC_FLOAT_NONBANKED;
_Bool __fsgt (float, float) __SDCC_FLOAT_NONBANKED;
#if defined(__SDCC_FLOAT_LIB) && defined(__SDCC_mcs51) && !defined(__SDCC_USE_XSTACK) && !defined(_SDCC_NO_ASM_LIB_FUNCS)
#define FLOAT_ASM_MCS51
/* This adds extra code for proper round-off, in
an attempt to match the results from gcc. */
#define FLOAT_FULL_ACCURACY
/* This adds about 66 bytes to the code size and
significantly speeds up shift operations more
than 8 bits (common when subtracting numbers
of significantly different magnitude and scaling
to fixed point) */
#define FLOAT_SHIFT_SPEEDUP
#define sign_a psw.1
#define sign_b psw.5
#define exp_a dpl
#define exp_b dph
#endif /* using mcs51 assembly */
#endif /* __SDC51_FLOAT_H */

19
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/* Macro voodoo rewriting GCC-style attributes to C23-style attributes. */
/* Can be used via "--include gcc_attr.h" on the command line. */
#if __STDC_VERSION__ < 202311L
/* Not in C23 mode => remove GCC-style attributes */
#warning "Rewriting GCC-style to C23-style attributes requires C23. Ignoring all GCC-style attributes."
#define __attribute__(__GCC_ATTR_ARG)
#else
/* In C23 mode => translate to C23-style attributes */
/* e.g. from __attribute__((packed, foo(bar))) to [[packed, foo(bar)]] */
#warning "Rewriting GCC-style to C23-style attributes. Please check compatibility."
#define __GCC_ATTR_LIST_ARGS(...) __VA_ARGS__
#define __GCC_ATTR_UNWRAP_ARG(__GCC_ATTR_ARG) __GCC_ATTR_ARG
#define __attribute__(__GCC_ATTR_ARG) [[__GCC_ATTR_UNWRAP_ARG(__GCC_ATTR_LIST_ARGS __GCC_ATTR_ARG)]]
#endif

650
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/hc08/mc68hc908apxx.h Normal file
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/*-------------------------------------------------------------------------
mc68hc908apxx.h - register declarations for Motorola MC68HC908AP16/32/64
Copyright (C) 2004, Lucas Loizaga <lucas.loizaga AT ingenieria-inversa.com.ar>
Based on mc68hc908gp32.h,
Written By - Juan Gonzalez <juan AT iearobotics.com>
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef MC68HC908APXX_H
#define MC68HC908APXX_H
#ifndef _UINT8
#define _UINT8 unsigned char
#endif
#ifndef _UINT16
#define _UINT16 unsigned int
#endif
#ifndef _VOLDATA
#define _VOLDATA volatile __data
#endif
#ifndef _VOLXDATA
#define _VOLXDATA volatile __xdata
#endif
struct __hc08_bits
{
unsigned int bit0:1;
unsigned int bit1:1;
unsigned int bit2:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
};
_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
#define PORTA PTA /* Alias for PTA */
#define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
#define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
#define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
#define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
#define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
#define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
#define PTA6 ((struct __hc08_bits *)(&PTA))->bit6
#define PTA7 ((struct __hc08_bits *)(&PTA))->bit7
_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
#define PORTB PTB /* Alias for PTB */
#define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
#define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
#define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
#define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
#define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
#define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
#define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
#define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
_VOLDATA _UINT8 __at 0x02 PTC; /* Port C Data Register */
#define PORTC PTC /* Alias for PTC */
#define PTC0 ((struct __hc08_bits *)(&PTC))->bit0
#define PTC1 ((struct __hc08_bits *)(&PTC))->bit1
#define PTC2 ((struct __hc08_bits *)(&PTC))->bit2
#define PTC3 ((struct __hc08_bits *)(&PTC))->bit3
#define PTC4 ((struct __hc08_bits *)(&PTC))->bit4
#define PTC5 ((struct __hc08_bits *)(&PTC))->bit5
#define PTC6 ((struct __hc08_bits *)(&PTC))->bit6
#define PTC7 ((struct __hc08_bits *)(&PTC))->bit7
_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
#define PORTD PTD /* Alias for PTD */
#define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
#define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
#define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
#define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
#define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
#define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
#define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
#define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
#define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
#define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
#define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
#define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
#define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
#define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
#define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
#define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
#define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
#define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
#define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
#define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
#define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
#define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
#define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
#define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
_VOLDATA _UINT8 __at 0x06 DDRC; /* Data Direction Register C */
#define DDRC0 ((struct __hc08_bits *)(&DDRC))->bit0
#define DDRC1 ((struct __hc08_bits *)(&DDRC))->bit1
#define DDRC2 ((struct __hc08_bits *)(&DDRC))->bit2
#define DDRC3 ((struct __hc08_bits *)(&DDRC))->bit3
#define DDRC4 ((struct __hc08_bits *)(&DDRC))->bit4
#define DDRC5 ((struct __hc08_bits *)(&DDRC))->bit5
#define DDRC6 ((struct __hc08_bits *)(&DDRC))->bit6
#define DDRC7 ((struct __hc08_bits *)(&DDRC))->bit7
_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
#define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
#define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
#define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
#define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
#define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
#define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
#define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
#define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
_VOLDATA _UINT8 __at 0x0C LEDA; /* PORTA Led Control Register */
#define LEDA0 ((struct __hc08_bits *)(&LEDA))->bit0
#define LEDA1 ((struct __hc08_bits *)(&LEDA))->bit1
#define LEDA2 ((struct __hc08_bits *)(&LEDA))->bit2
#define LEDA3 ((struct __hc08_bits *)(&LEDA))->bit3
#define LEDA4 ((struct __hc08_bits *)(&LEDA))->bit4
#define LEDA5 ((struct __hc08_bits *)(&LEDA))->bit5
#define LEDA6 ((struct __hc08_bits *)(&LEDA))->bit6
#define LEDA7 ((struct __hc08_bits *)(&LEDA))->bit7
_VOLDATA _UINT8 __at 0x10 SPCR; /* SPI Control Register */
#define SPRIE ((struct __hc08_bits *)(&SPCR))->bit7
#define DMAS ((struct __hc08_bits *)(&SPCR))->bit6
#define SPMSTR ((struct __hc08_bits *)(&SPCR))->bit5
#define CPOL ((struct __hc08_bits *)(&SPCR))->bit4
#define CPHA ((struct __hc08_bits *)(&SPCR))->bit3
#define SPWOM ((struct __hc08_bits *)(&SPCR))->bit2
#define SPE ((struct __hc08_bits *)(&SPCR))->bit1
#define SPTIE ((struct __hc08_bits *)(&SPCR))->bit0
_VOLDATA _UINT8 __at 0x11 SPSCR; /* SPI Status and Control Register */
#define SPRF ((struct __hc08_bits *)(&SPSCR))->bit7
#define ERRIE ((struct __hc08_bits *)(&SPSCR))->bit6
#define OVRF ((struct __hc08_bits *)(&SPSCR))->bit5
#define MODF ((struct __hc08_bits *)(&SPSCR))->bit4
#define SPTE ((struct __hc08_bits *)(&SPSCR))->bit3
#define MODFEN ((struct __hc08_bits *)(&SPSCR))->bit2
#define SPR1 ((struct __hc08_bits *)(&SPSCR))->bit1
#define SPR0 ((struct __hc08_bits *)(&SPSCR))->bit0
_VOLDATA _UINT8 __at 0x12 SPDR; /* SPI Data Register */
_VOLDATA _UINT8 __at 0x13 SCC1; /* SCI Control Register 1 */
#define LOOPS ((struct __hc08_bits *)(&SCC1))->bit7
#define ENSCI ((struct __hc08_bits *)(&SCC1))->bit6
#define TXINV ((struct __hc08_bits *)(&SCC1))->bit5
#define M ((struct __hc08_bits *)(&SCC1))->bit4
#define WAKE ((struct __hc08_bits *)(&SCC1))->bit3
#define ILTY ((struct __hc08_bits *)(&SCC1))->bit2
#define PEN ((struct __hc08_bits *)(&SCC1))->bit1
#define PTY ((struct __hc08_bits *)(&SCC1))->bit0
_VOLDATA _UINT8 __at 0x14 SCC2; /* SCI Control Register 2 */
#define SCTIE ((struct __hc08_bits *)(&SCC2))->bit7
#define TCIE ((struct __hc08_bits *)(&SCC2))->bit6
#define SCRIE ((struct __hc08_bits *)(&SCC2))->bit5
#define ILIE ((struct __hc08_bits *)(&SCC2))->bit4
#define TE ((struct __hc08_bits *)(&SCC2))->bit3
#define RE ((struct __hc08_bits *)(&SCC2))->bit2
#define WRU ((struct __hc08_bits *)(&SCC2))->bit1
#define SBK ((struct __hc08_bits *)(&SCC2))->bit0
_VOLDATA _UINT8 __at 0x15 SCC3; /* SCI Control Register 3 */
#define SCC3_R8 ((struct __hc08_bits *)(&SCC3))->bit7
#define SCC3_T8 ((struct __hc08_bits *)(&SCC3))->bit6
#define DMARE ((struct __hc08_bits *)(&SCC3))->bit5
#define DMATE ((struct __hc08_bits *)(&SCC3))->bit4
#define ORIE ((struct __hc08_bits *)(&SCC3))->bit3
#define NEIE ((struct __hc08_bits *)(&SCC3))->bit2
#define FEIE ((struct __hc08_bits *)(&SCC3))->bit1
#define PEIE ((struct __hc08_bits *)(&SCC3))->bit0
_VOLDATA _UINT8 __at 0x16 SCS1; /* SCI Status Register 1 */
#define SCTE ((struct __hc08_bits *)(&SCS1))->bit7
#define TC ((struct __hc08_bits *)(&SCS1))->bit6
#define SCRF ((struct __hc08_bits *)(&SCS1))->bit5
#define IDLE ((struct __hc08_bits *)(&SCS1))->bit4
#define OR ((struct __hc08_bits *)(&SCS1))->bit3
#define NF ((struct __hc08_bits *)(&SCS1))->bit2
#define FE ((struct __hc08_bits *)(&SCS1))->bit1
#define PE ((struct __hc08_bits *)(&SCS1))->bit0
_VOLDATA _UINT8 __at 0x17 SCS2; /* SCI Status Register 2 */
#define RPF ((struct __hc08_bits *)(&SCS2))->bit0
#define BKF ((struct __hc08_bits *)(&SCS2))->bit1
/* Bits 2-7 not implemented */
_VOLDATA _UINT8 __at 0x18 SCDR; /* SCI Data Register */
_VOLDATA _UINT8 __at 0x19 SCBR; /* SCI Baud Rate Register */
#define SCP1 ((struct __hc08_bits *)(&SCBR))->bit5
#define SCP0 ((struct __hc08_bits *)(&SCBR))->bit4
#define R ((struct __hc08_bits *)(&SCBR))->bit3
#define SCR2 ((struct __hc08_bits *)(&SCBR))->bit2
#define SCR1 ((struct __hc08_bits *)(&SCBR))->bit1
#define SCR0 ((struct __hc08_bits *)(&SCBR))->bit0
/*-- Bits 6 and 7 do not exist */
_VOLDATA _UINT8 __at 0x1a INTKBSCR; /* Keyboard Status and Control Register */
#define KEYF ((struct __hc08_bits *)(&INTKBSCR))->bit3
#define ACKK ((struct __hc08_bits *)(&INTKBSCR))->bit2
#define IMASKK ((struct __hc08_bits *)(&INTKBSCR))->bit1
#define MODEK ((struct __hc08_bits *)(&INTKBSCR))->bit0
/*-- Bits 4-7 do not exist */
_VOLDATA _UINT8 __at 0x1b INTKBIER; /* Keyboard Interrupt Enable Register */
#define KBIE7 ((struct __hc08_bits *)(&INTKBIER))->bit7
#define KBIE6 ((struct __hc08_bits *)(&INTKBIER))->bit6
#define KBIE5 ((struct __hc08_bits *)(&INTKBIER))->bit5
#define KBIE4 ((struct __hc08_bits *)(&INTKBIER))->bit4
#define KBIE3 ((struct __hc08_bits *)(&INTKBIER))->bit3
#define KBIE2 ((struct __hc08_bits *)(&INTKBIER))->bit2
#define KBIE1 ((struct __hc08_bits *)(&INTKBIER))->bit1
#define KBIE0 ((struct __hc08_bits *)(&INTKBIER))->bit0
_VOLDATA _UINT8 __at 0x1C INTSCR2; /* Keyboard Status and Control Register */
#define PUC0ENB ((struct __hc08_bits *)(&INTSCR2))->bit6
#define IRQF2 ((struct __hc08_bits *)(&INTSCR2))->bit3
#define ACK2 ((struct __hc08_bits *)(&INTSCR2))->bit2
#define IMASK2 ((struct __hc08_bits *)(&INTSCR2))->bit1
#define MODE2 ((struct __hc08_bits *)(&INTSCR2))->bit0
_VOLDATA _UINT8 __at 0x1D CONFIG2; /* Configuration Register 2 */
/* CONFIG2 is one-time writeble, so can't use bitfields */
_VOLDATA _UINT8 __at 0x1E INTSCR1; /* IRQ status/control */
#define IRQF1 ((struct __hc08_bits *)(&INTSCR1))->bit3
#define ACK1 ((struct __hc08_bits *)(&INTSCR1))->bit2
#define IMASK1 ((struct __hc08_bits *)(&INTSCR1))->bit1
#define MODE1 ((struct __hc08_bits *)(&INTSCR1))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
/* CONFIG1 is one-time writeable, so can't use bitfields */
_VOLDATA _UINT8 __at 0x20 T1SC; /* TIM 1 Status and Control */
#define PS0 ((struct __hc08_bits *)(&T1SC))->bit0
#define PS1 ((struct __hc08_bits *)(&T1SC))->bit1
#define PS2 ((struct __hc08_bits *)(&T1SC))->bit2
#define TRST ((struct __hc08_bits *)(&T1SC))->bit4
#define TSTOP ((struct __hc08_bits *)(&T1SC))->bit5
#define TOIE ((struct __hc08_bits *)(&T1SC))->bit6
#define TOF ((struct __hc08_bits *)(&T1SC))->bit7
_VOLDATA _UINT16 __at 0x21 T1CNT; /* TIM1 Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x21 T1CNTH; /* TIM1 Counter Register High */
_VOLDATA _UINT8 __at 0x22 T1CNTL; /* TIM1 Counter Register Low */
_VOLDATA _UINT16 __at 0x23 T1MOD; /* TIM1 Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x23 T1MODH; /* TIM1 Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x24 T1MODL; /* TIM1 Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x25 T1SC0; /* TIM1 Channel 0 Status and Control Register */
#define CH0MAX ((struct __hc08_bits *)(&T1SC0))->bit0
#define TOV0 ((struct __hc08_bits *)(&T1SC0))->bit1
#define ELS0A ((struct __hc08_bits *)(&T1SC0))->bit2
#define ELS0B ((struct __hc08_bits *)(&T1SC0))->bit3
#define MS0A ((struct __hc08_bits *)(&T1SC0))->bit4
#define MS0B ((struct __hc08_bits *)(&T1SC0))->bit5
#define CH0IE ((struct __hc08_bits *)(&T1SC0))->bit6
#define CH0F ((struct __hc08_bits *)(&T1SC0))->bit7
_VOLDATA _UINT16 __at 0x26 T1CH0; /* TIM1 Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x26 T1CH0H; /* TIM1 Channel 0 Register High */
_VOLDATA _UINT8 __at 0x27 T1CH0L; /* TIM1 Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x28 T1SC1; /* TIM1 Channel 1 Status and Control Register */
#define CH1MAX ((struct __hc08_bits *)(&T1SC1))->bit0
#define TOV1 ((struct __hc08_bits *)(&T1SC1))->bit1
#define ELS1A ((struct __hc08_bits *)(&T1SC1))->bit2
#define ELS1B ((struct __hc08_bits *)(&T1SC1))->bit3
#define MS1A ((struct __hc08_bits *)(&T1SC1))->bit4
#define CH1IE ((struct __hc08_bits *)(&T1SC1))->bit6
#define CH1F ((struct __hc08_bits *)(&T1SC1))->bit7
_VOLDATA _UINT16 __at 0x29 T1CH1; /* TIM1 Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x29 T1CH1H; /* TIM1 Channel 1 Register High */
_VOLDATA _UINT8 __at 0x2A T1CH1L; /* TIM1 Channel 1 Register Low */
/*------------------*/
/* TIM 2 REGISTERS */
/*------------------*/
_VOLDATA _UINT8 __at 0x2B T2SC; /* TIM 2 Status and Control */
#define PS0_2 ((struct __hc08_bits *)(&T2SC))->bit0
#define PS1_2 ((struct __hc08_bits *)(&T2SC))->bit1
#define PS2_2 ((struct __hc08_bits *)(&T2SC))->bit2
#define TRST_2 ((struct __hc08_bits *)(&T2SC))->bit4
#define TSTOP_2 ((struct __hc08_bits *)(&T2SC))->bit5
#define TOIE_2 ((struct __hc08_bits *)(&T2SC))->bit6
#define TOF_2 ((struct __hc08_bits *)(&T2SC))->bit7
_VOLDATA _UINT16 __at 0x2C T2CNT; /* TIM2 Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x2C T2CNTH; /* TIM2 Counter Register High */
_VOLDATA _UINT8 __at 0x2D T2CNTL; /* TIM2 Counter Register Low */
_VOLDATA _UINT16 __at 0x2E T2MOD; /* TIM2 Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x2E T2MODH; /* TIM2 Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x2F T2MODL; /* TIM2 Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x30 T2SC0; /* TIM2 Channel 0 Status and Control Register */
#define CH0MAX_2 ((struct __hc08_bits *)(&T2SC0))->bit0
#define TOV0_2 ((struct __hc08_bits *)(&T2SC0))->bit1
#define ELS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit2
#define ELS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit3
#define MS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit4
#define MS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit5
#define CH0IE_2 ((struct __hc08_bits *)(&T2SC0))->bit6
#define CH0F_2 ((struct __hc08_bits *)(&T2SC0))->bit7
_VOLDATA _UINT16 __at 0x31 T2CH0; /* TIM2 Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x31 T2CH0H; /* TIM2 Channel 0 Register High */
_VOLDATA _UINT8 __at 0x32 T2CH0L; /* TIM2 Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x33 T2SC1; /* TIM2 Channel 1 Status and Control Register */
#define CH1MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0
#define TOV1_2 ((struct __hc08_bits *)(&T2SC1))->bit1
#define ELS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit2
#define ELS1B_2 ((struct __hc08_bits *)(&T2SC1))->bit3
#define MS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit4
#define CH1IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6
#define CH1F_2 ((struct __hc08_bits *)(&T2SC1))->bit7
_VOLDATA _UINT16 __at 0x34 T2CH1; /* TIM2 Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x34 T2CH1H; /* TIM2 Channel 1 Register High */
_VOLDATA _UINT8 __at 0x35 T2CH1L; /* TIM2 Channel 1 Register Low */
_VOLDATA _UINT8 __at 0x36 PCTL; /* PLL Control Register */
#define PLLIE ((struct __hc08_bits *)(&PCTL))->bit7
#define PLLF ((struct __hc08_bits *)(&PCTL))->bit6
#define PLLON ((struct __hc08_bits *)(&PCTL))->bit5
#define BCS ((struct __hc08_bits *)(&PCTL))->bit4
#define PRE1 ((struct __hc08_bits *)(&PCTL))->bit3
#define PRE0 ((struct __hc08_bits *)(&PCTL))->bit2
#define VPR1 ((struct __hc08_bits *)(&PCTL))->bit1
#define VPR0 ((struct __hc08_bits *)(&PCTL))->bit0
_VOLDATA _UINT8 __at 0x37 PBWC; /* PLL Bandwidth Control Register */
#define AUTO ((struct __hc08_bits *)(&PBWC))->bit7
#define LOCK ((struct __hc08_bits *)(&PBWC))->bit6
#define ACQ ((struct __hc08_bits *)(&PBWC))->bit5
/* Bits 1-4, Unimplemented */
/* Bit 0, Reserved */
_VOLDATA _UINT8 __at 0x38 PMSH; /* PLL Multiplier Select High */
#define MUL11 ((struct __hc08_bits *)(&PMSH))->bit3
#define MUL10 ((struct __hc08_bits *)(&PMSH))->bit2
#define MUL9 ((struct __hc08_bits *)(&PMSH))->bit1
#define MUL8 ((struct __hc08_bits *)(&PMSH))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x39 PMSL; /* PLL Multiplir Select Low */
#define MUL7 ((struct __hc08_bits *)(&PMSL))->bit7
#define MUL6 ((struct __hc08_bits *)(&PMSL))->bit6
#define MUL5 ((struct __hc08_bits *)(&PMSL))->bit5
#define MUL4 ((struct __hc08_bits *)(&PMSL))->bit4
#define MUL3 ((struct __hc08_bits *)(&PMSL))->bit3
#define MUL2 ((struct __hc08_bits *)(&PMSL))->bit2
#define MUL1 ((struct __hc08_bits *)(&PMSL))->bit1
#define MUL0 ((struct __hc08_bits *)(&PMSL))->bit0
_VOLDATA _UINT8 __at 0x3a PMRS; /* PLL VCO Select Range */
#define VRS7 ((struct __hc08_bits *)(&PMRS))->bit7
#define VRS6 ((struct __hc08_bits *)(&PMRS))->bit6
#define VRS5 ((struct __hc08_bits *)(&PMRS))->bit5
#define VRS4 ((struct __hc08_bits *)(&PMRS))->bit4
#define VRS3 ((struct __hc08_bits *)(&PMRS))->bit3
#define VRS2 ((struct __hc08_bits *)(&PMRS))->bit2
#define VRS1 ((struct __hc08_bits *)(&PMRS))->bit1
#define VRS0 ((struct __hc08_bits *)(&PMRS))->bit0
_VOLDATA _UINT8 __at 0x3b PMDS; /* PLL Reference Divider Select Register */
#define RDS3 ((struct __hc08_bits *)(&PMDS))->bit3
#define RDS2 ((struct __hc08_bits *)(&PMDS))->bit2
#define RDS1 ((struct __hc08_bits *)(&PMDS))->bit1
#define RDS0 ((struct __hc08_bits *)(&PMDS))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x40 IRSCC1; /* SCI Control Register 1 */
#define LOOPS_IR ((struct __hc08_bits *)(&IRSCC1))->bit7
#define ENSCI_IR ((struct __hc08_bits *)(&IRSCC1))->bit6
#define TXINV_IR ((struct __hc08_bits *)(&IRSCC1))->bit5
#define M_IR ((struct __hc08_bits *)(&IRSCC1))->bit4
#define WAKE_IR ((struct __hc08_bits *)(&IRSCC1))->bit3
#define ILTY_IR ((struct __hc08_bits *)(&IRSCC1))->bit2
#define PEN_IR ((struct __hc08_bits *)(&IRSCC1))->bit1
#define PTY_IR ((struct __hc08_bits *)(&IRSCC1))->bit0
_VOLDATA _UINT8 __at 0x41 IRSCC2; /* SCI Control Register 2 */
#define SCTIE_IR ((struct __hc08_bits *)(&IRSCC2))->bit7
#define TCIE_IR ((struct __hc08_bits *)(&IRSCC2))->bit6
#define SCRIE_IR ((struct __hc08_bits *)(&IRSCC2))->bit5
#define ILIE_IR ((struct __hc08_bits *)(&IRSCC2))->bit4
#define TE_IR ((struct __hc08_bits *)(&IRSCC2))->bit3
#define RE_IR ((struct __hc08_bits *)(&IRSCC2))->bit2
#define WRU_IR ((struct __hc08_bits *)(&IRSCC2))->bit1
#define SBK_IR ((struct __hc08_bits *)(&IRSCC2))->bit0
_VOLDATA _UINT8 __at 0x42 IRSCC3; /* SCI Control Register 3 */
#define SCC3_R8_IR ((struct __hc08_bits *)(&IRSCC3))->bit7
#define SCC3_T8_IR ((struct __hc08_bits *)(&IRSCC3))->bit6
#define DMARE_IR ((struct __hc08_bits *)(&IRSCC3))->bit5
#define DMATE_IR ((struct __hc08_bits *)(&IRSCC3))->bit4
#define ORIE_IR ((struct __hc08_bits *)(&IRSCC3))->bit3
#define NEIE_IR ((struct __hc08_bits *)(&IRSCC3))->bit2
#define FEIE_IR ((struct __hc08_bits *)(&IRSCC3))->bit1
#define PEIE_IR ((struct __hc08_bits *)(&IRSCC3))->bit0
_VOLDATA _UINT8 __at 0x43 IRSCS1; /* SCI Status Register 1 */
#define SCTE_IR ((struct __hc08_bits *)(&IRSCS1))->bit7
#define TC_IR ((struct __hc08_bits *)(&IRSCS1))->bit6
#define SCRF_IR ((struct __hc08_bits *)(&IRSCS1))->bit5
#define IDLE_IR ((struct __hc08_bits *)(&IRSCS1))->bit4
#define OR_IR ((struct __hc08_bits *)(&IRSCS1))->bit3
#define NF_IR ((struct __hc08_bits *)(&IRSCS1))->bit2
#define FE_IR ((struct __hc08_bits *)(&IRSCS1))->bit1
#define PE_IR ((struct __hc08_bits *)(&IRSCS1))->bit0
_VOLDATA _UINT8 __at 0x44 IRSCS2; /* SCI Status Register 2 */
#define RPF_IR ((struct __hc08_bits *)(&IRSCS2))->bit0
#define BKF_IR ((struct __hc08_bits *)(&IRSCS2))->bit1
/* Bits 2-7 not implemented */
_VOLDATA _UINT8 __at 0x45 IRSCDR; /* SCI Data Register */
_VOLDATA _UINT8 __at 0x46 IRSCBR; /* SCI Baud Rate Register */
#define CKS_IR ((struct __hc08_bits *)(&IRSCBR))->bit7
#define SCP1_IR ((struct __hc08_bits *)(&IRSCBR))->bit5
#define SCP0_IR ((struct __hc08_bits *)(&IRSCBR))->bit4
#define SCR2_IR ((struct __hc08_bits *)(&IRSCBR))->bit2
#define SCR1_IR ((struct __hc08_bits *)(&IRSCBR))->bit1
#define SCR0_IR ((struct __hc08_bits *)(&IRSCBR))->bit0
_VOLDATA _UINT8 __at 0x47 IRSCIRCR; /* SCI Baud Rate Register */
#define TNP1_IR ((struct __hc08_bits *)(&IRSCIRCR))->bit2
#define TNP0_IR ((struct __hc08_bits *)(&IRSCIRCR))->bit1
#define IREN_IR ((struct __hc08_bits *)(&IRSCIRCR))->bit0
_VOLDATA _UINT8 __at 0x48 MMADR; /* MMIIC Address Register. */
#define MMAD7 ((struct __hc08_bits *)(&MMADR))->bit7
#define MMAD6 ((struct __hc08_bits *)(&MMADR))->bit6
#define MMAD5 ((struct __hc08_bits *)(&MMADR))->bit5
#define MMAD4 ((struct __hc08_bits *)(&MMADR))->bit4
#define MMAD3 ((struct __hc08_bits *)(&MMADR))->bit3
#define MMAD2 ((struct __hc08_bits *)(&MMADR))->bit2
#define MMAD1 ((struct __hc08_bits *)(&MMADR))->bit1
#define MMEXTAD ((struct __hc08_bits *)(&MMADR))->bit0
_VOLDATA _UINT8 __at 0x49 MMCR1; /* MMIIC Control Register 1. */
#define MMEN ((struct __hc08_bits *)(&MMCR1))->bit7
#define MMIEN ((struct __hc08_bits *)(&MMCR1))->bit6
#define MMCLRBB ((struct __hc08_bits *)(&MMCR1))->bit5
#define MMTXAK ((struct __hc08_bits *)(&MMCR1))->bit3
#define REPSEN ((struct __hc08_bits *)(&MMCR1))->bit2
#define MMCRCBYTE ((struct __hc08_bits *)(&MMCR1))->bit1
_VOLDATA _UINT8 __at 0x4a MMCR2; /* MMIIC Control Register 2. */
#define MMALIF ((struct __hc08_bits *)(&MMCR2))->bit7
#define MMNAKIF ((struct __hc08_bits *)(&MMCR2))->bit6
#define MMBB ((struct __hc08_bits *)(&MMCR2))->bit5
#define MMAST ((struct __hc08_bits *)(&MMCR2))->bit4
#define MMRW ((struct __hc08_bits *)(&MMCR2))->bit3
#define MMCRCEF ((struct __hc08_bits *)(&MMCR2))->bit0
_VOLDATA _UINT8 __at 0x4B MMSR; /* MMIIC Status Register. */
#define MMRXIF ((struct __hc08_bits *)(&MMSR))->bit7
#define MMTXIF ((struct __hc08_bits *)(&MMSR))->bit6
#define MMATCH ((struct __hc08_bits *)(&MMSR))->bit5
#define MMSRW ((struct __hc08_bits *)(&MMSR))->bit4
#define MMRXAK ((struct __hc08_bits *)(&MMSR))->bit3
#define MMCRCBF ((struct __hc08_bits *)(&MMSR))->bit2
#define MMTXBE ((struct __hc08_bits *)(&MMSR))->bit1
#define MMRXBF ((struct __hc08_bits *)(&MMSR))->bit0
_VOLDATA _UINT8 __at 0x4C MMDTR; /* MMIIC Data Transmit Register */
_VOLDATA _UINT8 __at 0x4D MMDRR; /* MMIIC Data Receive Register */
_VOLDATA _UINT8 __at 0x4E MMCRDR; /* MMIIC CRC Data Register */
_VOLDATA _UINT8 __at 0x4F MMFDR; /* MMIIC Frecuency Divider Register */
#define MMBR2 ((struct __hc08_bits *)(&MMFDR))->bit2
#define MMBR1 ((struct __hc08_bits *)(&MMFDR))->bit1
#define MMBR0 ((struct __hc08_bits *)(&MMFDR))->bit0
_VOLDATA _UINT8 __at 0x51 TBCR; /* Time Base Module Control */
#define TBIF ((struct __hc08_bits *)(&TBCR))->bit7
#define TBR2 ((struct __hc08_bits *)(&TBCR))->bit6
#define TBR1 ((struct __hc08_bits *)(&TBCR))->bit5
#define TBR0 ((struct __hc08_bits *)(&TBCR))->bit4
#define TACK ((struct __hc08_bits *)(&TBCR))->bit3
#define TBIE ((struct __hc08_bits *)(&TBCR))->bit2
#define TBON ((struct __hc08_bits *)(&TBCR))->bit1
/* Bit 0 Reserved */
_VOLDATA _UINT8 __at 0x57 ADSCR; /* Analog-to-Digital Status and Control Reg. */
#define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
#define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
#define ADCO ((struct __hc08_bits *)(&ADSCR))->bit5
#define ADCH4 ((struct __hc08_bits *)(&ADSCR))->bit4
#define ADCH3 ((struct __hc08_bits *)(&ADSCR))->bit3
#define ADCH2 ((struct __hc08_bits *)(&ADSCR))->bit2
#define ADCH1 ((struct __hc08_bits *)(&ADSCR))->bit1
#define ADCH0 ((struct __hc08_bits *)(&ADSCR))->bit0
_VOLDATA _UINT8 __at 0x58 ADCLK; /* Analog-to-Digital Clock */
#define ADIV2 ((struct __hc08_bits *)(&ADCLK))->bit7
#define ADIV1 ((struct __hc08_bits *)(&ADCLK))->bit6
#define ADIV0 ((struct __hc08_bits *)(&ADCLK))->bit5
#define ADICLK ((struct __hc08_bits *)(&ADCLK))->bit4
#define ADMODE1 ((struct __hc08_bits *)(&ADCLK))->bit3
#define ADMODE0 ((struct __hc08_bits *)(&ADCLK))->bit2
_VOLDATA _UINT8 __at 0x59 ADRH0; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x5a ADRL0; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x5b ADRL1; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x5c ADRL2; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x5d ADRL3; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x5e ADASCR; /* ADC Auto Scan Control */
#define ASCAN ((struct __hc08_bits *)(&ADCLK))->bit0
#define AUTO0 ((struct __hc08_bits *)(&ADCLK))->bit1
#define AUTO1 ((struct __hc08_bits *)(&ADCLK))->bit2
_VOLXDATA _UINT8 __at 0xfe00 SBSR; /* SIM Break Status Register */
#define SBSW ((struct __hc08_bits *)(&SBSR))->bit1
_VOLXDATA _UINT8 __at 0xfe01 SRSR; /* SIM Reset Status Register */
#define LVI ((struct __hc08_bits *)(&SRSR))->bit1
#define MODRST ((struct __hc08_bits *)(&SRSR))->bit2
#define ILAD ((struct __hc08_bits *)(&SRSR))->bit3
#define ILOP ((struct __hc08_bits *)(&SRSR))->bit4
#define COP ((struct __hc08_bits *)(&SRSR))->bit5
#define PIN ((struct __hc08_bits *)(&SRSR))->bit6
#define POR ((struct __hc08_bits *)(&SRSR))->bit7
/* Bit 0 unimplemented */
_VOLXDATA _UINT8 __at 0xfe03 SBFCR; /* SIM Break Flag Control Register */
#define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
#define IF1 ((struct __hc08_bits *)(&INT1))->bit2
#define IF2 ((struct __hc08_bits *)(&INT1))->bit3
#define IF3 ((struct __hc08_bits *)(&INT1))->bit4
#define IF4 ((struct __hc08_bits *)(&INT1))->bit5
#define IF5 ((struct __hc08_bits *)(&INT1))->bit6
#define IF6 ((struct __hc08_bits *)(&INT1))->bit7
/* Bits 0-1 Reserved */
_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
#define IF14 ((struct __hc08_bits *)(&INT2))->bit7
#define IF13 ((struct __hc08_bits *)(&INT2))->bit6
#define IF12 ((struct __hc08_bits *)(&INT2))->bit5
#define IF11 ((struct __hc08_bits *)(&INT2))->bit4
#define IF10 ((struct __hc08_bits *)(&INT2))->bit3
#define IF9 ((struct __hc08_bits *)(&INT2))->bit2
#define IF8 ((struct __hc08_bits *)(&INT2))->bit1
#define IF7 ((struct __hc08_bits *)(&INT2))->bit0
_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
#define IF21 ((struct __hc08_bits *)(&INT3))->bit6
#define IF20 ((struct __hc08_bits *)(&INT3))->bit5
#define IF19 ((struct __hc08_bits *)(&INT3))->bit4
#define IF18 ((struct __hc08_bits *)(&INT3))->bit3
#define IF17 ((struct __hc08_bits *)(&INT3))->bit2
#define IF16 ((struct __hc08_bits *)(&INT3))->bit1
#define IF15 ((struct __hc08_bits *)(&INT3))->bit0
_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
#define PGM ((struct __hc08_bits *)(&FLCR))->bit0
#define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
#define MASS ((struct __hc08_bits *)(&FLCR))->bit2
#define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
_VOLXDATA _UINT8 __at 0xfe09 FLBPR; /* FLASH Block Protect Register */
#define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
#define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
#define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
#define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
#define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
#define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
#define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
#define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
_VOLXDATA _UINT16 __at 0xfe0C BRK; /* Break Address High & Low Registers */
_VOLXDATA _UINT8 __at 0xfe0C BRKH; /* Break Address High Register */
_VOLXDATA _UINT8 __at 0xfe0D BRKL; /* Break Address Low Register */
_VOLXDATA _UINT8 __at 0xfe0b BRKSCR; /* Break Status and Control Register */
#define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
#define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
_VOLXDATA _UINT8 __at 0xfe0c LVISR; /* Low voltage detect */
#define LVIOUT ((struct __hc08_bits *)(&LVISR))->bit7
_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
#endif

550
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/hc08/mc68hc908gp32.h Normal file
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@@ -0,0 +1,550 @@
/*-------------------------------------------------------------------------
mc68hc908gp.h - Register Declarations for Motorola MC68HC908GP32
Copyright (C) 2004, Juan Gonzalez <juan@iearobotics.com>
Based on mc68hc908qy.h,
Written By - Erik Petrich epetrich@users.sourceforge.net (2003)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef _MC68HC908GP32_H
#define _MC68HC908GP32_H
#ifndef _UINT8
#define _UINT8 unsigned char
#endif
#ifndef _UINT16
#define _UINT16 unsigned int
#endif
#ifndef _VOLDATA
#define _VOLDATA volatile __data
#endif
#ifndef _VOLXDATA
#define _VOLXDATA volatile __xdata
#endif
struct __hc08_bits
{
unsigned int bit0:1;
unsigned int bit1:1;
unsigned int bit2:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
};
_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
#define PORTA PTA /* Alias for PTA */
#define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
#define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
#define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
#define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
#define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
#define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
#define PTA6 ((struct __hc08_bits *)(&PTA))->bit6
#define PTA7 ((struct __hc08_bits *)(&PTA))->bit7
_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
#define PORTB PTB /* Alias for PTB */
#define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
#define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
#define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
#define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
#define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
#define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
#define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
#define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
_VOLDATA _UINT8 __at 0x02 PTC; /* Port C Data Register */
#define PORTC PTC /* Alias for PTC */
#define PTC0 ((struct __hc08_bits *)(&PTC))->bit0
#define PTC1 ((struct __hc08_bits *)(&PTC))->bit1
#define PTC2 ((struct __hc08_bits *)(&PTC))->bit2
#define PTC3 ((struct __hc08_bits *)(&PTC))->bit3
#define PTC4 ((struct __hc08_bits *)(&PTC))->bit4
#define PTC5 ((struct __hc08_bits *)(&PTC))->bit5
#define PTC6 ((struct __hc08_bits *)(&PTC))->bit6
#define PTC7 ((struct __hc08_bits *)(&PTC))->bit7
_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
#define PORTD PTD /* Alias for PTD */
#define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
#define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
#define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
#define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
#define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
#define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
#define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
#define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
#define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
#define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
#define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
#define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
#define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
#define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
#define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
#define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
#define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
#define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
#define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
#define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
#define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
#define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
#define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
#define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
_VOLDATA _UINT8 __at 0x06 DDRC; /* Data Direction Register C */
#define DDRC0 ((struct __hc08_bits *)(&DDRC))->bit0
#define DDRC1 ((struct __hc08_bits *)(&DDRC))->bit1
#define DDRC2 ((struct __hc08_bits *)(&DDRC))->bit2
#define DDRC3 ((struct __hc08_bits *)(&DDRC))->bit3
#define DDRC4 ((struct __hc08_bits *)(&DDRC))->bit4
#define DDRC5 ((struct __hc08_bits *)(&DDRC))->bit5
#define DDRC6 ((struct __hc08_bits *)(&DDRC))->bit6
#define DDRC7 ((struct __hc08_bits *)(&DDRC))->bit7
_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
#define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
#define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
#define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
#define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
#define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
#define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
#define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
#define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
_VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */
#define PORTE PTE /* Alias for PTE */
#define PTE0 ((struct __hc08_bits *)(&PTE))->bit0
#define PTE1 ((struct __hc08_bits *)(&PTE))->bit1
#define PTE2 ((struct __hc08_bits *)(&PTE))->bit2
#define PTE3 ((struct __hc08_bits *)(&PTE))->bit3
#define PTE4 ((struct __hc08_bits *)(&PTE))->bit4
#define PTE5 ((struct __hc08_bits *)(&PTE))->bit5
#define PTE6 ((struct __hc08_bits *)(&PTE))->bit6
#define PTE7 ((struct __hc08_bits *)(&PTE))->bit7
_VOLDATA _UINT8 __at 0x0C DDRE; /* Data Direction Register E */
#define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0
#define DDRE1 ((struct __hc08_bits *)(&DDRE))->bit1
#define DDRE2 ((struct __hc08_bits *)(&DDRE))->bit2
#define DDRE3 ((struct __hc08_bits *)(&DDRE))->bit3
#define DDRE4 ((struct __hc08_bits *)(&DDRE))->bit4
#define DDRE5 ((struct __hc08_bits *)(&DDRE))->bit5
#define DDRE6 ((struct __hc08_bits *)(&DDRE))->bit6
#define DDRE7 ((struct __hc08_bits *)(&DDRE))->bit7
_VOLDATA _UINT8 __at 0x0D PTAPUE; /* Port A pull-up enables */
#define PTAPUE0 ((struct __hc08_bits *)(&PTAPUE))->bit0
#define PTAPUE1 ((struct __hc08_bits *)(&PTAPUE))->bit1
#define PTAPUE2 ((struct __hc08_bits *)(&PTAPUE))->bit2
#define PTAPUE3 ((struct __hc08_bits *)(&PTAPUE))->bit3
#define PTAPUE4 ((struct __hc08_bits *)(&PTAPUE))->bit4
#define PTAPUE5 ((struct __hc08_bits *)(&PTAPUE))->bit5
#define PTAPUE6 ((struct __hc08_bits *)(&PTAPUE))->bit6
#define PTAPUE7 ((struct __hc08_bits *)(&PTAPUE))->bit7
_VOLDATA _UINT8 __at 0x0E PTCPUE; /* Port C pull-up enables */
#define PTCPUE0 ((struct __hc08_bits *)(&PTCPUE))->bit0
#define PTCPUE1 ((struct __hc08_bits *)(&PTCPUE))->bit1
#define PTCPUE2 ((struct __hc08_bits *)(&PTCPUE))->bit2
#define PTCPUE3 ((struct __hc08_bits *)(&PTCPUE))->bit3
#define PTCPUE4 ((struct __hc08_bits *)(&PTCPUE))->bit4
#define PTCPUE5 ((struct __hc08_bits *)(&PTCPUE))->bit5
#define PTCPUE6 ((struct __hc08_bits *)(&PTCPUE))->bit6
/* PTCPUE7 does not exit! */
_VOLDATA _UINT8 __at 0x0F PTDPUE; /* port D pull-up enables */
#define PTDPUE0 ((struct __hc08_bits *)(&PTDPUE))->bit0
#define PTDPUE1 ((struct __hc08_bits *)(&PTDPUE))->bit1
#define PTDPUE2 ((struct __hc08_bits *)(&PTDPUE))->bit2
#define PTDPUE3 ((struct __hc08_bits *)(&PTDPUE))->bit3
#define PTDPUE4 ((struct __hc08_bits *)(&PTDPUE))->bit4
#define PTDPUE5 ((struct __hc08_bits *)(&PTDPUE))->bit5
#define PTDPUE6 ((struct __hc08_bits *)(&PTDPUE))->bit6
#define PTDPUE7 ((struct __hc08_bits *)(&PTDPUE))->bit7
_VOLDATA _UINT8 __at 0x10 SPCR; /* SPI Control Register */
#define SPRIE ((struct __hc08_bits *)(&SPCR))->bit7
#define DMAS ((struct __hc08_bits *)(&SPCR))->bit6
#define SPMSTR ((struct __hc08_bits *)(&SPCR))->bit5
#define CPOL ((struct __hc08_bits *)(&SPCR))->bit4
#define CPHA ((struct __hc08_bits *)(&SPCR))->bit3
#define SPWOM ((struct __hc08_bits *)(&SPCR))->bit2
#define SPE ((struct __hc08_bits *)(&SPCR))->bit1
#define SPTIE ((struct __hc08_bits *)(&SPCR))->bit0
_VOLDATA _UINT8 __at 0x11 SPSCR; /* SPI Status and Control Register */
#define SPRF ((struct __hc08_bits *)(&SPSCR))->bit7
#define ERRIE ((struct __hc08_bits *)(&SPSCR))->bit6
#define OVRF ((struct __hc08_bits *)(&SPSCR))->bit5
#define MODF ((struct __hc08_bits *)(&SPSCR))->bit4
#define SPTE ((struct __hc08_bits *)(&SPSCR))->bit3
#define MODFEN ((struct __hc08_bits *)(&SPSCR))->bit2
#define SPR1 ((struct __hc08_bits *)(&SPSCR))->bit1
#define SPR0 ((struct __hc08_bits *)(&SPSCR))->bit0
_VOLDATA _UINT8 __at 0x12 SPDR; /* SPI Data Register */
_VOLDATA _UINT8 __at 0x13 SCC1; /* SCI Control Register 1 */
#define LOOPS ((struct __hc08_bits *)(&SCC1))->bit7
#define ENSCI ((struct __hc08_bits *)(&SCC1))->bit6
#define TXINV ((struct __hc08_bits *)(&SCC1))->bit5
#define M ((struct __hc08_bits *)(&SCC1))->bit4
#define WAKE ((struct __hc08_bits *)(&SCC1))->bit3
#define ILTY ((struct __hc08_bits *)(&SCC1))->bit2
#define PEN ((struct __hc08_bits *)(&SCC1))->bit1
#define PTY ((struct __hc08_bits *)(&SCC1))->bit0
_VOLDATA _UINT8 __at 0x14 SCC2; /* SCI Control Register 2 */
#define SCTIE ((struct __hc08_bits *)(&SCC2))->bit7
#define TCIE ((struct __hc08_bits *)(&SCC2))->bit6
#define SCRIE ((struct __hc08_bits *)(&SCC2))->bit5
#define ILIE ((struct __hc08_bits *)(&SCC2))->bit4
#define TE ((struct __hc08_bits *)(&SCC2))->bit3
#define RE ((struct __hc08_bits *)(&SCC2))->bit2
#define WRU ((struct __hc08_bits *)(&SCC2))->bit1
#define SBK ((struct __hc08_bits *)(&SCC2))->bit0
_VOLDATA _UINT8 __at 0x15 SCC3; /* SCI Control Register 3 */
#define SCC3_R8 ((struct __hc08_bits *)(&SCC3))->bit7
#define SCC3_TB ((struct __hc08_bits *)(&SCC3))->bit6
#define DMARE ((struct __hc08_bits *)(&SCC3))->bit5
#define DMATE ((struct __hc08_bits *)(&SCC3))->bit4
#define ORIE ((struct __hc08_bits *)(&SCC3))->bit3
#define NEIE ((struct __hc08_bits *)(&SCC3))->bit2
#define FEIE ((struct __hc08_bits *)(&SCC3))->bit1
#define PEIE ((struct __hc08_bits *)(&SCC3))->bit0
_VOLDATA _UINT8 __at 0x16 SCS1; /* SCI Status Register 1 */
#define SCTE ((struct __hc08_bits *)(&SCS1))->bit7
#define TC ((struct __hc08_bits *)(&SCS1))->bit6
#define SCRF ((struct __hc08_bits *)(&SCS1))->bit5
#define IDLE ((struct __hc08_bits *)(&SCS1))->bit4
#define OR ((struct __hc08_bits *)(&SCS1))->bit3
#define NF ((struct __hc08_bits *)(&SCS1))->bit2
#define FE ((struct __hc08_bits *)(&SCS1))->bit1
#define PE ((struct __hc08_bits *)(&SCS1))->bit0
_VOLDATA _UINT8 __at 0x17 SCS2; /* SCI Status Register 2 */
#define RPF ((struct __hc08_bits *)(&SCS2))->bit0
#define BKF ((struct __hc08_bits *)(&SCS2))->bit1
/* Bits 2-7 not implemented */
_VOLDATA _UINT8 __at 0x18 SCDR; /* SCI Data Register */
_VOLDATA _UINT8 __at 0x19 SCBR; /* SCI Baud Rate Register */
#define SCP1 ((struct __hc08_bits *)(&SCBR))->bit5
#define SCP0 ((struct __hc08_bits *)(&SCBR))->bit4
#define R ((struct __hc08_bits *)(&SCBR))->bit3
#define SCR2 ((struct __hc08_bits *)(&SCBR))->bit2
#define SCR1 ((struct __hc08_bits *)(&SCBR))->bit1
#define SCR0 ((struct __hc08_bits *)(&SCBR))->bit0
/*-- Bits 6 and 7 do not exist */
_VOLDATA _UINT8 __at 0x1a INTKBSCR; /* Keyboard Status and Control Register */
#define KEYF ((struct __hc08_bits *)(&INTKBSCR))->bit3
#define ACKK ((struct __hc08_bits *)(&INTKBSCR))->bit2
#define IMASKK ((struct __hc08_bits *)(&INTKBSCR))->bit1
#define MODEK ((struct __hc08_bits *)(&INTKBSCR))->bit0
/*-- Bits 4-7 do not exist */
_VOLDATA _UINT8 __at 0x1b INTKBIER; /* Keyboard Interrupt Enable Register */
#define KBIE7 ((struct __hc08_bits *)(&INTKBIER))->bit7
#define KBIE6 ((struct __hc08_bits *)(&INTKBIER))->bit6
#define KBIE5 ((struct __hc08_bits *)(&INTKBIER))->bit5
#define KBIE4 ((struct __hc08_bits *)(&INTKBIER))->bit4
#define KBIE3 ((struct __hc08_bits *)(&INTKBIER))->bit3
#define KBIE2 ((struct __hc08_bits *)(&INTKBIER))->bit2
#define KBIE1 ((struct __hc08_bits *)(&INTKBIER))->bit1
#define KBIE0 ((struct __hc08_bits *)(&INTKBIER))->bit0
_VOLDATA _UINT8 __at 0x1C TBCR; /* Time Base Module Control */
#define TBIF ((struct __hc08_bits *)(&TBCR))->bit7
#define TBR2 ((struct __hc08_bits *)(&TBCR))->bit6
#define TBR1 ((struct __hc08_bits *)(&TBCR))->bit5
#define TBR0 ((struct __hc08_bits *)(&TBCR))->bit4
#define TACK ((struct __hc08_bits *)(&TBCR))->bit3
#define TBIE ((struct __hc08_bits *)(&TBCR))->bit2
#define TBON ((struct __hc08_bits *)(&TBCR))->bit1
/* Bit 0 Reserved */
_VOLDATA _UINT8 __at 0x1D INTSCR; /* IRQ status/control */
#define IRQF1 ((struct __hc08_bits *)(&INTSCR))->bit3
#define ACK1 ((struct __hc08_bits *)(&INTSCR))->bit2
#define IMASK1 ((struct __hc08_bits *)(&INTSCR))->bit1
#define MODE1 ((struct __hc08_bits *)(&INTSCR))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x1e CONFIG2; /* Configuration Register 2 */
/* CONFIG2 is one-time writeble, so can't use bitfields */
_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
/* CONFIG1 is one-time writeable, so can't use bitfields */
_VOLDATA _UINT8 __at 0x20 T1SC; /* TIM 1 Status and Control */
#define PS0 ((struct __hc08_bits *)(&T1SC))->bit0
#define PS1 ((struct __hc08_bits *)(&T1SC))->bit1
#define PS2 ((struct __hc08_bits *)(&T1SC))->bit2
#define TRST ((struct __hc08_bits *)(&T1SC))->bit4
#define TSTOP ((struct __hc08_bits *)(&T1SC))->bit5
#define TOIE ((struct __hc08_bits *)(&T1SC))->bit6
#define TOF ((struct __hc08_bits *)(&T1SC))->bit7
_VOLDATA _UINT16 __at 0x21 T1CNT; /* TIM1 Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x21 T1CNTH; /* TIM1 Counter Register High */
_VOLDATA _UINT8 __at 0x22 T1CNTL; /* TIM1 Counter Register Low */
_VOLDATA _UINT16 __at 0x23 T1MOD; /* TIM1 Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x23 T1MODH; /* TIM1 Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x24 T1MODL; /* TIM1 Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x25 T1SC0; /* TIM1 Channel 0 Status and Control Register */
#define CH0MAX ((struct __hc08_bits *)(&T1SC0))->bit0
#define TOV0 ((struct __hc08_bits *)(&T1SC0))->bit1
#define ELS0A ((struct __hc08_bits *)(&T1SC0))->bit2
#define ELS0B ((struct __hc08_bits *)(&T1SC0))->bit3
#define MS0A ((struct __hc08_bits *)(&T1SC0))->bit4
#define MS0B ((struct __hc08_bits *)(&T1SC0))->bit5
#define CH0IE ((struct __hc08_bits *)(&T1SC0))->bit6
#define CH0F ((struct __hc08_bits *)(&T1SC0))->bit7
_VOLDATA _UINT16 __at 0x26 T1CH0; /* TIM1 Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x26 T1CH0H; /* TIM1 Channel 0 Register High */
_VOLDATA _UINT8 __at 0x27 T1CH0L; /* TIM1 Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x28 T1SC1; /* TIM1 Channel 1 Status and Control Register */
#define CH1MAX ((struct __hc08_bits *)(&T1SC1))->bit0
#define TOV1 ((struct __hc08_bits *)(&T1SC1))->bit1
#define ELS1A ((struct __hc08_bits *)(&T1SC1))->bit2
#define ELS1B ((struct __hc08_bits *)(&T1SC1))->bit3
#define MS1A ((struct __hc08_bits *)(&T1SC1))->bit4
#define CH1IE ((struct __hc08_bits *)(&T1SC1))->bit6
#define CH1F ((struct __hc08_bits *)(&T1SC1))->bit7
_VOLDATA _UINT16 __at 0x29 T1CH1; /* TIM1 Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x29 T1CH1H; /* TIM1 Channel 1 Register High */
_VOLDATA _UINT8 __at 0x2A T1CH1L; /* TIM1 Channel 1 Register Low */
/*------------------*/
/* TIM 2 REGISTERS */
/*------------------*/
_VOLDATA _UINT8 __at 0x2B T2SC; /* TIM 2 Status and Control */
#define PS0_2 ((struct __hc08_bits *)(&T2SC))->bit0
#define PS1_2 ((struct __hc08_bits *)(&T2SC))->bit1
#define PS2_2 ((struct __hc08_bits *)(&T2SC))->bit2
#define TRST_2 ((struct __hc08_bits *)(&T2SC))->bit4
#define TSTOP_2 ((struct __hc08_bits *)(&T2SC))->bit5
#define TOIE_2 ((struct __hc08_bits *)(&T2SC))->bit6
#define TOF_2 ((struct __hc08_bits *)(&T2SC))->bit7
_VOLDATA _UINT16 __at 0x2C T2CNT; /* TIM2 Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x2C T2CNTH; /* TIM2 Counter Register High */
_VOLDATA _UINT8 __at 0x2D T2CNTL; /* TIM2 Counter Register Low */
_VOLDATA _UINT16 __at 0x2E T2MOD; /* TIM2 Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x2E T2MODH; /* TIM2 Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x2F T2MODL; /* TIM2 Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x30 T2SC0; /* TIM2 Channel 0 Status and Control Register */
#define CH0MAX_2 ((struct __hc08_bits *)(&T2SC0))->bit0
#define TOV0_2 ((struct __hc08_bits *)(&T2SC0))->bit1
#define ELS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit2
#define ELS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit3
#define MS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit4
#define MS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit5
#define CH0IE_2 ((struct __hc08_bits *)(&T2SC0))->bit6
#define CH0F_2 ((struct __hc08_bits *)(&T2SC0))->bit7
_VOLDATA _UINT16 __at 0x31 T2CH0; /* TIM2 Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x31 T2CH0H; /* TIM2 Channel 0 Register High */
_VOLDATA _UINT8 __at 0x32 T2CH0L; /* TIM2 Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x33 T2SC1; /* TIM2 Channel 1 Status and Control Register */
#define CH1MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0
#define TOV1_2 ((struct __hc08_bits *)(&T2SC1))->bit1
#define ELS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit2
#define ELS1B_2 ((struct __hc08_bits *)(&T2SC1))->bit3
#define MS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit4
#define CH1IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6
#define CH1F_2 ((struct __hc08_bits *)(&T2SC1))->bit7
_VOLDATA _UINT16 __at 0x34 T2CH1; /* TIM2 Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x34 T2CH1H; /* TIM2 Channel 1 Register High */
_VOLDATA _UINT8 __at 0x35 T2CH1L; /* TIM2 Channel 1 Register Low */
_VOLDATA _UINT8 __at 0x36 PCTL; /* PLL Control Register */
#define PLLIE ((struct __hc08_bits *)(&PCTL))->bit7
#define PLLF ((struct __hc08_bits *)(&PCTL))->bit6
#define PLLON ((struct __hc08_bits *)(&PCTL))->bit5
#define BCS ((struct __hc08_bits *)(&PCTL))->bit4
#define PRE1 ((struct __hc08_bits *)(&PCTL))->bit3
#define PRE0 ((struct __hc08_bits *)(&PCTL))->bit2
#define VPR1 ((struct __hc08_bits *)(&PCTL))->bit1
#define VPR0 ((struct __hc08_bits *)(&PCTL))->bit0
_VOLDATA _UINT8 __at 0x37 PBWC; /* PLL Bandwidth Control Register */
#define AUTO ((struct __hc08_bits *)(&PBWC))->bit7
#define LOCK ((struct __hc08_bits *)(&PBWC))->bit6
#define ACQ ((struct __hc08_bits *)(&PBWC))->bit5
/* Bits 1-4, Unimplemented */
/* Bit 0, Reserved */
_VOLDATA _UINT8 __at 0x38 PMSH; /* PLL Multiplier Select High */
#define MUL11 ((struct __hc08_bits *)(&PMSH))->bit3
#define MUL10 ((struct __hc08_bits *)(&PMSH))->bit2
#define MUL9 ((struct __hc08_bits *)(&PMSH))->bit1
#define MUL8 ((struct __hc08_bits *)(&PMSH))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x39 PMSL; /* PLL Multiplir Select Low */
#define MUL7 ((struct __hc08_bits *)(&PMSL))->bit7
#define MUL6 ((struct __hc08_bits *)(&PMSL))->bit6
#define MUL5 ((struct __hc08_bits *)(&PMSL))->bit5
#define MUL4 ((struct __hc08_bits *)(&PMSL))->bit4
#define MUL3 ((struct __hc08_bits *)(&PMSL))->bit3
#define MUL2 ((struct __hc08_bits *)(&PMSL))->bit2
#define MUL1 ((struct __hc08_bits *)(&PMSL))->bit1
#define MUL0 ((struct __hc08_bits *)(&PMSL))->bit0
_VOLDATA _UINT8 __at 0x3a PMRS; /* PLL VCO Select Range */
#define VRS7 ((struct __hc08_bits *)(&PMRS))->bit7
#define VRS6 ((struct __hc08_bits *)(&PMRS))->bit6
#define VRS5 ((struct __hc08_bits *)(&PMRS))->bit5
#define VRS4 ((struct __hc08_bits *)(&PMRS))->bit4
#define VRS3 ((struct __hc08_bits *)(&PMRS))->bit3
#define VRS2 ((struct __hc08_bits *)(&PMRS))->bit2
#define VRS1 ((struct __hc08_bits *)(&PMRS))->bit1
#define VRS0 ((struct __hc08_bits *)(&PMRS))->bit0
_VOLDATA _UINT8 __at 0x3b PMDS; /* PLL Reference Divider Select Register */
#define RDS3 ((struct __hc08_bits *)(&PMDS))->bit3
#define RDS2 ((struct __hc08_bits *)(&PMDS))->bit2
#define RDS1 ((struct __hc08_bits *)(&PMDS))->bit1
#define RDS0 ((struct __hc08_bits *)(&PMDS))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x3c ADSCR; /* Analog-to-Digital Status and Control Reg. */
#define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
#define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
#define ADCO ((struct __hc08_bits *)(&ADSCR))->bit5
#define ADCH4 ((struct __hc08_bits *)(&ADSCR))->bit4
#define ADCH3 ((struct __hc08_bits *)(&ADSCR))->bit3
#define ADCH2 ((struct __hc08_bits *)(&ADSCR))->bit2
#define ADCH1 ((struct __hc08_bits *)(&ADSCR))->bit1
#define ADCH0 ((struct __hc08_bits *)(&ADSCR))->bit0
_VOLDATA _UINT8 __at 0x3d ADR; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x3e ADCLK; /* Analog-to-Digital Clock */
#define ADIV2 ((struct __hc08_bits *)(&ADCLK))->bit7
#define ADIV1 ((struct __hc08_bits *)(&ADCLK))->bit6
#define ADIV0 ((struct __hc08_bits *)(&ADCLK))->bit5
#define ADICLK ((struct __hc08_bits *)(&ADCLK))->bit4
/* Bits 0-3 unimplemented */
_VOLXDATA _UINT8 __at 0xfe00 SBSR; /* SIM Break Status Register */
#define SBSW ((struct __hc08_bits *)(&SBSR))->bit1
_VOLXDATA _UINT8 __at 0xfe01 SRSR; /* SIM Reset Status Register */
#define LVI ((struct __hc08_bits *)(&SRSR))->bit1
#define MODRST ((struct __hc08_bits *)(&SRSR))->bit2
#define ILAD ((struct __hc08_bits *)(&SRSR))->bit3
#define ILOP ((struct __hc08_bits *)(&SRSR))->bit4
#define COP ((struct __hc08_bits *)(&SRSR))->bit5
#define PIN ((struct __hc08_bits *)(&SRSR))->bit6
#define POR ((struct __hc08_bits *)(&SRSR))->bit7
/* Bit 0 unimplemented */
_VOLXDATA _UINT8 __at 0xfe02 SUBAR; /* SIM Upper Byte Address */
_VOLXDATA _UINT8 __at 0xfe03 SBFCR; /* SIM Break Flag Control Register */
#define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
#define IF1 ((struct __hc08_bits *)(&INT1))->bit2
#define IF2 ((struct __hc08_bits *)(&INT1))->bit3
#define IF3 ((struct __hc08_bits *)(&INT1))->bit4
#define IF4 ((struct __hc08_bits *)(&INT1))->bit5
#define IF5 ((struct __hc08_bits *)(&INT1))->bit6
#define IF6 ((struct __hc08_bits *)(&INT1))->bit7
/* Bits 0-1 Reserved */
_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
#define IF14 ((struct __hc08_bits *)(&INT2))->bit7
#define IF13 ((struct __hc08_bits *)(&INT2))->bit6
#define IF12 ((struct __hc08_bits *)(&INT2))->bit5
#define IF11 ((struct __hc08_bits *)(&INT2))->bit4
#define IF10 ((struct __hc08_bits *)(&INT2))->bit3
#define IF9 ((struct __hc08_bits *)(&INT2))->bit2
#define IF8 ((struct __hc08_bits *)(&INT2))->bit1
#define IF7 ((struct __hc08_bits *)(&INT2))->bit0
_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
#define IF16 ((struct __hc08_bits *)(&INT3))->bit1
#define IF15 ((struct __hc08_bits *)(&INT3))->bit0
_VOLXDATA _UINT8 __at 0xfe07 FLCTR; /* Flash test/programming */
_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
#define PGM ((struct __hc08_bits *)(&FLCR))->bit0
#define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
#define MASS ((struct __hc08_bits *)(&FLCR))->bit2
#define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
_VOLXDATA _UINT16 __at 0xfe09 BRK; /* Break Address High & Low Registers */
_VOLXDATA _UINT8 __at 0xfe09 BRKH; /* Break Address High Register */
_VOLXDATA _UINT8 __at 0xfe0a BRKL; /* Break Address Low Register */
_VOLXDATA _UINT8 __at 0xfe0b BRKSCR; /* Break Status and Control Register */
#define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
#define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
_VOLXDATA _UINT8 __at 0xfe0c LVISR; /* Low voltage detect */
#define LVIOUT ((struct __hc08_bits *)(&LVISR))->bit7
_VOLXDATA _UINT8 __at 0xfe7e FLBPR; /* FLASH Block Protect Register */
#define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
#define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
#define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
#define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
#define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
#define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
#define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
#define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
#endif

414
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/hc08/mc68hc908jb8.h Normal file
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@@ -0,0 +1,414 @@
/*-------------------------------------------------------------------------
mc68hc908jb8.h - Register Declarations for Motorola MC68HC908JB8
Copyright (C) 2004, Bjorn Bringert <bjorn@bringert.net>
Based on mc68hc908qy.h,
written By - Erik Petrich epetrich@users.sourceforge.net (2003)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef _MC68HC908JB8_H
#define _MC68HC908JB8_H
#ifndef _UINT8
#define _UINT8 unsigned char
#endif
#ifndef _UINT16
#define _UINT16 unsigned int
#endif
#ifndef _VOLDATA
#define _VOLDATA volatile __data
#endif
#ifndef _VOLXDATA
#define _VOLXDATA volatile __xdata
#endif
struct __hc08_bits
{
unsigned int bit0:1;
unsigned int bit1:1;
unsigned int bit2:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
};
_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
#define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
#define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
#define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
#define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
#define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
#define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
#define PTA6 ((struct __hc08_bits *)(&PTA))->bit6
#define PTA7 ((struct __hc08_bits *)(&PTA))->bit7
_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
#define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
#define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
#define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
#define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
#define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
#define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
#define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
#define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
_VOLDATA _UINT8 __at 0x02 PTC; /* Port C Data Register */
#define PTC0 ((struct __hc08_bits *)(&PTC))->bit0
#define PTC1 ((struct __hc08_bits *)(&PTC))->bit1
#define PTC2 ((struct __hc08_bits *)(&PTC))->bit2
#define PTC3 ((struct __hc08_bits *)(&PTC))->bit3
#define PTC4 ((struct __hc08_bits *)(&PTC))->bit4
#define PTC5 ((struct __hc08_bits *)(&PTC))->bit5
#define PTC6 ((struct __hc08_bits *)(&PTC))->bit6
#define PTC7 ((struct __hc08_bits *)(&PTC))->bit7
_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
#define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
#define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
#define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
#define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
#define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
#define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
#define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
#define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
#define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
#define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
#define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
#define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
#define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
#define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
#define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
#define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
#define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
#define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
#define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
#define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
#define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
#define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
#define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
#define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
_VOLDATA _UINT8 __at 0x06 DDRC; /* Data Direction Register C */
#define DDRC0 ((struct __hc08_bits *)(&DDRC))->bit0
#define DDRC1 ((struct __hc08_bits *)(&DDRC))->bit1
#define DDRC2 ((struct __hc08_bits *)(&DDRC))->bit2
#define DDRC3 ((struct __hc08_bits *)(&DDRC))->bit3
#define DDRC4 ((struct __hc08_bits *)(&DDRC))->bit4
#define DDRC5 ((struct __hc08_bits *)(&DDRC))->bit5
#define DDRC6 ((struct __hc08_bits *)(&DDRC))->bit6
#define DDRC7 ((struct __hc08_bits *)(&DDRC))->bit7
_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
#define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
#define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
#define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
#define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
#define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
#define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
#define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
#define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
_VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */
#define PTE0 ((struct __hc08_bits *)(&PTE))->bit0
#define PTE1 ((struct __hc08_bits *)(&PTE))->bit1
#define PTE2 ((struct __hc08_bits *)(&PTE))->bit2
#define PTE3 ((struct __hc08_bits *)(&PTE))->bit3
#define PTE4 ((struct __hc08_bits *)(&PTE))->bit4
#define PTE5 ((struct __hc08_bits *)(&PTE))->bit5
#define PTE6 ((struct __hc08_bits *)(&PTE))->bit6
#define PTE7 ((struct __hc08_bits *)(&PTE))->bit7
_VOLDATA _UINT8 __at 0x09 DDRE; /* Data Direction Register E */
#define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0
#define DDRE1 ((struct __hc08_bits *)(&DDRE))->bit1
#define DDRE2 ((struct __hc08_bits *)(&DDRE))->bit2
#define DDRE3 ((struct __hc08_bits *)(&DDRE))->bit3
#define DDRE4 ((struct __hc08_bits *)(&DDRE))->bit4
#define DDRE5 ((struct __hc08_bits *)(&DDRE))->bit5
#define DDRE6 ((struct __hc08_bits *)(&DDRE))->bit6
#define DDRE7 ((struct __hc08_bits *)(&DDRE))->bit7
_VOLDATA _UINT8 __at 0x0a TSC; /* TIM Status and Control */
#define PS0 ((struct __hc08_bits *)(&TSC))->bit0
#define PS1 ((struct __hc08_bits *)(&TSC))->bit1
#define PS2 ((struct __hc08_bits *)(&TSC))->bit2
#define TRST ((struct __hc08_bits *)(&TSC))->bit4
#define TSTOP ((struct __hc08_bits *)(&TSC))->bit5
#define TOIE ((struct __hc08_bits *)(&TSC))->bit6
#define TOF ((struct __hc08_bits *)(&TSC))->bit7
_VOLDATA _UINT16 __at 0x0c TCNT; /* TIM Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x0c TCNTH; /* TIM Counter Register High */
_VOLDATA _UINT8 __at 0x0d TCNTL; /* TIM Counter Register Low */
_VOLDATA _UINT16 __at 0x0e TMOD; /* TIM Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x0e TMODH; /* TIM Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x0f TMODL; /* TIM Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x10 TSC0; /* TIM Channel 0 Status and Control Register */
#define CH0MAX ((struct __hc08_bits *)(&TSC0))->bit0
#define TOV0 ((struct __hc08_bits *)(&TSC0))->bit1
#define ELS0A ((struct __hc08_bits *)(&TSC0))->bit2
#define ELS0B ((struct __hc08_bits *)(&TSC0))->bit3
#define MS0A ((struct __hc08_bits *)(&TSC0))->bit4
#define MS0B ((struct __hc08_bits *)(&TSC0))->bit5
#define CH0IE ((struct __hc08_bits *)(&TSC0))->bit6
#define CH0F ((struct __hc08_bits *)(&TSC0))->bit7
_VOLDATA _UINT16 __at 0x11 TCH0; /* TIM Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x11 TCH0H; /* TIM Channel 0 Register High */
_VOLDATA _UINT8 __at 0x12 TCH0L; /* TIM Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x13 TSC1; /* TIM Channel 1 Status and Control Register */
#define CH1MAX ((struct __hc08_bits *)(&TSC1))->bit0
#define TOV1 ((struct __hc08_bits *)(&TSC1))->bit1
#define ELS1A ((struct __hc08_bits *)(&TSC1))->bit2
#define ELS1B ((struct __hc08_bits *)(&TSC1))->bit3
#define MS1A ((struct __hc08_bits *)(&TSC1))->bit4
#define CH1IE ((struct __hc08_bits *)(&TSC1))->bit6
#define CH1F ((struct __hc08_bits *)(&TSC1))->bit7
_VOLDATA _UINT16 __at 0x14 TCH1; /* TIM Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x14 TCH1H; /* TIM Channel 1 Register High */
_VOLDATA _UINT8 __at 0x15 TCH1L; /* TIM Channel 1 Register Low */
_VOLDATA _UINT8 __at 0x16 KBSCR; /* Keyboard Status and Control Register */
#define MODEK ((struct __hc08_bits *)(&KBSCR))->bit0
#define IMASKK ((struct __hc08_bits *)(&KBSCR))->bit1
#define ACKK ((struct __hc08_bits *)(&KBSCR))->bit2
#define KEYF ((struct __hc08_bits *)(&KBSCR))->bit3
_VOLDATA _UINT8 __at 0x17 KBIER; /* Keyboard Interrupt Enable Register */
#define KBIE0 ((struct __hc08_bits *)(&KBIER))->bit0
#define KBIE1 ((struct __hc08_bits *)(&KBIER))->bit1
#define KBIE2 ((struct __hc08_bits *)(&KBIER))->bit2
#define KBIE3 ((struct __hc08_bits *)(&KBIER))->bit3
#define KBIE4 ((struct __hc08_bits *)(&KBIER))->bit4
#define KBIE5 ((struct __hc08_bits *)(&KBIER))->bit5
#define KBIE6 ((struct __hc08_bits *)(&KBIER))->bit6
#define KBIE7 ((struct __hc08_bits *)(&KBIER))->bit7
_VOLDATA _UINT8 __at 0x18 UIR2; /* USB Interrupt Register 2 */
#define RXD0FR ((struct __hc08_bits *)(&UIR2))->bit0
#define TXD0FR ((struct __hc08_bits *)(&UIR2))->bit1
#define RESUMFR ((struct __hc08_bits *)(&UIR2))->bit2
#define TXD1FR ((struct __hc08_bits *)(&UIR2))->bit3
#define RXD2FR ((struct __hc08_bits *)(&UIR2))->bit4
#define TXD2FR ((struct __hc08_bits *)(&UIR2))->bit5
#define RSTFR ((struct __hc08_bits *)(&UIR2))->bit6
#define EOPFR ((struct __hc08_bits *)(&UIR2))->bit7
_VOLDATA _UINT8 __at 0x19 UCR2; /* USB Control Register 2 */
#define TP2SIZ0 ((struct __hc08_bits *)(&UCR2))->bit0
#define TP2SIZ1 ((struct __hc08_bits *)(&UCR2))->bit1
#define TP2SIZ2 ((struct __hc08_bits *)(&UCR2))->bit2
#define TP2SIZ3 ((struct __hc08_bits *)(&UCR2))->bit3
#define RX2E ((struct __hc08_bits *)(&UCR2))->bit4
#define TX2E ((struct __hc08_bits *)(&UCR2))->bit5
#define STALL2 ((struct __hc08_bits *)(&UCR2))->bit6
#define T2SEQ ((struct __hc08_bits *)(&UCR2))->bit7
_VOLDATA _UINT8 __at 0x1a UCR3; /* USB Control Register 3 */
#define ENABLE1 ((struct __hc08_bits *)(&UCR3))->bit0
#define ENABLE2 ((struct __hc08_bits *)(&UCR3))->bit1
#define PULLEN ((struct __hc08_bits *)(&UCR3))->bit2
#define ISTALL0 ((struct __hc08_bits *)(&UCR3))->bit4
#define OSTALL0 ((struct __hc08_bits *)(&UCR3))->bit5
#define TX1STR ((struct __hc08_bits *)(&UCR3))->bit6
#define TX1ST ((struct __hc08_bits *)(&UCR3))->bit7
_VOLDATA _UINT8 __at 0x1b UCR4; /* USB Control Register 4 */
#define FDM ((struct __hc08_bits *)(&UCR4))->bit0
#define FDP ((struct __hc08_bits *)(&UCR4))->bit1
#define FUSB0 ((struct __hc08_bits *)(&UCR4))->bit2
_VOLDATA _UINT8 __at 0x1c IOCR; /* IRQ Option Control Register */
#define IRQPD ((struct __hc08_bits *)(&IOCR))->bit0
#define PTE4IE ((struct __hc08_bits *)(&IOCR))->bit1
#define PTE4IF ((struct __hc08_bits *)(&IOCR))->bit2
_VOLDATA _UINT8 __at 0x1d POCR; /* Port Option Control Register */
#define PAP ((struct __hc08_bits *)(&POCR))->bit0
#define PBP ((struct __hc08_bits *)(&POCR))->bit1
#define PCP ((struct __hc08_bits *)(&POCR))->bit2
#define PTE3P ((struct __hc08_bits *)(&POCR))->bit3
#define PTE4P ((struct __hc08_bits *)(&POCR))->bit4
#define PTDILDD ((struct __hc08_bits *)(&POCR))->bit5
#define PTDLDD ((struct __hc08_bits *)(&POCR))->bit6
#define PTE20P ((struct __hc08_bits *)(&POCR))->bit7
_VOLDATA _UINT8 __at 0x1e ISCR; /* IRQ Status and Control Register */
#define MODE ((struct __hc08_bits *)(&ISCR))->bit0
#define IMASK ((struct __hc08_bits *)(&ISCR))->bit1
#define ACK ((struct __hc08_bits *)(&ISCR))->bit2
#define IRQF ((struct __hc08_bits *)(&ISCR))->bit3
_VOLDATA _UINT8 __at 0x1f CONFIG; /* Configuration Register 1 */
/* CONFIG1 is one-time writeable, so can't use bitfields */
_VOLDATA _UINT8 __at 0x20 UE0D0; /* USB Endpoint 0 Data Register 0 */
_VOLDATA _UINT8 __at 0x21 UE0D1; /* USB Endpoint 0 Data Register 1 */
_VOLDATA _UINT8 __at 0x22 UE0D2; /* USB Endpoint 0 Data Register 2 */
_VOLDATA _UINT8 __at 0x23 UE0D3; /* USB Endpoint 0 Data Register 3 */
_VOLDATA _UINT8 __at 0x24 UE0D4; /* USB Endpoint 0 Data Register 4 */
_VOLDATA _UINT8 __at 0x25 UE0D5; /* USB Endpoint 0 Data Register 5 */
_VOLDATA _UINT8 __at 0x26 UE0D6; /* USB Endpoint 0 Data Register 6 */
_VOLDATA _UINT8 __at 0x27 UE0D7; /* USB Endpoint 0 Data Register 7 */
_VOLDATA _UINT8 __at 0x28 UE1D0; /* USB Endpoint 1 Data Register 0 */
_VOLDATA _UINT8 __at 0x29 UE1D1; /* USB Endpoint 1 Data Register 1 */
_VOLDATA _UINT8 __at 0x2a UE1D2; /* USB Endpoint 1 Data Register 2 */
_VOLDATA _UINT8 __at 0x2b UE1D3; /* USB Endpoint 1 Data Register 3 */
_VOLDATA _UINT8 __at 0x2c UE1D4; /* USB Endpoint 1 Data Register 4 */
_VOLDATA _UINT8 __at 0x2d UE1D5; /* USB Endpoint 1 Data Register 5 */
_VOLDATA _UINT8 __at 0x2e UE1D6; /* USB Endpoint 1 Data Register 6 */
_VOLDATA _UINT8 __at 0x2f UE1D7; /* USB Endpoint 1 Data Register 7 */
_VOLDATA _UINT8 __at 0x30 UE2D0; /* USB Endpoint 2 Data Register 0 */
_VOLDATA _UINT8 __at 0x31 UE2D1; /* USB Endpoint 2 Data Register 1 */
_VOLDATA _UINT8 __at 0x32 UE2D2; /* USB Endpoint 2 Data Register 2 */
_VOLDATA _UINT8 __at 0x33 UE2D3; /* USB Endpoint 2 Data Register 3 */
_VOLDATA _UINT8 __at 0x34 UE2D4; /* USB Endpoint 2 Data Register 4 */
_VOLDATA _UINT8 __at 0x35 UE2D5; /* USB Endpoint 2 Data Register 5 */
_VOLDATA _UINT8 __at 0x36 UE2D6; /* USB Endpoint 2 Data Register 6 */
_VOLDATA _UINT8 __at 0x37 UE2D7; /* USB Endpoint 2 Data Register 7 */
_VOLDATA _UINT8 __at 0x38 UADDR; /* USB Address Register */
#define USBEN ((struct __hc08_bits *)(&UADDR))->bit7
_VOLDATA _UINT8 __at 0x39 UIR0; /* USB Interrupt Register 0 */
#define RXD0IE ((struct __hc08_bits *)(&UIR0))->bit0
#define TXD0IE ((struct __hc08_bits *)(&UIR0))->bit1
#define TXD1IE ((struct __hc08_bits *)(&UIR0))->bit3
#define RXD2IE ((struct __hc08_bits *)(&UIR0))->bit4
#define TXD2IE ((struct __hc08_bits *)(&UIR0))->bit5
#define SUSPND ((struct __hc08_bits *)(&UIR0))->bit6
#define EOPIE ((struct __hc08_bits *)(&UIR0))->bit7
_VOLDATA _UINT8 __at 0x3a UIR1; /* USB Interrupt Register 1 */
#define RXD0F ((struct __hc08_bits *)(&UIR1))->bit0
#define TXD0F ((struct __hc08_bits *)(&UIR1))->bit1
#define RESUMF ((struct __hc08_bits *)(&UIR1))->bit2
#define TXD1F ((struct __hc08_bits *)(&UIR1))->bit3
#define RXD2F ((struct __hc08_bits *)(&UIR1))->bit4
#define TXD2F ((struct __hc08_bits *)(&UIR1))->bit5
#define RSTF ((struct __hc08_bits *)(&UIR1))->bit6
#define EOPF ((struct __hc08_bits *)(&UIR1))->bit7
_VOLDATA _UINT8 __at 0x3b UCR0; /* USB Control Register 0 */
#define TP0SIZ0 ((struct __hc08_bits *)(&UCR0))->bit0
#define TP0SIZ1 ((struct __hc08_bits *)(&UCR0))->bit1
#define TP0SIZ2 ((struct __hc08_bits *)(&UCR0))->bit2
#define TP0SIZ3 ((struct __hc08_bits *)(&UCR0))->bit3
#define RX0E ((struct __hc08_bits *)(&UCR0))->bit4
#define TX0E ((struct __hc08_bits *)(&UCR0))->bit5
#define T0SEQ ((struct __hc08_bits *)(&UCR0))->bit7
_VOLDATA _UINT8 __at 0x3c UCR1; /* USB Control Register 1 */
#define TP1SIZ0 ((struct __hc08_bits *)(&UCR1))->bit0
#define TP1SIZ1 ((struct __hc08_bits *)(&UCR1))->bit1
#define TP1SIZ2 ((struct __hc08_bits *)(&UCR1))->bit2
#define TP1SIZ3 ((struct __hc08_bits *)(&UCR1))->bit3
#define FRESUM ((struct __hc08_bits *)(&UCR1))->bit4
#define TX1E ((struct __hc08_bits *)(&UCR1))->bit5
#define STALL1 ((struct __hc08_bits *)(&UCR1))->bit6
#define T1SEQ ((struct __hc08_bits *)(&UCR1))->bit7
_VOLDATA _UINT8 __at 0x3d USR0; /* USB Status Register 0 */
#define RP0SIZ0 ((struct __hc08_bits *)(&USR0))->bit0
#define RP0SIZ1 ((struct __hc08_bits *)(&USR0))->bit1
#define RP0SIZ2 ((struct __hc08_bits *)(&USR0))->bit2
#define RP0SIZ3 ((struct __hc08_bits *)(&USR0))->bit3
#define SETUP ((struct __hc08_bits *)(&USR0))->bit6
#define R0SEQ ((struct __hc08_bits *)(&USR0))->bit7
_VOLDATA _UINT8 __at 0x3e USR1; /* USB Status Register 1 */
#define RP2SIZ0 ((struct __hc08_bits *)(&USR1))->bit0
#define RP2SIZ1 ((struct __hc08_bits *)(&USR1))->bit1
#define RP2SIZ2 ((struct __hc08_bits *)(&USR1))->bit2
#define RP2SIZ3 ((struct __hc08_bits *)(&USR1))->bit3
#define TXSTL ((struct __hc08_bits *)(&USR1))->bit4
#define TXNAK ((struct __hc08_bits *)(&USR1))->bit5
#define TXACK ((struct __hc08_bits *)(&USR1))->bit6
#define R2SEQ ((struct __hc08_bits *)(&USR1))->bit7
_VOLXDATA _UINT8 __at 0xfe00 BSR; /* Break Status Register */
#define SBSW ((struct __hc08_bits *)(&BSR))->bit1
_VOLXDATA _UINT8 __at 0xfe01 RSR; /* Reset Status Register */
#define LVI ((struct __hc08_bits *)(&RSR))->bit1
#define USB ((struct __hc08_bits *)(&RSR))->bit2
#define ILAD ((struct __hc08_bits *)(&RSR))->bit3
#define ILOP ((struct __hc08_bits *)(&RSR))->bit4
#define COP ((struct __hc08_bits *)(&RSR))->bit5
#define PIN ((struct __hc08_bits *)(&RSR))->bit6
#define POR ((struct __hc08_bits *)(&RSR))->bit7
_VOLXDATA _UINT8 __at 0xfe03 BFCR; /* Break Flag Control Register */
#define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
#define IF1 ((struct __hc08_bits *)(&INT1))->bit2
#define IF2 ((struct __hc08_bits *)(&INT1))->bit3
#define IF3 ((struct __hc08_bits *)(&INT1))->bit4
#define IF4 ((struct __hc08_bits *)(&INT1))->bit5
#define IF5 ((struct __hc08_bits *)(&INT1))->bit6
#define IF6 ((struct __hc08_bits *)(&INT1))->bit7
_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
#define PGM ((struct __hc08_bits *)(&FLCR))->bit0
#define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
#define MASS ((struct __hc08_bits *)(&FLCR))->bit2
#define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
_VOLXDATA _UINT8 __at 0xfe09 FLBPR; /* FLASH Block Protect Register */
#define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
#define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
#define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
#define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
#define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
#define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
#define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
#define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
_VOLXDATA _UINT16 __at 0xfe0c BRK; /* Break Address High & Low Registers */
_VOLXDATA _UINT8 __at 0xfe0c BRKH; /* Break Address High Register */
_VOLXDATA _UINT8 __at 0xfe0d BRKL; /* Break Address Low Register */
_VOLXDATA _UINT8 __at 0xfe0e BRKSCR; /* Break Status and Control Register */
#define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
#define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
#endif

408
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/hc08/mc68hc908jkjl.h Normal file
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@@ -0,0 +1,408 @@
/*-------------------------------------------------------------------------
mc68hc908jkjl.h - register declarations for Motorola MC68HC908JK1/JK3/JL3/JK8/JL8
Copyright (C) 2004, Lucas Loizaga <lucas.loizaga AT ingenieria-inversa.com.ar>
Based on mc68hc908qy.h,
Written By - Erik Petrich <epetrich AT users.sourceforge.net> (2003)
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef _MC68HC908JKJL_H
#define _MC68HC908JKJL_H
#ifndef _UINT8
#define _UINT8 unsigned char
#endif
#ifndef _UINT16
#define _UINT16 unsigned int
#endif
#ifndef _VOLDATA
#define _VOLDATA volatile __data
#endif
#ifndef _VOLXDATA
#define _VOLXDATA volatile __xdata
#endif
struct __hc08_bits
{
unsigned int bit0:1;
unsigned int bit1:1;
unsigned int bit2:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
};
_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
#define PORTA PTA /* Alias for PTA */
#define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
#define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
#define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
#define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
#define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
#define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
#define PTA6 ((struct __hc08_bits *)(&PTA))->bit6
#define PTA7 ((struct __hc08_bits *)(&PTA))->bit7
_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
#define PORTB PTB /* Alias for PTB */
#define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
#define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
#define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
#define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
#define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
#define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
#define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
#define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
_VOLDATA _UINT8 __at 0x03 PTD; /* Port D Data Register */
#define PORTD PTD /* Alias for PTD */
#define PTD0 ((struct __hc08_bits *)(&PTD))->bit0
#define PTD1 ((struct __hc08_bits *)(&PTD))->bit1
#define PTD2 ((struct __hc08_bits *)(&PTD))->bit2
#define PTD3 ((struct __hc08_bits *)(&PTD))->bit3
#define PTD4 ((struct __hc08_bits *)(&PTD))->bit4
#define PTD5 ((struct __hc08_bits *)(&PTD))->bit5
#define PTD6 ((struct __hc08_bits *)(&PTD))->bit6
#define PTD7 ((struct __hc08_bits *)(&PTD))->bit7
_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
#define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
#define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
#define DDRA2 ((struct __hc08_bits *)(&DDRA))->bit2
#define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
#define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
#define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
#define DDRA6 ((struct __hc08_bits *)(&DDRA))->bit6
#define DDRA7 ((struct __hc08_bits *)(&DDRA))->bit7
_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
#define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
#define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
#define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
#define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
#define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
#define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
#define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
#define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
_VOLDATA _UINT8 __at 0x07 DDRD; /* Data Direction Register D */
#define DDRD0 ((struct __hc08_bits *)(&DDRD))->bit0
#define DDRD1 ((struct __hc08_bits *)(&DDRD))->bit1
#define DDRD2 ((struct __hc08_bits *)(&DDRD))->bit2
#define DDRD3 ((struct __hc08_bits *)(&DDRD))->bit3
#define DDRD4 ((struct __hc08_bits *)(&DDRD))->bit4
#define DDRD5 ((struct __hc08_bits *)(&DDRD))->bit5
#define DDRD6 ((struct __hc08_bits *)(&DDRD))->bit6
#define DDRD7 ((struct __hc08_bits *)(&DDRD))->bit7
_VOLDATA _UINT8 __at 0x08 PTE; /* Port E Data Register */
#define PORTE PTE /* Alias for PTE */
#define PTE0 ((struct __hc08_bits *)(&PTE))->bit0
#define PTE1 ((struct __hc08_bits *)(&PTE))->bit1
_VOLDATA _UINT8 __at 0x0A PDCR; /* Port D Control Register */
#define PTDPU6 ((struct __hc08_bits *)(&PDCR))->bit0
#define PTDPU7 ((struct __hc08_bits *)(&PDCR))->bit1
#define SLOWD6 ((struct __hc08_bits *)(&PDCR))->bit2
#define SLOWD7 ((struct __hc08_bits *)(&PDCR))->bit3
_VOLDATA _UINT8 __at 0x0C DDRE; /* Data Direction Register E */
#define DDRE0 ((struct __hc08_bits *)(&DDRE))->bit0
#define DDRE1 ((struct __hc08_bits *)(&DDRE))->bit1
_VOLDATA _UINT8 __at 0x0D PTAPUE; /* Port A pull-up enables */
#define PTAPUE0 ((struct __hc08_bits *)(&PTAPUE))->bit0
#define PTAPUE1 ((struct __hc08_bits *)(&PTAPUE))->bit1
#define PTAPUE2 ((struct __hc08_bits *)(&PTAPUE))->bit2
#define PTAPUE3 ((struct __hc08_bits *)(&PTAPUE))->bit3
#define PTAPUE4 ((struct __hc08_bits *)(&PTAPUE))->bit4
#define PTAPUE5 ((struct __hc08_bits *)(&PTAPUE))->bit5
#define PTAPUE6 ((struct __hc08_bits *)(&PTAPUE))->bit6
#define PTA6EN ((struct __hc08_bits *)(&PTAPUE))->bit7
_VOLDATA _UINT8 __at 0x0E PTA7PUE; /* Port A pull-up enables */
#define PTAPUE7 ((struct __hc08_bits *)(&PTA7PUE))->bit7
_VOLDATA _UINT8 __at 0x13 SCC1; /* SCI Control Register 1 */
#define LOOPS ((struct __hc08_bits *)(&SCC1))->bit7
#define ENSCI ((struct __hc08_bits *)(&SCC1))->bit6
#define TXINV ((struct __hc08_bits *)(&SCC1))->bit5
#define M ((struct __hc08_bits *)(&SCC1))->bit4
#define WAKE ((struct __hc08_bits *)(&SCC1))->bit3
#define ILTY ((struct __hc08_bits *)(&SCC1))->bit2
#define PEN ((struct __hc08_bits *)(&SCC1))->bit1
#define PTY ((struct __hc08_bits *)(&SCC1))->bit0
_VOLDATA _UINT8 __at 0x14 SCC2; /* SCI Control Register 2 */
#define SCTIE ((struct __hc08_bits *)(&SCC2))->bit7
#define TCIE ((struct __hc08_bits *)(&SCC2))->bit6
#define SCRIE ((struct __hc08_bits *)(&SCC2))->bit5
#define ILIE ((struct __hc08_bits *)(&SCC2))->bit4
#define TE ((struct __hc08_bits *)(&SCC2))->bit3
#define RE ((struct __hc08_bits *)(&SCC2))->bit2
#define WRU ((struct __hc08_bits *)(&SCC2))->bit1
#define SBK ((struct __hc08_bits *)(&SCC2))->bit0
_VOLDATA _UINT8 __at 0x15 SCC3; /* SCI Control Register 3 */
#define SCC3_R8 ((struct __hc08_bits *)(&SCC3))->bit7
#define SCC3_TB ((struct __hc08_bits *)(&SCC3))->bit6
#define DMARE ((struct __hc08_bits *)(&SCC3))->bit5
#define DMATE ((struct __hc08_bits *)(&SCC3))->bit4
#define ORIE ((struct __hc08_bits *)(&SCC3))->bit3
#define NEIE ((struct __hc08_bits *)(&SCC3))->bit2
#define FEIE ((struct __hc08_bits *)(&SCC3))->bit1
#define PEIE ((struct __hc08_bits *)(&SCC3))->bit0
_VOLDATA _UINT8 __at 0x16 SCS1; /* SCI Status Register 1 */
#define SCTE ((struct __hc08_bits *)(&SCS1))->bit7
#define TC ((struct __hc08_bits *)(&SCS1))->bit6
#define SCRF ((struct __hc08_bits *)(&SCS1))->bit5
#define IDLE ((struct __hc08_bits *)(&SCS1))->bit4
#define OR ((struct __hc08_bits *)(&SCS1))->bit3
#define NF ((struct __hc08_bits *)(&SCS1))->bit2
#define FE ((struct __hc08_bits *)(&SCS1))->bit1
#define PE ((struct __hc08_bits *)(&SCS1))->bit0
_VOLDATA _UINT8 __at 0x17 SCS2; /* SCI Status Register 2 */
#define RPF ((struct __hc08_bits *)(&SCS2))->bit0
#define BKF ((struct __hc08_bits *)(&SCS2))->bit1
/* Bits 2-7 not implemented */
_VOLDATA _UINT8 __at 0x18 SCDR; /* SCI Data Register */
_VOLDATA _UINT8 __at 0x19 SCBR; /* SCI Baud Rate Register */
#define SCP1 ((struct __hc08_bits *)(&SCBR))->bit5
#define SCP0 ((struct __hc08_bits *)(&SCBR))->bit4
#define R ((struct __hc08_bits *)(&SCBR))->bit3
#define SCR2 ((struct __hc08_bits *)(&SCBR))->bit2
#define SCR1 ((struct __hc08_bits *)(&SCBR))->bit1
#define SCR0 ((struct __hc08_bits *)(&SCBR))->bit0
/*-- Bits 6 and 7 do not exist */
_VOLDATA _UINT8 __at 0x1a KBSCR; /* Keyboard Status and Control Register */
#define MODEK ((struct __hc08_bits *)(&KBSCR))->bit0
#define IMASKK ((struct __hc08_bits *)(&KBSCR))->bit1
#define ACKK ((struct __hc08_bits *)(&KBSCR))->bit2
#define KEYF ((struct __hc08_bits *)(&KBSCR))->bit3
/*-- Bits 4-7 do not exist */
_VOLDATA _UINT8 __at 0x1b KBIER; /* Keyboard Interrupt Enable Register */
#define KBIE0 ((struct __hc08_bits *)(&KBIER))->bit0
#define KBIE1 ((struct __hc08_bits *)(&KBIER))->bit1
#define KBIE3 ((struct __hc08_bits *)(&KBIER))->bit3
#define KBIE2 ((struct __hc08_bits *)(&KBIER))->bit2
#define KBIE4 ((struct __hc08_bits *)(&KBIER))->bit4
#define KBIE5 ((struct __hc08_bits *)(&KBIER))->bit5
#define KBIE6 ((struct __hc08_bits *)(&KBIER))->bit6
#define KBIE7 ((struct __hc08_bits *)(&KBIER))->bit7
_VOLDATA _UINT8 __at 0x1D INTSCR; /* IRQ status/control */
#define IRQF1 ((struct __hc08_bits *)(&INTSCR))->bit3
#define ACK1 ((struct __hc08_bits *)(&INTSCR))->bit2
#define IMASK1 ((struct __hc08_bits *)(&INTSCR))->bit1
#define MODE1 ((struct __hc08_bits *)(&INTSCR))->bit0
/* Bits 4-7 unimplemented */
_VOLDATA _UINT8 __at 0x1e CONFIG2; /* Configuration Register 2 */
/* CONFIG2 is one-time writeble, so can't use bitfields */
_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
/* CONFIG1 is one-time writeable, so can't use bitfields */
_VOLDATA _UINT8 __at 0x20 T1SC; /* TIM 1 Status and Control */
#define PS0 ((struct __hc08_bits *)(&T1SC))->bit0
#define PS1 ((struct __hc08_bits *)(&T1SC))->bit1
#define PS2 ((struct __hc08_bits *)(&T1SC))->bit2
#define TRST ((struct __hc08_bits *)(&T1SC))->bit4
#define TSTOP ((struct __hc08_bits *)(&T1SC))->bit5
#define TOIE ((struct __hc08_bits *)(&T1SC))->bit6
#define TOF ((struct __hc08_bits *)(&T1SC))->bit7
_VOLDATA _UINT16 __at 0x21 T1CNT; /* TIM1 Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x21 T1CNTH; /* TIM1 Counter Register High */
_VOLDATA _UINT8 __at 0x22 T1CNTL; /* TIM1 Counter Register Low */
_VOLDATA _UINT16 __at 0x23 T1MOD; /* TIM1 Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x23 T1MODH; /* TIM1 Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x24 T1MODL; /* TIM1 Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x25 T1SC0; /* TIM1 Channel 0 Status and Control Register */
#define CH0MAX ((struct __hc08_bits *)(&T1SC0))->bit0
#define TOV0 ((struct __hc08_bits *)(&T1SC0))->bit1
#define ELS0A ((struct __hc08_bits *)(&T1SC0))->bit2
#define ELS0B ((struct __hc08_bits *)(&T1SC0))->bit3
#define MS0A ((struct __hc08_bits *)(&T1SC0))->bit4
#define MS0B ((struct __hc08_bits *)(&T1SC0))->bit5
#define CH0IE ((struct __hc08_bits *)(&T1SC0))->bit6
#define CH0F ((struct __hc08_bits *)(&T1SC0))->bit7
_VOLDATA _UINT16 __at 0x26 T1CH0; /* TIM1 Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x26 T1CH0H; /* TIM1 Channel 0 Register High */
_VOLDATA _UINT8 __at 0x27 T1CH0L; /* TIM1 Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x28 T1SC1; /* TIM1 Channel 1 Status and Control Register */
#define CH1MAX ((struct __hc08_bits *)(&T1SC1))->bit0
#define TOV1 ((struct __hc08_bits *)(&T1SC1))->bit1
#define ELS1A ((struct __hc08_bits *)(&T1SC1))->bit2
#define ELS1B ((struct __hc08_bits *)(&T1SC1))->bit3
#define MS1A ((struct __hc08_bits *)(&T1SC1))->bit4
#define CH1IE ((struct __hc08_bits *)(&T1SC1))->bit6
#define CH1F ((struct __hc08_bits *)(&T1SC1))->bit7
_VOLDATA _UINT16 __at 0x29 T1CH1; /* TIM1 Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x29 T1CH1H; /* TIM1 Channel 1 Register High */
_VOLDATA _UINT8 __at 0x2A T1CH1L; /* TIM1 Channel 1 Register Low */
_VOLDATA _UINT8 __at 0x30 T2SC; /* TIM2 Status and Control Register */
#define PS0_2 ((struct __hc08_bits *)(&T2SC))->bit0
#define PS1_2 ((struct __hc08_bits *)(&T2SC0))->bit1
#define PS2_2 ((struct __hc08_bits *)(&T2SC0))->bit2
#define TRST_2 ((struct __hc08_bits *)(&T2SC0))->bit4
#define TSTOP_2 ((struct __hc08_bits *)(&T2SC0))->bit5
#define TOIE_2 ((struct __hc08_bits *)(&T2SC0))->bit6
#define TOF_2 ((struct __hc08_bits *)(&T2SC0))->bit7
_VOLDATA _UINT16 __at 0x31 T2CNT; /* TIM2 Counter Registers */
_VOLDATA _UINT8 __at 0x31 T2CNTH; /* TIM2 Counter Register High */
_VOLDATA _UINT8 __at 0x32 T2CNTL; /* TIM2 Counter Register Low */
_VOLDATA _UINT16 __at 0x33 T2MOD; /* TIM2 Counter Modulo Registers */
_VOLDATA _UINT8 __at 0x33 T2MODH; /* TIM2 Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x34 T2MODL; /* TIM2 Counter Modulo Register Low */
_VOLDATA _UINT8 __at 0x35 T2SC0; /* TIM2 Channel 0 Status and Control Register */
#define CH0MAX_2 ((struct __hc08_bits *)(&T2SC0))->bit0
#define TOV0_2 ((struct __hc08_bits *)(&T2SC0))->bit1
#define ELS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit2
#define ELS0B_2 ((struct __hc08_bits *)(&T2SC0))->bit3
#define MS0A_2 ((struct __hc08_bits *)(&T2SC0))->bit4
#define CH0IE_2 ((struct __hc08_bits *)(&T2SC0))->bit6
#define CH0F_2 ((struct __hc08_bits *)(&T2SC0))->bit7
_VOLDATA _UINT16 __at 0x36 T2CH0; /* TIM2 Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x36 T2CH0H; /* TIM2 Channel 0 Register High */
_VOLDATA _UINT8 __at 0x37 T2CH0L; /* TIM2 Channel 0 Register Low */
_VOLDATA _UINT8 __at 0x38 T2SC1; /* TIM2 Channel 1 Status and Control Register */
#define CH1MAX_2 ((struct __hc08_bits *)(&T2SC1))->bit0
#define TOV1_2 ((struct __hc08_bits *)(&T2SC1))->bit1
#define ELS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit2
#define ELS1B_2 ((struct __hc08_bits *)(&T2SC1))->bit3
#define MS1A_2 ((struct __hc08_bits *)(&T2SC1))->bit4
#define CH1IE_2 ((struct __hc08_bits *)(&T2SC1))->bit6
#define CH1F_2 ((struct __hc08_bits *)(&T2SC1))->bit7
_VOLDATA _UINT16 __at 0x39 T2CH1; /* TIM2 Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x39 T2CH1H; /* TIM2 Channel 1 Register High */
_VOLDATA _UINT8 __at 0x3a T2CH1L; /* TIM2 Channel 1 Register Low */
_VOLDATA _UINT8 __at 0x3c ADSCR; /* Analog-to-Digital Status and Control Reg. */
#define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
#define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
#define ADCO ((struct __hc08_bits *)(&ADSCR))->bit5
#define ADCH4 ((struct __hc08_bits *)(&ADSCR))->bit4
#define ADCH3 ((struct __hc08_bits *)(&ADSCR))->bit3
#define ADCH2 ((struct __hc08_bits *)(&ADSCR))->bit2
#define ADCH1 ((struct __hc08_bits *)(&ADSCR))->bit1
#define ADCH0 ((struct __hc08_bits *)(&ADSCR))->bit0
_VOLDATA _UINT8 __at 0x3d ADR; /* Analog-to-Digital Data Register */
_VOLDATA _UINT8 __at 0x3e ADCLK; /* Analog-to-Digital Clock */
#define ADIV2 ((struct __hc08_bits *)(&ADCLK))->bit7
#define ADIV1 ((struct __hc08_bits *)(&ADCLK))->bit6
#define ADIV0 ((struct __hc08_bits *)(&ADCLK))->bit5
/* Bits 0-4 unimplemented */
_VOLXDATA _UINT8 __at 0xfe00 BSR; /* SIM Break Status Register */
#define SBSW ((struct __hc08_bits *)(&BSR))->bit1
_VOLXDATA _UINT8 __at 0xfe01 RSR; /* SIM Reset Status Register */
#define LVI ((struct __hc08_bits *)(&RSR))->bit1
#define MODRST ((struct __hc08_bits *)(&RSR))->bit2
#define ILAD ((struct __hc08_bits *)(&RSR))->bit3
#define ILOP ((struct __hc08_bits *)(&RSR))->bit4
#define COP ((struct __hc08_bits *)(&RSR))->bit5
#define PIN ((struct __hc08_bits *)(&RSR))->bit6
#define POR ((struct __hc08_bits *)(&RSR))->bit7
/* Bit 0 unimplemented */
_VOLXDATA _UINT8 __at 0xfe02 SUBAR; /* SIM Upper Byte Address */
_VOLXDATA _UINT8 __at 0xfe03 BFCR; /* SIM Break Flag Control Register */
#define BFCE ((struct __hc08_bits *)(&BFCR))->bit7
_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
#define IF1 ((struct __hc08_bits *)(&INT1))->bit2
#define IF3 ((struct __hc08_bits *)(&INT1))->bit4
#define IF4 ((struct __hc08_bits *)(&INT1))->bit5
#define IF5 ((struct __hc08_bits *)(&INT1))->bit6
_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
#define IF14 ((struct __hc08_bits *)(&INT2))->bit7
_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
#define IF16 ((struct __hc08_bits *)(&INT3))->bit1
#define IF15 ((struct __hc08_bits *)(&INT3))->bit0
_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
#define PGM ((struct __hc08_bits *)(&FLCR))->bit0
#define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
#define MASS ((struct __hc08_bits *)(&FLCR))->bit2
#define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
_VOLXDATA _UINT8 __at 0xfe09 FLBPR; /* Flash Block Protect Register */
#define BPR0 ((struct __hc08_bits *)(&FLBPR))->bit0
#define BPR1 ((struct __hc08_bits *)(&FLBPR))->bit1
#define BPR2 ((struct __hc08_bits *)(&FLBPR))->bit2
#define BPR3 ((struct __hc08_bits *)(&FLBPR))->bit3
#define BPR4 ((struct __hc08_bits *)(&FLBPR))->bit4
#define BPR5 ((struct __hc08_bits *)(&FLBPR))->bit5
#define BPR6 ((struct __hc08_bits *)(&FLBPR))->bit6
#define BPR7 ((struct __hc08_bits *)(&FLBPR))->bit7
_VOLXDATA _UINT16 __at 0xfe0C BRK; /* Break Address High & Low Registers */
_VOLXDATA _UINT8 __at 0xfe0C BRKH; /* Break Address High Register */
_VOLXDATA _UINT8 __at 0xfe0D BRKL; /* Break Address Low Register */
_VOLXDATA _UINT8 __at 0xfe0e BRKSCR; /* Break Status and Control Register */
#define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
#define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
#endif

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/*-------------------------------------------------------------------------
mc68hc908qy.h - Register Declarations for Motorola MC68HC908QY & MC68HC908QT
Copyright (C) 2003, Erik Petrich epetrich@users.sourceforge.net
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef _MC68HC908QY_H
#define _MC68HC908QY_H
#ifndef _UINT8
#define _UINT8 unsigned char
#endif
#ifndef _UINT16
#define _UINT16 unsigned int
#endif
#ifndef _VOLDATA
#define _VOLDATA volatile __data
#endif
#ifndef _VOLXDATA
#define _VOLXDATA volatile __xdata
#endif
struct __hc08_bits
{
unsigned int bit0:1;
unsigned int bit1:1;
unsigned int bit2:1;
unsigned int bit3:1;
unsigned int bit4:1;
unsigned int bit5:1;
unsigned int bit6:1;
unsigned int bit7:1;
};
_VOLDATA _UINT8 __at 0x00 PTA; /* Port A Data Register */
#define PTA0 ((struct __hc08_bits *)(&PTA))->bit0
#define PTA1 ((struct __hc08_bits *)(&PTA))->bit1
#define PTA2 ((struct __hc08_bits *)(&PTA))->bit2
#define PTA3 ((struct __hc08_bits *)(&PTA))->bit3
#define PTA4 ((struct __hc08_bits *)(&PTA))->bit4
#define PTA5 ((struct __hc08_bits *)(&PTA))->bit5
#define AWUL ((struct __hc08_bits *)(&PTA))->bit6
_VOLDATA _UINT8 __at 0x01 PTB; /* Port B Data Register */
#define PTB0 ((struct __hc08_bits *)(&PTB))->bit0
#define PTB1 ((struct __hc08_bits *)(&PTB))->bit1
#define PTB2 ((struct __hc08_bits *)(&PTB))->bit2
#define PTB3 ((struct __hc08_bits *)(&PTB))->bit3
#define PTB4 ((struct __hc08_bits *)(&PTB))->bit4
#define PTB5 ((struct __hc08_bits *)(&PTB))->bit5
#define PTB6 ((struct __hc08_bits *)(&PTB))->bit6
#define PTB7 ((struct __hc08_bits *)(&PTB))->bit7
_VOLDATA _UINT8 __at 0x04 DDRA; /* Data Direction Register A */
#define DDRA0 ((struct __hc08_bits *)(&DDRA))->bit0
#define DDRA1 ((struct __hc08_bits *)(&DDRA))->bit1
#define DDRA3 ((struct __hc08_bits *)(&DDRA))->bit3
#define DDRA4 ((struct __hc08_bits *)(&DDRA))->bit4
#define DDRA5 ((struct __hc08_bits *)(&DDRA))->bit5
_VOLDATA _UINT8 __at 0x05 DDRB; /* Data Direction Register B */
#define DDRB0 ((struct __hc08_bits *)(&DDRB))->bit0
#define DDRB1 ((struct __hc08_bits *)(&DDRB))->bit1
#define DDRB2 ((struct __hc08_bits *)(&DDRB))->bit2
#define DDRB3 ((struct __hc08_bits *)(&DDRB))->bit3
#define DDRB4 ((struct __hc08_bits *)(&DDRB))->bit4
#define DDRB5 ((struct __hc08_bits *)(&DDRB))->bit5
#define DDRB6 ((struct __hc08_bits *)(&DDRB))->bit6
#define DDRB7 ((struct __hc08_bits *)(&DDRB))->bit7
_VOLDATA _UINT8 __at 0x0b PTAPUE; /* Port A Input Pullup Enable Register */
#define PTAPUE0 ((struct __hc08_bits *)(&PTAPUE))->bit0
#define PTAPUE1 ((struct __hc08_bits *)(&PTAPUE))->bit1
#define PTAPUE2 ((struct __hc08_bits *)(&PTAPUE))->bit2
#define PTAPUE3 ((struct __hc08_bits *)(&PTAPUE))->bit3
#define PTAPUE4 ((struct __hc08_bits *)(&PTAPUE))->bit4
#define PTAPUE5 ((struct __hc08_bits *)(&PTAPUE))->bit5
#define OSC2EN ((struct __hc08_bits *)(&PTAPUE))->bit7
_VOLDATA _UINT8 __at 0x0c PTBPUE; /* Port B Input Pullup Enable Register */
#define PTBPUE0 ((struct __hc08_bits *)(&PTBPUE))->bit0
#define PTBPUE1 ((struct __hc08_bits *)(&PTBPUE))->bit1
#define PTBPUE2 ((struct __hc08_bits *)(&PTBPUE))->bit2
#define PTBPUE3 ((struct __hc08_bits *)(&PTBPUE))->bit3
#define PTBPUE4 ((struct __hc08_bits *)(&PTBPUE))->bit4
#define PTBPUE5 ((struct __hc08_bits *)(&PTBPUE))->bit5
#define PTBPUE6 ((struct __hc08_bits *)(&PTBPUE))->bit6
#define PTBPUE7 ((struct __hc08_bits *)(&PTBPUE))->bit7
_VOLDATA _UINT8 __at 0x1a KBSCR; /* Keyboard Status and Control Register */
#define MODEK ((struct __hc08_bits *)(&KBSCR))->bit0
#define IMASKK ((struct __hc08_bits *)(&KBSCR))->bit1
#define ACKK ((struct __hc08_bits *)(&KBSCR))->bit2
#define KEYF ((struct __hc08_bits *)(&KBSCR))->bit3
_VOLDATA _UINT8 __at 0x1b KBIER; /* Keyboard Interrupt Enable Register */
#define KBIE0 ((struct __hc08_bits *)(&KBIER))->bit0
#define KBIE1 ((struct __hc08_bits *)(&KBIER))->bit1
#define KBIE2 ((struct __hc08_bits *)(&KBIER))->bit2
#define KBIE3 ((struct __hc08_bits *)(&KBIER))->bit3
#define KBIE4 ((struct __hc08_bits *)(&KBIER))->bit4
#define KBIE5 ((struct __hc08_bits *)(&KBIER))->bit5
#define AWUIE ((struct __hc08_bits *)(&KBIER))->bit6
_VOLDATA _UINT8 __at 0x1d INTSCR; /* IRQ Status and Control Register */
#define MODE1 ((struct __hc08_bits *)(&INTSCR))->bit0
#define IMASK1 ((struct __hc08_bits *)(&INTSCR))->bit1
#define ACK1 ((struct __hc08_bits *)(&INTSCR))->bit2
#define IRQF1 ((struct __hc08_bits *)(&INTSCR))->bit3
_VOLDATA _UINT8 __at 0x1e CONFIG2; /* Configuration Register 2 */
/* CONFIG2 is one-time writeable, so can't use bitfields */
_VOLDATA _UINT8 __at 0x1f CONFIG1; /* Configuration Register 1 */
/* CONFIG1 is one-time writeable, so can't use bitfields */
_VOLDATA _UINT8 __at 0x20 TSC; /* TIM Status and Control */
#define PS0 ((struct __hc08_bits *)(&TSC))->bit0
#define PS1 ((struct __hc08_bits *)(&TSC))->bit1
#define PS2 ((struct __hc08_bits *)(&TSC))->bit2
#define TRST ((struct __hc08_bits *)(&TSC))->bit4
#define TSTOP ((struct __hc08_bits *)(&TSC))->bit5
#define TOIE ((struct __hc08_bits *)(&TSC))->bit6
#define TOF ((struct __hc08_bits *)(&TSC))->bit7
_VOLDATA _UINT8 __at 0x21 TCNTH; /* TIM Counter Register High */
_VOLDATA _UINT8 __at 0x22 TCNTL; /* TIM Counter Register Low */
_VOLDATA _UINT16 __at 0x21 TCNT; /* TIM Counter High & Low Registers */
_VOLDATA _UINT8 __at 0x23 TMODH; /* TIM Counter Modulo Register High */
_VOLDATA _UINT8 __at 0x24 TMODL; /* TIM Counter Modulo Register Low */
_VOLDATA _UINT16 __at 0x23 TMOD; /* TIM Counter Modulo High & Low Registers */
_VOLDATA _UINT8 __at 0x25 TSC0; /* TIM Channel 0 Status and Control Register */
#define CH0MAX ((struct __hc08_bits *)(&TSC0))->bit0
#define TOV0 ((struct __hc08_bits *)(&TSC0))->bit1
#define ELS0A ((struct __hc08_bits *)(&TSC0))->bit2
#define ELS0B ((struct __hc08_bits *)(&TSC0))->bit3
#define MS0A ((struct __hc08_bits *)(&TSC0))->bit4
#define MS0B ((struct __hc08_bits *)(&TSC0))->bit5
#define CH0IE ((struct __hc08_bits *)(&TSC0))->bit6
#define CH0F ((struct __hc08_bits *)(&TSC0))->bit7
_VOLDATA _UINT8 __at 0x26 TCH0H; /* TIM Channel 0 Register High */
_VOLDATA _UINT8 __at 0x27 TCH0L; /* TIM Channel 0 Register Low */
_VOLDATA _UINT16 __at 0x26 TCH0; /* TIM Channel 0 High & Low Registers */
_VOLDATA _UINT8 __at 0x28 TSC1; /* TIM Channel 1 Status and Control Register */
#define CH1MAX ((struct __hc08_bits *)(&TSC1))->bit0
#define TOV1 ((struct __hc08_bits *)(&TSC1))->bit1
#define ELS1A ((struct __hc08_bits *)(&TSC1))->bit2
#define ELS1B ((struct __hc08_bits *)(&TSC1))->bit3
#define MS1A ((struct __hc08_bits *)(&TSC1))->bit4
#define MS1B ((struct __hc08_bits *)(&TSC1))->bit5
#define CH1IE ((struct __hc08_bits *)(&TSC1))->bit6
#define CH1F ((struct __hc08_bits *)(&TSC1))->bit7
_VOLDATA _UINT8 __at 0x29 TCH1H; /* TIM Channel 1 Register High */
_VOLDATA _UINT8 __at 0x2a TCH1L; /* TIM Channel 1 Register Low */
_VOLDATA _UINT16 __at 0x29 TCH1; /* TIM Channel 1 High & Low Registers */
_VOLDATA _UINT8 __at 0x36 OSCSTAT; /* Oscillator Status Register */
#define ECGST ((struct __hc08_bits *)(&OSCSTAT))->bit0
#define ECGON ((struct __hc08_bits *)(&OSCSTAT))->bit1
_VOLDATA _UINT8 __at 0x38 OSCTRIM; /* Oscillator Trim Register */
_VOLDATA _UINT8 __at 0x3c ADSCR; /* ADC Status and Control Register */
#define CH0 ((struct __hc08_bits *)(&ADSCR))->bit0
#define CH1 ((struct __hc08_bits *)(&ADSCR))->bit1
#define CH2 ((struct __hc08_bits *)(&ADSCR))->bit2
#define CH3 ((struct __hc08_bits *)(&ADSCR))->bit3
#define CH4 ((struct __hc08_bits *)(&ADSCR))->bit4
#define ADC0 ((struct __hc08_bits *)(&ADSCR))->bit5
#define AIEN ((struct __hc08_bits *)(&ADSCR))->bit6
#define COCO ((struct __hc08_bits *)(&ADSCR))->bit7
_VOLDATA _UINT8 __at 0x3e ADR; /* ADC Data Register */
_VOLDATA _UINT8 __at 0x3f ADICLK; /* ADS Input Clock Register */
#define ADIV0 ((struct __hc08_bits *)(&ADICLK))->bit5
#define ADIV1 ((struct __hc08_bits *)(&ADICLK))->bit6
#define ADIV2 ((struct __hc08_bits *)(&ADICLK))->bit7
_VOLXDATA _UINT8 __at 0xfe00 BSR; /* Break Status Register */
#define SBSW ((struct __hc08_bits *)(&BSR))->bit1
_VOLXDATA _UINT8 __at 0xfe01 SRSR; /* SIM Reset Status Register */
#define LVI ((struct __hc08_bits *)(&SRSR))->bit1
#define MODRST ((struct __hc08_bits *)(&SRSR))->bit2
#define ILAD ((struct __hc08_bits *)(&SRSR))->bit3
#define ILOP ((struct __hc08_bits *)(&SRSR))->bit4
#define COP ((struct __hc08_bits *)(&SRSR))->bit5
#define PIN ((struct __hc08_bits *)(&SRSR))->bit6
#define POR ((struct __hc08_bits *)(&SRSR))->bit7
_VOLXDATA _UINT8 __at 0xfe02 BRKAR; /* Break Auxilliary Register */
#define BDCOP ((struct __hc08_bits *)(&BRKAR))->bit0
_VOLXDATA _UINT8 __at 0xfe03 BFCF; /* Break Flag Control Register */
#define BFCF ((struct __hc08_bits *)(&BFCF))->bit7
_VOLXDATA _UINT8 __at 0xfe04 INT1; /* Interrupt Status Register 1 */
#define IF1 ((struct __hc08_bits *)(&INT1))->bit2
#define IF3 ((struct __hc08_bits *)(&INT1))->bit4
#define IF4 ((struct __hc08_bits *)(&INT1))->bit5
#define IF5 ((struct __hc08_bits *)(&INT1))->bit6
_VOLXDATA _UINT8 __at 0xfe05 INT2; /* Interrupt Status Register 2 */
#define IF14 ((struct __hc08_bits *)(&INT2))->bit7
_VOLXDATA _UINT8 __at 0xfe06 INT3; /* Interrupt Status Register 3 */
#define IF15 ((struct __hc08_bits *)(&INT3))->bit0
_VOLXDATA _UINT8 __at 0xfe08 FLCR; /* FLASH Control Register */
#define PGM ((struct __hc08_bits *)(&FLCR))->bit0
#define ERASE ((struct __hc08_bits *)(&FLCR))->bit1
#define MASS ((struct __hc08_bits *)(&FLCR))->bit2
#define HVEN ((struct __hc08_bits *)(&FLCR))->bit3
_VOLXDATA _UINT8 __at 0xfe09 BRKH; /* Break Address High Register */
_VOLXDATA _UINT8 __at 0xfe0a BRKL; /* Break Address Low Register */
_VOLXDATA _UINT16 __at 0xfe09 BRK; /* Break Address High & Low Registers */
_VOLXDATA _UINT8 __at 0xfe0b BRKSCR; /* Break Status and Control Register */
#define BRKA ((struct __hc08_bits *)(&BRKSCR))->bit6
#define BRKE ((struct __hc08_bits *)(&BRKSCR))->bit7
_VOLXDATA _UINT8 __at 0xfe0c LVISR; /* LVI Status Register */
#define LVIOUT ((struct __hc08_bits *)(&LVISR))->bit7
_VOLXDATA _UINT8 __at 0xffbe FLBPR; /* FLASH Block Protect Register */
_VOLXDATA _UINT8 __at 0xffc0 OSCTRIMVAL; /* Oscillator Trim Value */
_VOLXDATA _UINT8 __at 0xffff COPCTL; /* COP Control Register */
#endif

45
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/*-------------------------------------------------------------------------
iso646.h
Copyright (C) 2011, Philipp Klaus Krause . pkk@spth.de
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __SDCC_ISO646_H
#define __SDCC_ISO646_H
#define and &&
#define and_eq &=
#define bitand &
#define bitor |
#define compl ~
#define not !
#define not_eq !=
#define or ||
#define or_eq |=
#define xor ^
#define xor_eq ^=
#endif

77
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/limits.h Normal file
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@@ -0,0 +1,77 @@
/*-------------------------------------------------------------------------
limits.h - ANSI defines constants for sizes of integral types
Copyright (C) 1999, Sandeep Dutta . sandeep.dutta@usa.net
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef __STDC_VERSION_LIMITS_H__
#define __STDC_VERSION_LIMITS_H__ __STDC_VERSION__
#define CHAR_BIT 8 /* bits in a char */
#define SCHAR_MAX 127
#define SCHAR_MIN -128
#define UCHAR_MAX 0xff
#ifdef __SDCC_CHAR_UNSIGNED
#define CHAR_MAX UCHAR_MAX
#define CHAR_MIN 0
#else
#define CHAR_MAX SCHAR_MAX
#define CHAR_MIN SCHAR_MIN
#endif
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199409L
#define MB_LEN_MAX 4
#endif
#define INT_MIN (-32767 - 1)
#define INT_MAX 32767
#define SHRT_MAX INT_MAX
#define SHRT_MIN INT_MIN
#define UINT_MAX 0xffff
#define UINT_MIN 0
#define USHRT_MAX UINT_MAX
#define USHRT_MIN UINT_MIN
#define LONG_MIN (-2147483647L-1)
#define LONG_MAX 2147483647L
#define ULONG_MAX 0xffffffff
#define ULONG_MIN 0
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#define LLONG_MIN (-9223372036854775807LL-1)
#define LLONG_MAX 9223372036854775807LL
#define ULLONG_MAX 18446744073709551615ULL
#endif
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L
#define BITINT_MAXWIDTH __SDCC_BITINT_MAXWIDTH
#define USHRT_WIDTH 16
#define UINT_WIDTH 16
#define ULONG_WIDTH 32
#define ULLONG_WIDTH 64
#endif
#endif

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/*-------------------------------------------------------------------------
math.h: Floating point math function declarations
Copyright (C) 2001, Jesus Calvino-Fraga, jesusc@ieee.org
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
/* Version 1.0 - Initial release */
#ifndef _INC_MATH
#define _INC_MATH
#define HUGE_VALF 3.402823466e+38
#define PI 3.1415926536
#define TWO_PI 6.2831853071
#define HALF_PI 1.5707963268
#define QUART_PI 0.7853981634
#define iPI 0.3183098862
#define iTWO_PI 0.1591549431
#define TWO_O_PI 0.6366197724
/* EPS=B**(-t/2), where B is the radix of the floating-point representation
and there are t base-B digits in the significand. Therefore, for floats
EPS=2**(-12). Also define EPS2=EPS*EPS. */
#define EPS 244.14062E-6
#define EPS2 59.6046E-9
union float_long
{
float f;
long l;
};
#if defined(__SDCC_MATH_LIB) && defined(__SDCC_mcs51) && !defined(__SDCC_USE_XSTACK) && !defined(__SDCC_STACK_AUTO) && !defined(_SDCC_NO_ASM_LIB_FUNCS)
/* Compile the mcs51 assembly version only when all these
conditions are met. Since not all the functions are
reentrant, do not compile with --stack-auto is used. */
#define MATH_ASM_MCS51
#endif
/* Functions on the z80 and related are always reentrant and so the "reentrant" */
/* keyword is not defined. */
#if defined(__SDCC_z80) || defined(__SDCC_z180) || defined(__SDCC_r2k) || defined(__SDCC_r2ka) || defined(__SDCC_r3ka) || defined(__SDCC_tlcs90) || defined(__SDCC_sm83) || defined(__SDCC_ez80_z80) || defined(__SDCC_z80n) || defined(__SDCC_stm8)
#define _FLOAT_FUNC_REENTRANT
#else
#define _FLOAT_FUNC_REENTRANT __reentrant
#endif
/**********************************************
* Prototypes for float ANSI C math functions *
**********************************************/
/* Trigonometric functions */
float sinf(float x) _FLOAT_FUNC_REENTRANT;
float cosf(float x) _FLOAT_FUNC_REENTRANT;
float tanf(float x) _FLOAT_FUNC_REENTRANT;
float cotf(float x) _FLOAT_FUNC_REENTRANT;
float asinf(float x) _FLOAT_FUNC_REENTRANT;
float acosf(float x) _FLOAT_FUNC_REENTRANT;
float atanf(float x) _FLOAT_FUNC_REENTRANT;
float atan2f(float x, float y);
/* Hyperbolic functions */
float sinhf(float x) _FLOAT_FUNC_REENTRANT;
float coshf(float x) _FLOAT_FUNC_REENTRANT;
float tanhf(float x) _FLOAT_FUNC_REENTRANT;
/* Exponential, logarithmic and power functions */
float expf(float x) _FLOAT_FUNC_REENTRANT;
float logf(float x) _FLOAT_FUNC_REENTRANT;
float log10f(float x) _FLOAT_FUNC_REENTRANT;
float powf(float x, float y);
float sqrtf(float a) _FLOAT_FUNC_REENTRANT;
/* Nearest integer, absolute value, and remainder functions */
float fabsf(float x) _FLOAT_FUNC_REENTRANT;
float frexpf(float x, int *pw2);
float ldexpf(float x, int pw2);
float ceilf(float x) _FLOAT_FUNC_REENTRANT;
float floorf(float x) _FLOAT_FUNC_REENTRANT;
float modff(float x, float * y);
int isnan(float f);
int isinf(float f);
#endif /* _INC_MATH */

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/*-------------------------------------------------------------------------
8051.h: Register Declarations for the Intel 8051 Processor
Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef REG8051_H
#define REG8051_H
/* BYTE Register */
__sfr __at (0x80) P0 ;
__sfr __at (0x81) SP ;
__sfr __at (0x82) DPL ;
__sfr __at (0x83) DPH ;
__sfr __at (0x87) PCON ;
__sfr __at (0x88) TCON ;
__sfr __at (0x89) TMOD ;
__sfr __at (0x8A) TL0 ;
__sfr __at (0x8B) TL1 ;
__sfr __at (0x8C) TH0 ;
__sfr __at (0x8D) TH1 ;
__sfr __at (0x90) P1 ;
__sfr __at (0x98) SCON ;
__sfr __at (0x99) SBUF ;
__sfr __at (0xA0) P2 ;
__sfr __at (0xA8) IE ;
__sfr __at (0xB0) P3 ;
__sfr __at (0xB8) IP ;
__sfr __at (0xD0) PSW ;
__sfr __at (0xE0) ACC ;
__sfr __at (0xF0) B ;
/* BIT Register */
/* P0 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON */
__sbit __at (0x88) IT0 ;
__sbit __at (0x89) IE0 ;
__sbit __at (0x8A) IT1 ;
__sbit __at (0x8B) IE1 ;
__sbit __at (0x8C) TR0 ;
__sbit __at (0x8D) TF0 ;
__sbit __at (0x8E) TR1 ;
__sbit __at (0x8F) TF1 ;
/* P1 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON */
__sbit __at (0x98) RI ;
__sbit __at (0x99) TI ;
__sbit __at (0x9A) RB8 ;
__sbit __at (0x9B) TB8 ;
__sbit __at (0x9C) REN ;
__sbit __at (0x9D) SM2 ;
__sbit __at (0x9E) SM1 ;
__sbit __at (0x9F) SM0 ;
/* P2 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE */
__sbit __at (0xA8) EX0 ;
__sbit __at (0xA9) ET0 ;
__sbit __at (0xAA) EX1 ;
__sbit __at (0xAB) ET1 ;
__sbit __at (0xAC) ES ;
__sbit __at (0xAF) EA ;
/* P3 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
__sbit __at (0xB0) RXD ;
__sbit __at (0xB1) TXD ;
__sbit __at (0xB2) INT0 ;
__sbit __at (0xB3) INT1 ;
__sbit __at (0xB4) T0 ;
__sbit __at (0xB5) T1 ;
__sbit __at (0xB6) WR ;
__sbit __at (0xB7) RD ;
/* IP */
__sbit __at (0xB8) PX0 ;
__sbit __at (0xB9) PT0 ;
__sbit __at (0xBA) PX1 ;
__sbit __at (0xBB) PT1 ;
__sbit __at (0xBC) PS ;
/* PSW */
__sbit __at (0xD0) P ;
__sbit __at (0xD1) F1 ;
__sbit __at (0xD2) OV ;
__sbit __at (0xD3) RS0 ;
__sbit __at (0xD4) RS1 ;
__sbit __at (0xD5) F0 ;
__sbit __at (0xD6) AC ;
__sbit __at (0xD7) CY ;
/* BIT definitions for bits that are not directly accessible */
/* PCON bits */
#define IDL 0x01
#define PD 0x02
#define GF0 0x04
#define GF1 0x08
#define SMOD 0x80
/* TMOD bits */
#define T0_M0 0x01
#define T0_M1 0x02
#define T0_CT 0x04
#define T0_GATE 0x08
#define T1_M0 0x10
#define T1_M1 0x20
#define T1_CT 0x40
#define T1_GATE 0x80
#define T0_MASK 0x0F
#define T1_MASK 0xF0
/* Interrupt numbers: address = (number * 8) + 3 */
#define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
#define TF0_VECTOR 1 /* 0x0b timer 0 */
#define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
#define TF1_VECTOR 3 /* 0x1b timer 1 */
#define SI0_VECTOR 4 /* 0x23 serial port 0 */
#endif

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/*-------------------------------------------------------------------------
8052.h: Register Declarations for the Intel 8052 Processor
Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef REG8052_H
#define REG8052_H
#include <8051.h> /* load definitions for the 8051 core */
#ifdef REG8051_H
#undef REG8051_H
#endif
/* define 8052 specific registers only */
/* T2CON */
__sfr __at (0xC8) T2CON ;
/* RCAP2 L & H */
__sfr __at (0xCA) RCAP2L ;
__sfr __at (0xCB) RCAP2H ;
__sfr __at (0xCC) TL2 ;
__sfr __at (0xCD) TH2 ;
/* IE */
__sbit __at (0xAD) ET2 ; /* Enable timer2 interrupt */
/* IP */
__sbit __at (0xBD) PT2 ; /* T2 interrupt priority bit */
/* T2CON bits */
__sbit __at (0xC8) T2CON_0 ;
__sbit __at (0xC9) T2CON_1 ;
__sbit __at (0xCA) T2CON_2 ;
__sbit __at (0xCB) T2CON_3 ;
__sbit __at (0xCC) T2CON_4 ;
__sbit __at (0xCD) T2CON_5 ;
__sbit __at (0xCE) T2CON_6 ;
__sbit __at (0xCF) T2CON_7 ;
__sbit __at (0xC8) CP_RL2 ;
__sbit __at (0xC9) C_T2 ;
__sbit __at (0xCA) TR2 ;
__sbit __at (0xCB) EXEN2 ;
__sbit __at (0xCC) TCLK ;
__sbit __at (0xCD) RCLK ;
__sbit __at (0xCE) EXF2 ;
__sbit __at (0xCF) TF2 ;
#endif

384
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/ADuC84x.h Normal file
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/*-------------------------------------------------------------------------
ADuC84x.h: Register Declarations for Analog Devices
ADuC841/ADuC842/ADuC843 (Based on datasheet Rev 0, 11/2003 )
Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef REG_ADUC84X_H
#define REG_ADUC84X_H
#include <compiler.h>
SFR(CFG841, 0xAF); // ADuC841 Configuration SFR.
SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR.
//For the two SFRs above these are the bits. Warning: some are different for
//the ADuC841 and ADuC842/ADuC843. Check the datasheet!
#define EPM2 0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2.
#define EPM1 0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1.
#define EPM0 0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0.
#define EXSP 0x80 // Extended SP Enable.
#define PWPO 0x40 // PWM Pin Out Selection.
#define DBUF 0x20 // DAC Output Buffer.
#define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4.
#define MSPI 0x02 // Set to 1 by the user to move the SPI functionality of.
#define XRAMEN 0x01 // XRAM Enable Bit.
SFR(SP, 0x81); // Stack Pointer.
SFR(SPH, 0xB7); // Stack pointer high.
SFR(DPL, 0x82); // Data Pointer Low.
SFR(DPH, 0x83); // Data Pointer High.
SFR(DPP, 0x84); // Data Pointer Page Byte.
SFR(DPCON, 0xA7); // Data Pointer Control SFR.
SFR(PCON, 0x87); // Power Control.
#define SMOD 0x80 //Double UART Baud Rate.
#define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable.
#define INT0PD 0x20 //INT0 Power-Down Interrupt Enable.
#define ALEOFF 0x10 //Disable ALE Output.
#define GF1 0x08 //General-Purpose Flag Bit.
#define GF0 0x04 //General-Purpose Flag Bit.
#define PD 0x02 //Power-Down Mode Enable.
#define IDL 0x01 //Idle Mode Enable.
SFR(TCON, 0x88); // Timer/Counter Control.
SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
SFR(TMOD, 0x89); // Timer/Counter Mode Control.
#define GATE1 0x80 // External enable for timer 1.
#define C_T1 0x40 // Timer or counter select for timer 1.
#define M1_1 0x20 // Operation mode bit 1 for timer 1.
#define M0_1 0x10 // Operation mode bit 0 for timer 1.
#define GATE0 0x08 // External enable for timer 0.
#define C_T0 0x04 // Timer or counter select for timer 0.
#define M1_0 0x02 // Operation mode bit 1 for timer 0.
#define M0_0 0x01 // Operation mode bit 0 for timer 0.
SFR(TL0, 0x8A); // Timer 0 LSB.
SFR(TL1, 0x8B); // Timer 1 LSB.
SFR(TH0, 0x8C); // Timer 0 MSB.
SFR(TH1, 0x8D); // Timer 1 MSB.
SFR(P0, 0x80); // Port 0
SBIT(P0_0, 0x80, 0); // Port 0 bit 0.
SBIT(P0_1, 0x80, 1); // Port 0 bit 1.
SBIT(P0_2, 0x80, 2); // Port 0 bit 2.
SBIT(P0_3, 0x80, 3); // Port 0 bit 3.
SBIT(P0_4, 0x80, 4); // Port 0 bit 4.
SBIT(P0_5, 0x80, 5); // Port 0 bit 5.
SBIT(P0_6, 0x80, 6); // Port 0 bit 6.
SBIT(P0_7, 0x80, 7); // Port 0 bit 7.
SFR(P1, 0x90); // Port 1
SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
// Alternate names
SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2.
SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
SFR(P2, 0xA0); // Port 2
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.
SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.
SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.
SFR(P3, 0xB0); // Port 3
SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
// Alternate names.
SBIT(RXD, 0xB0, 0);
SBIT(TXD, 0xB0, 1);
SBIT(INT0, 0xB0, 2);
SBIT(INT1, 0xB0, 3);
SBIT(T0, 0xB0, 4);
SBIT(T1, 0xB0, 5);
SBIT(WR, 0xB0, 6);
SBIT(RD, 0xB0, 7);
SFR(I2CADD, 0x9B); // I2C Address Register 1.
SFR(I2CADD1, 0x91); // I2C Address Register 2.
SFR(I2CADD2, 0x92); // I2C Address Register 3.
SFR(I2CADD3, 0x93); // I2C Address Register 4.
SFR(I2CDAT, 0x9A); // I2C Data Register.
SFR(SCON, 0x98); // Serial Port Control.
SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
SBIT(REN, 0x98, 4); // Enables serial reception.
SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
SBIT(TI, 0x98, 1); // Transmit interrupt flag.
SBIT(RI, 0x98, 0); // Receive interrupt flag.
SFR(SBUF, 0x99); // Serial Data Buffer.
//For these two, you may want to check page 68 of the datasheet...
SFR(T3FD, 0x9D); // Fractional divider ratio.
SFR(T3CON, 0x9E); // T3CON is the baud rate control SFR, allowing Timer 3 to be
// used to set up the UART baud rate, and setting up the binary
// divider (DIV).
#define T3BAUDEN 0x80 // T3 UART BAUD Enable.
#define DIV2 0x04 // Binary Divider Factor bit 3.
#define DIV1 0x02 // Binary Divider Factor bit 2.
#define DIV0 0x01 // Binary Divider Factor bit 1.
SFR(TIMECON, 0xA1); // TIC Control Register.
#define TFH 0x40 // Twenty-Four Hour Select Bit.
#define ITS1 0x20 // Interval Timebase Selection Bit 1.
#define ITS0 0x10 // Interval Timebase Selection Bit 1.
#define STI 0x08 // Single Time Interval Bit.
#define TII 0x04 // TIC Interrupt Bit.
#define TIEN 0x02 // Time Interval Enable Bit.
#define TCEN 0x01 // Time Clock Enable Bit.
SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register.
SFR(SEC, 0xA3); // Seconds Time Register.
SFR(MIN, 0xA4); // Minutes Time Register.
SFR(HOUR, 0xA5); // Hours Time Register.
SFR(INTVAL, 0xA6); // User Time Interval Select Register.
SFR(IE, 0xA8); // Interrupt Enable.
SBIT(EA, 0xA8, 7); // Global Interrupt Enable.
SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable.
SBIT(ET2, 0xA8, 5); // Timer 2 Interrupt Enable.
SBIT(ES, 0xA8, 4); // Serial Interrupt Enable.
SBIT(ET1, 0xA8, 3); // Timer 1 Interrupt Enable.
SBIT(EX1, 0xA8, 2); // External 1 Interrupt Enable.
SBIT(ET0, 0xA8, 1); // Timer 0 Interrupt Enable.
SBIT(EX0, 0xA8, 0); // External 0 Interrupt Enable.
SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register
#define PTI 0x40 // Priority for time interval interrupt.
#define PPSM 0x20 // Priority for power supply monitor interrupt.
#define PSI2 0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP???
#define ETI 0x04 // Enable time interval counter interrupts.
#define EPSMI 0x02 // Enable power supply monitor interrupts.
#define ESI 0x01 // Enable SPI or I2C serial port interrupts.
SFR(PWMCON, 0xAE); //PWM control.
#define SNGL 0x80 // Turns off PMW output at P2.6 or P3.4.
#define MD2 0x40 // PWM Mode Bit 2.
#define MD1 0x20 // PWM Mode Bit 2.
#define MD0 0x10 // PWM Mode Bit 2.
#define CDIV1 0x08 // PWM Clock Divider bit 1.
#define CDIV0 0x04 // PWM Clock Divider bit 1.
#define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???)
#define CSEL0 0x01 // PWM Clock Select bit 0.
SFR(PWM0L, 0xB1); // PWM 0 duty cycle low.
SFR(PWM0H, 0xB2); // PWM 0 duty cycle high.
SFR(PWM1L, 0xB3); // PWM 1 duty cycle low.
SFR(PWM1H, 0xB4); // PWM 1 duty cycle high.
SFR(IP, 0xB8); // Interrupt Priority Reg.
SBIT(PSI, 0xB8, 7); // Priority for SPI/I2C interrupt.
SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit.
SBIT(PT2, 0xB8, 5); // Timer 2 interrupt priority bit.
SBIT(PS, 0xB8, 4); // Serial Port interrupt priority bit.
SBIT(PT1, 0xB8, 3); // Timer 1 interrupt priority bit.
SBIT(PX1, 0xB8, 2); // External interrupt 1 priority bit.
SBIT(PT0, 0xB8, 1); // Timer 0 interrupt priority bit.
SBIT(PX0, 0xB8, 0); // External interrupt 0 priority bit.
SFR(ECON, 0xB9); // Flash/EE Memory Control SFR.
SFR(EDATA1, 0xBC); // EE page data byte 1.
SFR(EDATA2, 0xBD); // EE page data byte 2.
SFR(EDATA3, 0xBE); // EE page data byte 3.
SFR(EDATA4, 0xBF); // EE page data byte 4.
SFR(EADRL, 0xC6); // EE address low.
SFR(EADRH, 0xC7); // EE address high.
SFR(WDCON, 0xC0); //Watchdog Timer Control Register.
SBIT(PRE3, 0xc0, 7); // Timeout period bit 4.
SBIT(PRE2, 0xc0, 6); // Timeout period bit 3.
SBIT(PRE1, 0xc0, 5); // Timeout period bit 2.
SBIT(PRE0, 0xc0, 4); // Timeout period bit 1.
SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit.
SBIT(WDS, 0xc0, 2); // Watchdog Status Bit.
SBIT(WDE, 0xc0, 1); // Watchdog Enable Bit.
SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit.
SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet.
SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
SBIT(RCLK, 0xC8, 5); // Receive clock flag.
SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
SFR(TL2, 0xCC); // Timer 2 LSB.
SFR(TH2, 0xCD); // Timer 2 MSB.
SFR(PSW, 0xD0); // Program Status Word.
SBIT(CY, 0xD0, 7); // Carry Flag.
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
SBIT(F0, 0xD0, 5); // User-Defined Flag.
SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
SBIT(OV, 0xD0, 2); // Overflow Flag.
SBIT(F1, 0xD0, 1); // User-Defined Flag.
SBIT(P, 0xD0, 0); // Parity Flag.
SFR(DMAL, 0xD2); // DMA mode address pointer low.
SFR(DMAH, 0xD3); // DMA mode address pointer high.
SFR(DMAP, 0xD4); // DMA mode address pointer page. (?)
SFR(PLLCON, 0xD7); // PLL Control Register.
SFR(PSMCON, 0xDF); // Power supply monitor.
#define CMPD 0x40 // DVDD Comparator Bit.
#define PSMI 0x20 // Power Supply Monitor Interrupt Bit.
#define TPD1 0x10 // DVDD Trip Point Selection Bit 2.
#define TPD0 0x08 // DVDD Trip Point Selection Bit 1.
#define PSMEN 0x01 // Power Supply Monitor Enable Bit.
SFR(ACC, 0xE0); // Accumulator
SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
SFR(I2CCON, 0xE8); // I2C Control Register
// Master mode
SBIT(MDO, 0xE8, 7); // I2C Software Master Data Output Bit.
SBIT(MDE, 0xE8, 6); // I2C Software Master Data Output Enable Bit.
SBIT(MCO, 0xE8, 5); // I2C Software Master Clock Output Bit.
SBIT(MDI, 0xE8, 4); // I2C Software Master Data Input Bit.
// Slave mode
SBIT(I2CSI, 0xE8, 7); // I2C Stop Interrupt Enable Bit.
SBIT(I2CGC, 0xE8, 6); // I2C General Call Status Bit.
SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2.
SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1.
SBIT(I2CM, 0xE8, 3); // I2C Master/Slave Mode Bit.
SBIT(I2CRS, 0xE8, 2); // I2C Reset Bit.
SBIT(I2CTX, 0xE8, 1); // I2C Direction Transfer Bit.
SBIT(I2CI, 0xE8, 0); // I2C Interrupt Bit.
SFR(B, 0xF0); // B Register
SBIT(B_0, 0xF0, 0); // Register B bit 0.
SBIT(B_1, 0xF0, 1); // Register B bit 1.
SBIT(B_2, 0xF0, 2); // Register B bit 2.
SBIT(B_3, 0xF0, 3); // Register B bit 3.
SBIT(B_4, 0xF0, 4); // Register B bit 4.
SBIT(B_5, 0xF0, 5); // Register B bit 5.
SBIT(B_6, 0xF0, 6); // Register B bit 6.
SBIT(B_7, 0xF0, 7); // Register B bit 7.
SFR(ADCCON1, 0xEF); //ADC Control SFR 1
//WARNING: bit 7 is named MD1 in the datasheet, but that name is already used.
#define MD 0x80 // The mode bit selects the active operating mode of the ADC.
#define EXT_REF 0x40 // Set by the user to select an external reference.
#define CK1 0x20 // The ADC clock divide bit 1.
#define CK0 0x10 // The ADC clock divide bit 0.
#define AQ1 0x08 // ADC acquisition select bit 1.
#define AQ0 0x04 // ADC acquisition select bit 0.
#define T2C 0x02 // The Timer 2 conversion bit.
#define EXC 0x01 // The external trigger enable bit.
SFR(ADCCON2, 0xD8); // ADC Control SFR 2.
SBIT(ADCI, 0xD8, 7); // ADC Interrupt Bit.
SBIT(DMA, 0xD8, 6); // DMA Mode Enable Bit.
SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit.
SBIT(SCONV, 0xD8, 4); // Single Conversion Bit.
SBIT(CS3, 0xD8, 3); // Channel Selection Bit 4.
SBIT(CS2, 0xD8, 2); // Channel Selection Bit 3.
SBIT(CS1, 0xD8, 1); // Channel Selection Bit 2.
SBIT(CS0, 0xD8, 0); // Channel Selection Bit 1.
SFR(ADCCON3, 0xF5); //ADC Control SFR 3
#define BUSY 0x80 // ADC Busy Status Bit.
#define AVGS1 0x20 // Number of Average Selection Bit 2.
#define AVGS0 0x10 // Number of Average Selection Bit 1.
#define TYPICAL 0x02 // Calibration Type Select Bit.
#define SCAL 0x01 // Start Calibration Cycle Bit.
SFR(ADCDATAL, 0xD9); // ADC Result byte low.
SFR(ADCDATAH, 0xDA); // ADC Result byte high. WARNING: bits 4 to 7 are the ADC channel!
SFR(ADCOFSL, 0xF1); // Offset calibration coefficient byte (low).
SFR(ADCOFSH, 0xF2); // Offset calibration coefficient byte (high).
SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low).
SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high).
SFR(SPIDAT, 0xF7); // SPI Data Register.
SFR(SPICON, 0xF8); // SPI Control Register.
SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit.
SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit.
SBIT(SPE, 0xF8, 5); // SPI Interface Enable Bit.
SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit.
SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit.
SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit.
SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2.
SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1.
SFR(DAC0L, 0xF9); // DAC0 Data Low Byte.
SFR(DAC0H, 0xFA); // DAC0 Data High Byte.
SFR(DAC1L, 0xFB); // DAC1 Data Low Byte.
SFR(DAC1H, 0xFC); // DAC1 Data High Byte.
SFR(DACCON, 0xFD); // DAC Control Register.
#define MODE 0x80 // 8/12 bit selection.
#define RNG1 0x40 // DAC1 Range Select Bit.
#define RNG0 0x20 // DAC0 Range Select Bit.
#define CLR1 0x10 // DAC1 Clear Bit.
#define CLR0 0x08 // DAC0 Clear Bit.
#define SYNC 0x04 // DAC0/1 Update Synchronization Bit.
#define PD1 0x02 // DAC1 Power-Down Bit.
#define PD0 0x01 // DAC0 Power-Down Bit.
#endif //REG_ADUC84X_H

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/*-------------------------------------------------------------------------
Register Declarations for the Atmel AT89C513xA Processor Range
Copyright (C) 2010 - Anirban Brahmachari, a.brahmachari@gmail.com
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef AT89C5131AUM_H
#define AT89C5131AUM_H
#include <compiler.h>
SFR(P0, 0x80); // Port 0
SBIT(P0_0, 0x80, 0); // Port 0 bit 0
SBIT(P0_1, 0x80, 1); // Port 0 bit 1
SBIT(P0_2, 0x80, 2); // Port 0 bit 2
SBIT(P0_3, 0x80, 3); // Port 0 bit 3
SBIT(P0_4, 0x80, 4); // Port 0 bit 4
SBIT(P0_5, 0x80, 5); // Port 0 bit 5
SBIT(P0_6, 0x80, 6); // Port 0 bit 6
SBIT(P0_7, 0x80, 7); // Port 0 bit 7
SFR(SP, 0x81); // Stack Pointer ; LSB of SPX
SFR(DPL, 0x82); // Data Pointer Low Byte
SFR(DPH, 0x83); // Data Pointer High Byte
SFR(PCON, 0x87); // Power Mode Control
SFR(TCON, 0x88); // Timer Control
SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
SBIT(TR0, 0x88, 4); // Timer 0 Run Control
SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
SBIT(TR1, 0x88, 6); // Timer 1 Run Control
SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
SFR(TMOD, 0x89); // Timer Mode
SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
SFR(AUXR, 0x8E); // Auxiliary Register
SFR(CKCON0, 0x8F); // Clock Control 0
SFR(P1, 0x90); // Port 1
SBIT(P1_0, 0x90, 0); // Port 1 bit 0
SBIT(P1_1, 0x90, 1); // Port 1 bit 1
SBIT(P1_2, 0x90, 2); // Port 1 bit 2
SBIT(P1_3, 0x90, 3); // Port 1 bit 3
SBIT(P1_4, 0x90, 4); // Port 1 bit 4
SBIT(P1_5, 0x90, 5); // Port 1 bit 5
SBIT(P1_6, 0x90, 6); // Port 1 bit 6
SBIT(P1_7, 0x90, 7); // Port 1 bit 7
SFR(SSCON, 0x93); // Synchronous Serial Control
SFR(SSCS, 0x94); // Synchronous Serial Control-Status
SFR(SSDAT, 0x95); // Synchronous Serial Data
SFR(SSADR, 0x96); // Synchronous Serial Address
SFR(SCON, 0x98); // Serial Port 0 Control
SBIT(RI, 0x98, 0); // Receive Interrupt Flag
SBIT(TI, 0x98, 1); // Transmit Interrupt Flag
SBIT(RB8, 0x98, 2); // Ninth Receive Bit
SBIT(TB8, 0x98, 3); // Ninth Transmission Bit
SBIT(REN, 0x98, 4); // Receive Enable
SBIT(SM2, 0x98, 5); // Multiprocessor Communication Enable
SBIT(SM1, 0x98, 6); // Serial Port Mode 1
SBIT(SM0, 0x98, 7); // Serial Port Mode 0
SBIT(FE, 0x98, 7); // Framing Error
SFR(SBUF, 0x99); // Serial Port Data Buffer
SFR(BRL, 0x9A); // Baud Rate Reload
SFR(BDRCON, 0x9B); // Baud Rate Control
SFR(KBLS, 0x9C); // Keyboard Level Selector Register
SFR(KBE, 0x9D); // Keyboard Input Enable Register
SFR(KBF, 0x9E); // Keyboard Flag Register
SFR(P2, 0xA0); // Port 2
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
SFR(AUXR1, 0xA2); // Auxiliary Register 1
SFR(PLLCON, 0xA3); // PLL Control
SFR(PLLDIV, 0xA4); // PLL Divider
SFR(WDTRST, 0xA6); // Watchdog Timer Reset
SFR(WDTPRG, 0xA7); // Watchdog Timer Program
SFR(IE, 0xA8); // Interrupt Enable (traditional 8051 name)
SFR(IEN0, 0xA8); // Interrupt Enable Control 0
SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
SBIT(ES, 0xA8, 4); // Enable Serial Port Interrupt
SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
SBIT(EC, 0xA8, 6); // Enable PCA Interrupt
SBIT(EA, 0xA8, 7); // Global Interrupt Enable
SFR(SADDR, 0xA9); // Slave Address
SFR(CKCON1, 0xAF); // Clock Control 1
SFR(P3, 0xB0); // Port 3
SBIT(P3_0, 0xB0, 0); // Port 3 bit 0
SBIT(P3_1, 0xB0, 1); // Port 3 bit 1
SBIT(P3_2, 0xB0, 2); // Port 3 bit 2
SBIT(P3_3, 0xB0, 3); // Port 3 bit 3
SBIT(P3_4, 0xB0, 4); // Port 3 bit 4
SBIT(P3_5, 0xB0, 5); // Port 3 bit 5
SBIT(P3_6, 0xB0, 6); // Port 3 bit 6
SBIT(P3_7, 0xB0, 7); // Port 3 bit 7
SFR(IEN1, 0xB1); // Interrupt Enable Control 1
SFR(IPL1, 0xB2); // Interrupt Priority Control Low 1
SFR(IPH1, 0xB3); // Interrupt Priority Control High 1
SFR(IPH0, 0xB7); // Interrupt Priority Control High 0
SFR(IPL0, 0xB8); // Interrupt Priority Control Low 0
SBIT(PX0L, 0xB8, 0); // External interrupt 0 Priority bit
SBIT(PT0L, 0xB8, 1); // Timer 0 overflow interrupt Priority bit
SBIT(PX1L, 0xB8, 2); // External interrupt 1 Priority bit
SBIT(PT1L, 0xB8, 3); // Timer 1 overflow interrupt Priority bit
SBIT(PSL, 0xB8, 4); // Serial port Priority bit
SBIT(PT2L, 0xB8, 5); // Timer 2 overflow interrupt Priority bit
SBIT(PPCL, 0xB8, 6); // PCA interrupt Priority bit
SFR(SADEN, 0xB9); // Slave Address Mask
SFR16E(UFNUM, 0xBBBA); // USB Frame Number Word
SFR(UFNUML, 0xBA); // USB Frame Number Low
SFR(UFNUMH, 0xBB); // USB Frame Number High
SFR(USBCON, 0xBC); // USB Global Control
SFR(USBINT, 0xBD); // USB Global Interrupt
SFR(USBIEN, 0xBE); // USB Global Interrupt Enable
SFR(P4, 0xC0); // Port 4
SBIT(P4_0, 0xC0, 0); // Port 4 bit 0
SBIT(P4_1, 0xC0, 1); // Port 4 bit 1
SFR(UEPIEN, 0xC2); // USB Endpoint Interrupt Enable
SFR(SPCON, 0xC3); // Serial Peripheral Control
SFR(SPSTA, 0xC4); // Serial Peripheral Status-Control
SFR(SPDAT, 0xC5); // Serial Peripheral Data
SFR(USBADDR, 0xC6); // USB Address
SFR(UEPNUM, 0xC7); // USB Endpoint Number
SFR(T2CON, 0xC8); // Timer 2 Control
SBIT(CP_RL2, 0xC8, 0); // Timer 2 Capture/Reload bit
SBIT(C_T2, 0xC8, 1); // Timer/Counter 2 select bit
SBIT(TR2, 0xC8, 2); // Timer 2 Run control bit
SBIT(EXEN2, 0xC8, 3); // Timer 2 External Enable bit
SBIT(TCLK, 0xC8, 4); // Transmit Clock bit
SBIT(RCLK, 0xC8, 5); // Receive Clock bit
SBIT(EXF2, 0xC8, 6); // Timer 2 External Flag
SBIT(TF2, 0xC8, 7); // Timer 2 overflow Flag
SFR(T2MOD, 0xC9); // Timer 2 Mode
SFR16E(RCAP2, 0xCBCA); // Timer/Counter 2 Reload/Capture Word
SFR(RCAP2L, 0xCA); // Timer/Counter 2 Reload/Capture Low byte
SFR(RCAP2H, 0xCB); // Timer/Counter 2 Reload/Capture High byte
SFR16E(TMR2, 0xCDCC); // Timer/Counter 2 Word
SFR(TL2, 0xCC); // Timer/Counter 2 Low Byte
SFR(TH2, 0xCD); // Timer/Counter 2 High Byte
SFR(UEPSTAX, 0xCE); // USB Endpoint X Status
SFR(UEPDATX, 0xCF); // USB Endpoint X FIFO Data
SFR(PSW, 0xD0); // Program Status Word
SBIT(P, 0xD0, 0); // Parity Flag
SBIT(F1, 0xD0, 1); // User-Defined Flag
SBIT(OV, 0xD0, 2); // Overflow Flag
SBIT(RS0, 0xD0, 3); // Register Bank Select 0
SBIT(RS1, 0xD0, 4); // Register Bank Select 1
SBIT(F0, 0xD0, 5); // User-Defined Flag
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
SBIT(CY, 0xD0, 7); // Carry Flag
SFR(FCON, 0xD1); // Flash Control
SFR(EECON, 0xD2); // EEPROM Contol
SFR(UEPCONX, 0xD4); // USB Endpoint X Control
SFR(UEPRST, 0xD5); // USB Endpoint Reset
SFR(CCON, 0xD8); // PCA Timer/Counter Control
SBIT(CCF0, 0xD8,0); // PCA Module 0 interrupt flag
SBIT(CCF1, 0xD8,1); // PCA Module 1 interrupt flag
SBIT(CCF2, 0xD8,2); // PCA Module 2 interrupt flag
SBIT(CCF3, 0xD8,3); // PCA Module 3 interrupt flag
SBIT(CCF4, 0xD8,4); // PCA Module 4 interrupt flag
SBIT(CR, 0xD8,6); // PCA Counter Run control bit
SBIT(CF, 0xD8,7); // PCA Counter Overflow flag
SFR(CMOD, 0xD9); // PCA Timer/Counter Mode
SFR(CCAPM0, 0xDA); // PCA Timer/Counter 0 Mode
SFR(CCAPM1, 0xDB); // PCA Timer/Counter 1 Mode
SFR(CCAPM2, 0xDC); // PCA Timer/Counter 2 Mode
SFR(CCAPM3, 0xDD); // PCA Timer/Counter 3 Mode
SFR(CCAPM4, 0xDE); // PCA Timer/Counter 4 Mode
SFR(ACC, 0xE0); // Accumulator
SFR16E(UBYCTX, 0xE3E2); // USB Byte Counter Word
SFR(UBYCTLX, 0xE2); // USB Byte Counter Low
SFR(UBYCTHX, 0xE3); // USB Byte Counter High
SFR16E(PCA, 0xF9E9); // PCA Timer/Counter Word
SFR(CL, 0xE9); // PCA Timer/Counter Low byte
SFR(CH, 0xF9); // PCA Timer/Counter High byte
SFR16E(CCAP0, 0xFAEA); // PCA Compare Capture Module 0 Word
SFR(CCAP0L, 0xEA); // PCA Compare Capture Module 0 Low byte
SFR(CCAP0H, 0xFA); // PCA Compare Capture Module 0 High byte
SFR16E(CCAP1, 0xFBEB); // PCA Compare Capture Module 1 Word
SFR(CCAP1L, 0xEB); // PCA Compare Capture Module 1 Low byte
SFR(CCAP1H, 0xFB); // PCA Compare Capture Module 1 High byte
SFR16E(CCAP2, 0xFCEC); // PCA Compare Capture Module 2 Word
SFR(CCAP2L, 0xEC); // PCA Compare Capture Module 2 Low byte
SFR(CCAP2H, 0xFC); // PCA Compare Capture Module 2 High byte
SFR16E(CCAP3, 0xFDED); // PCA Compare Capture Module 3 Word
SFR(CCAP3L, 0xED); // PCA Compare Capture Module 3 Low byte
SFR(CCAP3H, 0xFD); // PCA Compare Capture Module 3 High byte
SFR16E(CCAP4, 0xFEEE); // PCA Compare Capture Module 4 Word
SFR(CCAP4L, 0xEE); // PCA Compare Capture Module 4 Low byte
SFR(CCAP4H, 0xFE); // PCA Compare Capture Module 4 High byte
SFR(B, 0xF0); // B Register
SFR(LEDCON, 0xF1); // LED Control
SFR(UEPINT, 0xF8); // USB Endpoint Interrupt
SBIT(EP0INT, 0xF8,0); // Endpoint 0 Interrupt
SBIT(EP1INT, 0xF8,1); // Endpoint 1 Interrupt
SBIT(EP2INT, 0xF8,2); // Endpoint 2 Interrupt
SBIT(EP3INT, 0xF8,3); // Endpoint 3 Interrupt
SBIT(EP4INT, 0xF8,4); // Endpoint 4 Interrupt
SBIT(EP5INT, 0xF8,5); // Endpoint 5 Interrupt
SBIT(EP6INT, 0xF8,6); // Endpoint 6 Interrupt
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
/* Interrupts */
#define INT_RESET 0 // Reset
#define INT_EXT0 1 // External Interrupt 0
#define INT_TIMER0 2 // Timer0 Overflow
#define INT_EXT1 3 // External Interrupt 1
#define INT_TIMER1 4 // Timer1 Overflow
#define INT_UART0 5 // Serial Port 0
#define INT_TIMER2 6 // Timer2 Overflow
#define INT_PCA 7 // Programmable Counter Array
#define INT_KEYBOARD 8 // Keyboard on P1
#define INT_TWI 9 // Two Wire Interface
#define INT_SPI 10 // Serial Peripheral Interface
// 11 Reserved
// 12 Reserved
// 13 Reserved
#define INT_USB 14 // USB events
// 15 Reserved
#endif

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/*---------------------------------------------------------------------------
C8051F000.h - Register Declarations for the Cygnal/SiLabs C8051F000-F017
Processor Range
Copyright (C) 2003, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F000_H
#define C8051F000_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xAD) PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
__sfr __at (0xD5) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
__sfr __at (0xD6) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
__sfr __at (0xD7) DAC1CN ; /* DAC 1 CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
__sfr16 __at (0xD6D5) DAC1 ; /* DAC 1 REGISTER WORD */
__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x87) P0_7 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x80) P0_0 ;
/* TCON 0x88 */
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
/* P1 0x90 */
__sbit __at (0x97) P1_7 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x90) P1_0 ;
/* SCON 0x98 */
__sbit __at (0x9F) SM0 ; /* SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9E) SM1 ; /* SERIAL MODE CONTROL BIT 1 */
__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9C) REN ; /* RECEIVE ENABLE */
__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
__sbit __at (0x99) TI ; /* TRANSMIT INTERRUPT FLAG */
__sbit __at (0x98) RI ; /* RECEIVE INTERRUPT FLAG */
/* P2 0xA0 */
__sbit __at (0xA7) P2_7 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA0) P2_0 ;
/* IE 0xA8 */
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
/* P3 0xB0 */
__sbit __at (0xB7) P3_7 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB0) P3_0 ;
/* IP 0xB8 */
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
/* T2CON 0xC8 */
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
/* PSW 0xD0 */
__sbit __at (0xD7) CY ; /* CARRY FLAG */
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
/* PCA0CN 0xD8H */
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
/* ADC0CN 0xE8H */
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
/* SPI0CN 0xF8H */
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define TF3 0x80 /* TMR3CN */
#define CPFIF 0x10 /* CPTnCN */
#define CPRIF 0x20 /* CPTnCN */
#define CPOUT 0x40 /* CPTnCN */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#endif

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/*---------------------------------------------------------------------------
C8051F018.h - Register Declarations for the Cygnal/SiLabs C8051F018-F019
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F018_H
#define C8051F018_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xAD) PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x87) P0_7 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x80) P0_0 ;
/* TCON 0x88 */
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
/* P1 0x90 */
__sbit __at (0x97) P1_7 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x90) P1_0 ;
/* SCON 0x98 */
__sbit __at (0x9F) SM0 ; /* SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9E) SM1 ; /* SERIAL MODE CONTROL BIT 1 */
__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9C) REN ; /* RECEIVE ENABLE */
__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
__sbit __at (0x99) TI ; /* TRANSMIT INTERRUPT FLAG */
__sbit __at (0x98) RI ; /* RECEIVE INTERRUPT FLAG */
/* P2 0xA0 */
__sbit __at (0xA7) P2_7 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA0) P2_0 ;
/* IE 0xA8 */
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
/* P3 0xB0 */
__sbit __at (0xB7) P3_7 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB0) P3_0 ;
/* IP 0xB8 */
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
/* T2CON 0xC8 */
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
/* PSW 0xD0 */
__sbit __at (0xD7) CY ; /* CARRY FLAG */
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
/* PCA0CN 0xD8H */
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
/* ADC0CN 0xE8H */
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
/* SPI0CN 0xF8H */
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define TF3 0x80 /* TMR3CN */
#define CPFIF 0x10 /* CPTnCN */
#define CPRIF 0x20 /* CPTnCN */
#define CPOUT 0x40 /* CPTnCN */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#endif

378
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/C8051F020.h Normal file
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@@ -0,0 +1,378 @@
/*-------------------------------------------------------------------------
C8051F020.h - Register Declarations for the Cygnal/SiLabs C8051F02x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F020_H
#define C8051F020_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x84) P4 ; /* PORT 4 */
__sfr __at (0x85) P5 ; /* PORT 5 */
__sfr __at (0x86) P6 ; /* PORT 6 */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) P7 ; /* PORT 7 */
__sfr __at (0x98) SCON ; /* UART0 CONTROL */
__sfr __at (0x98) SCON0 ; /* UART0 CONTROL */
__sfr __at (0x99) SBUF ; /* UART0 BUFFER */
__sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
__sfr __at (0x9C) ADC1 ; /* ADC 1 DATA */
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) EMI0TC ; /* External Memory Timing Control */
__sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */
__sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) SADDR0 ; /* UART0 Slave Address */
__sfr __at (0xAA) ADC1CN ; /* ADC 1 CONTROL */
__sfr __at (0xAB) ADC1CF ; /* ADC 1 CONFIGURATION */
__sfr __at (0xAC) AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */
__sfr __at (0xAD) P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
__sfr __at (0xAE) SADEN1 ; /* UART1 Slave Address Enable */
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB5) P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) SADEN0 ; /* UART0 Slave Address Enable */
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) P1MDIN ; /* PORT 1 Input Mode */
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC9) T4CON ; /* TIMER 4 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
__sfr __at (0xD5) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
__sfr __at (0xD6) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
__sfr __at (0xD7) DAC1CN ; /* DAC 1 CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
__sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
__sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
__sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
__sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
__sfr __at (0xE4) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xE5) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
__sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
__sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
__sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
__sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
__sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) SCON1 ; /* UART1 CONTROL */
__sfr __at (0xF2) SBUF1 ; /* UART1 DATA */
__sfr __at (0xF3) SADDR1 ; /* UART1 Slave Address */
__sfr __at (0xF4) TL4 ; /* TIMER 4 DATA - LOW BYTE */
__sfr __at (0xF5) TH4 ; /* TIMER 4 DATA - HIGH BYTE */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
__sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
__sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
__sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
__sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
__sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
__sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xF5F4) TMR4 ; /* TIMER 4 COUNTER */
__sfr16 __at (0xE5E4) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD */
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
__sfr16 __at (0xD6D5) DAC1 ; /* DAC 1 REGISTER WORD */
__sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9E) SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
__sbit __at (0x9E) SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
__sbit __at (0xBC) PS0 ; /* SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
/* T2CON 0xC8 */
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* CARRY FLAG */
/* PCA0CN 0xD8H */
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* ADC0CN 0xE8H */
__sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
__sbit __at (0xE8) AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
__sbit __at (0xE9) ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
__sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
__sbit __at (0xEA) AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
__sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
__sbit __at (0xEB) AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
__sbit __at (0xEC) ADBUSY ; /* ADC 0 BUSY FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
__sbit __at (0xED) ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
__sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
__sbit __at (0xEE) ADCTM ; /* ADC 0 TRACK MODE */
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
__sbit __at (0xEF) ADCEN ; /* ADC 0 ENABLE */
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
/* SPI0CN 0xF8H */
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
__sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
__sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
__sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define PCON_SMOD0 0x80 /* PCON */
#define TF3 0x80 /* TMR3CN */
#define CPFIF 0x10 /* CPTnCN */
#define CPRIF 0x20 /* CPTnCN */
#define CPOUT 0x40 /* CPTnCN */
#define TR4 0x04 /* T4CON */
#define TF4 0x80 /* T4CON */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define RI1 0x01 /* SCON1 */
#define TI1 0x02 /* SCON1 */
#define RB81 0x04 /* SCON1 */
#define TB81 0x08 /* SCON1 */
#define REN1 0x10 /* SCON1 */
#define SM21 0x20 /* SCON1 */
#define SM11 0x40 /* SCON1 */
#define SM01 0x80 /* SCON1 */
#endif

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OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/C8051F040.h Normal file
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/*-------------------------------------------------------------------------
C8051F040.h - Register Declarations for the Cygnal/SiLabs C8051F04x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F040_H
#define C8051F040_H
#include <compiler.h>
/* BYTE Registers */
/* All Pages */
SFR(P0, 0x80); /* PORT 0 */
SFR(SP, 0x81); /* STACK POINTER */
SFR(DPL, 0x82); /* DATA POINTER - LOW BYTE */
SFR(DPH, 0x83); /* DATA POINTER - HIGH BYTE */
SFR(SFRPAGE, 0x84); /* SFR PAGE SELECT */
SFR(SFRNEXT, 0x85); /* SFR STACK NEXT PAGE */
SFR(SFRLAST, 0x86); /* SFR STACK LAST PAGE */
SFR(PCON, 0x87); /* POWER CONTROL */
SFR(P1, 0x90); /* PORT 1 */
SFR(P2, 0xA0); /* PORT 2 */
SFR(IE, 0xA8); /* INTERRUPT ENABLE */
SFR(P3, 0xB0); /* PORT 3 */
SFR(IP, 0xB8); /* INTERRUPT PRIORITY */
SFR(PSW, 0xD0); /* PROGRAM STATUS WORD */
SFR(ACC, 0xE0); /* ACCUMULATOR */
SFR(EIE1, 0xE6); /* EXTERNAL INTERRUPT ENABLE 1 */
SFR(EIE2, 0xE7); /* EXTERNAL INTERRUPT ENABLE 2 */
SFR(B, 0xF0); /* B REGISTER */
SFR(EIP1, 0xF6); /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
SFR(EIP2, 0xF7); /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
SFR(WDTCN, 0xFF); /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
SFR(TCON, 0x88); /* TIMER CONTROL */
SFR(TMOD, 0x89); /* TIMER MODE */
SFR(TL0, 0x8A); /* TIMER 0 - LOW BYTE */
SFR(TL1, 0x8B); /* TIMER 1 - LOW BYTE */
SFR(TH0, 0x8C); /* TIMER 0 - HIGH BYTE */
SFR(TH1, 0x8D); /* TIMER 1 - HIGH BYTE */
SFR(CKCON, 0x8E); /* TIMER 0/1 CLOCK CONTROL */
SFR(PSCTL, 0x8F); /* FLASH WRITE/ERASE CONTROL */
SFR(SSTA0, 0x91); /* UART 0 STATUS */
SFR(SCON0, 0x98); /* UART 0 CONTROL */
SFR(SCON, 0x98); /* UART 0 CONTROL */
SFR(SBUF0, 0x99); /* UART 0 BUFFER */
SFR(SBUF, 0x99); /* UART 0 BUFFER */
SFR(SPI0CFG, 0x9A); /* SPI 0 CONFIGURATION */
SFR(SPI0DAT, 0x9B); /* SPI 0 DATA */
SFR(SPI0CKR, 0x9D); /* SPI 0 CLOCK RATE CONTROL */
SFR(EMI0TC, 0xA1); /* EMIF TIMING CONTROL */
SFR(EMI0CN, 0xA2); /* EMIF CONTROL */
SFR(_XPAGE, 0xA2); /* XDATA/PDATA PAGE */
SFR(EMI0CF, 0xA3); /* EMIF CONFIGURATION */
SFR(SADDR0, 0xA9); /* UART 0 SLAVE ADDRESS */
SFR(FLSCL, 0xB7); /* FLASH SCALE */
SFR(SADEN0, 0xB9); /* UART 0 SLAVE ADDRESS MASK */
SFR(AMX0CF, 0xBA); /* ADC 0 MUX CONFIGURATION */
SFR(AMX0SL, 0xBB); /* ADC 0 MUX CHANNEL SELECTION */
SFR(ADC0CF, 0xBC); /* ADC 0 CONFIGURATION */
SFR(AMX0PRT, 0xBD); /* ADC 0 PORT 3 I/O PIN SELECT */
SFR(ADC0L, 0xBE); /* ADC 0 DATA - LOW BYTE */
SFR(ADC0H, 0xBF); /* ADC 0 DATA - HIGH BYTE */
SFR(SMB0CN, 0xC0); /* SMBUS 0 CONTROL */
SFR(SMB0STA, 0xC1); /* SMBUS 0 STATUS */
SFR(SMB0DAT, 0xC2); /* SMBUS 0 DATA */
SFR(SMB0ADR, 0xC3); /* SMBUS 0 SLAVE ADDRESS */
SFR(ADC0GTL, 0xC4); /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
SFR(ADC0GTH, 0xC5); /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
SFR(ADC0LTL, 0xC6); /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
SFR(ADC0LTH, 0xC7); /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
SFR(TMR2CN, 0xC8); /* TIMER 2 CONTROL */
SFR(TMR2CF, 0xC9); /* TIMER 2 CONFIGURATION */
SFR(RCAP2L, 0xCA); /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR(RCAP2H, 0xCB); /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR(TMR2L, 0xCC); /* TIMER 2 - LOW BYTE */
SFR(TL2, 0xCC); /* TIMER 2 - LOW BYTE */
SFR(TMR2H, 0xCD); /* TIMER 2 - HIGH BYTE */
SFR(TH2, 0xCD); /* TIMER 2 - HIGH BYTE */
SFR(SMB0CR, 0xCF); /* SMBUS 0 CLOCK RATE */
SFR(REF0CN, 0xD1); /* VOLTAGE REFERENCE 0 CONTROL */
SFR(DAC0L, 0xD2); /* DAC 0 REGISTER - LOW BYTE */
SFR(DAC0H, 0xD3); /* DAC 0 REGISTER - HIGH BYTE */
SFR(DAC0CN, 0xD4); /* DAC 0 CONTROL */
SFR(HVA0CN, 0xD6); /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL */
SFR(PCA0CN, 0xD8); /* PCA 0 COUNTER CONTROL */
SFR(PCA0MD, 0xD9); /* PCA 0 COUNTER MODE */
SFR(PCA0CPM0, 0xDA); /* PCA 0 MODULE 0 CONTROL */
SFR(PCA0CPM1, 0xDB); /* PCA 0 MODULE 1 CONTROL */
SFR(PCA0CPM2, 0xDC); /* PCA 0 MODULE 2 CONTROL */
SFR(PCA0CPM3, 0xDD); /* PCA 0 MODULE 3 CONTROL */
SFR(PCA0CPM4, 0xDE); /* PCA 0 MODULE 4 CONTROL */
SFR(PCA0CPM5, 0xDF); /* PCA 0 MODULE 5 CONTROL */
SFR(PCA0CPL5, 0xE1); /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH5, 0xE2); /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
SFR(ADC0CN, 0xE8); /* ADC 0 CONTROL */
SFR(PCA0CPL2, 0xE9); /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH2, 0xEA); /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
SFR(PCA0CPL3, 0xEB); /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH3, 0xEC); /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
SFR(PCA0CPL4, 0xED); /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH4, 0xEE); /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
SFR(RSTSRC, 0xEF); /* RESET SOURCE */
SFR(SPI0CN, 0xF8); /* SPI 0 CONTROL */
SFR(PCA0L, 0xF9); /* PCA 0 TIMER - LOW BYTE */
SFR(PCA0H, 0xFA); /* PCA 0 TIMER - HIGH BYTE */
SFR(PCA0CPL0, 0xFB); /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH0, 0xFC); /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
SFR(PCA0CPL1, 0xFD); /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH1, 0xFE); /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
SFR(CPT0CN, 0x88); /* COMPARATOR 0 CONTROL */
SFR(CPT0MD, 0x89); /* COMPARATOR 0 CONFIGURATION */
SFR(SCON1, 0x98); /* UART 1 CONTROL */
SFR(SBUF1, 0x99); /* UART 1 BUFFER */
SFR(CAN0STA, 0xC0); /* CAN 0 STATUS */
SFR(TMR3CN, 0xC8); /* TIMER 3 CONTROL */
SFR(TMR3CF, 0xC9); /* TIMER 3 CONFIGURATION */
SFR(RCAP3L, 0xCA); /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
SFR(RCAP3H, 0xCB); /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
SFR(TMR3L, 0xCC); /* TIMER 3 - LOW BYTE */
SFR(TMR3H, 0xCD); /* TIMER 3 - HIGH BYTE */
SFR(DAC1L, 0xD2); /* DAC 1 REGISTER - LOW BYTE */
SFR(DAC1H, 0xD3); /* DAC 1 REGISTER - HIGH BYTE */
SFR(DAC1CN, 0xD4); /* DAC 1 CONTROL */
SFR(CAN0DATL, 0xD8); /* CAN 0 DATA REGISTER LOW */
SFR(CAN0DATH, 0xD9); /* CAN 0 DATA REGISTER HIGH */
SFR(CAN0ADR, 0xDA); /* CAN 0 ADDRESS */
SFR(CAN0TST, 0xDB); /* CAN 0 TEST REGISTER */
SFR(CAN0CN, 0xF8); /* CAN 0 CONTROL */
/* Page 0x02 */
SFR(CPT1CN, 0x88); /* COMPARATOR 1 CONTROL */
SFR(CPT1MD, 0x89); /* COMPARATOR 1 CONFIGURATION */
SFR(AMX2CF, 0xBA); /* ADC 2 MUX CONFIGURATION */
SFR(AMX2SL, 0xBB); /* ADC 2 MUX CHANNEL SELECTION */
SFR(ADC2CF, 0xBC); /* ADC 2 CONFIGURATION */
SFR(ADC2, 0xBE); /* ADC 2 DATA */
SFR(ADC2GT, 0xC4); /* ADC 2 GREATER-THAN REGISTER */
SFR(ADC2LT, 0xC6); /* ADC 2 LESS-THAN REGISTER */
SFR(TMR4CN, 0xC8); /* TIMER 4 CONTROL */
SFR(TMR4CF, 0xC9); /* TIMER 4 CONFIGURATION */
SFR(RCAP4L, 0xCA); /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
SFR(RCAP4H, 0xCB); /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
SFR(TMR4L, 0xCC); /* TIMER 4 - LOW BYTE */
SFR(TMR4H, 0xCD); /* TIMER 4 - HIGH BYTE */
SFR(ADC2CN, 0xE8); /* ADC 2 CONTROL */
/* Page 0x03 */
SFR(CPT2CN, 0x88); /* COMPARATOR 2 CONTROL */
SFR(CPT2MD, 0x89); /* COMPARATOR 2 CONFIGURATION */
/* Page 0x0F */
SFR(OSCICN, 0x8A); /* INTERNAL OSCILLATOR CONTROL */
SFR(OSCICL, 0x8B); /* INTERNAL OSCILLATOR CALIBRATION */
SFR(OSCXCN, 0x8C); /* EXTERNAL OSCILLATOR CONTROL */
SFR(SFRPGCN, 0x96); /* SFR PAGE CONTROL */
SFR(CLKSEL, 0x97); /* SYSTEM CLOCK SELECT */
SFR(P4MDOUT, 0x9C); /* PORT 4 OUTPUT MODE */
SFR(P5MDOUT, 0x9D); /* PORT 5 OUTPUT MODE */
SFR(P6MDOUT, 0x9E); /* PORT 6 OUTPUT MODE */
SFR(P7MDOUT, 0x9F); /* PORT 7 OUTPUT MODE */
SFR(P0MDOUT, 0xA4); /* PORT 0 OUTPUT MODE */
SFR(P1MDOUT, 0xA5); /* PORT 1 OUTPUT MODE */
SFR(P2MDOUT, 0xA6); /* PORT 2 OUTPUT MODE CONFIGURATION */
SFR(P3MDOUT, 0xA7); /* PORT 3 OUTPUT MODE CONFIGURATION */
SFR(P1MDIN, 0xAD); /* PORT 1 INPUT MODE */
SFR(P2MDIN, 0xAE); /* PORT 2 INPUT MODE */
SFR(P3MDIN, 0xAF); /* PORT 3 INPUT MODE */
SFR(FLACL, 0xB7); /* FLASH ACCESS LIMIT */
SFR(P4, 0xC8); /* PORT 4 */
SFR(P5, 0xD8); /* PORT 5 */
SFR(XBR0, 0xE1); /* CROSSBAR CONFIGURATION REGISTER 0 */
SFR(XBR1, 0xE2); /* CROSSBAR CONFIGURATION REGISTER 1 */
SFR(XBR2, 0xE3); /* CROSSBAR CONFIGURATION REGISTER 2 */
SFR(XBR3, 0xE4); /* CROSSBAR CONFIGURATION REGISTER 3 */
SFR(P6, 0xE8); /* PORT 6 */
SFR(P7, 0xF8); /* PORT 7 */
/*
Do NOT use sfr16 for CAN0DAT !
*/
/* BIT Registers */
/* P0 0x80 */
SBIT(P0_0, 0x80, 0);
SBIT(P0_1, 0x80, 1);
SBIT(P0_2, 0x80, 2);
SBIT(P0_3, 0x80, 3);
SBIT(P0_4, 0x80, 4);
SBIT(P0_5, 0x80, 5);
SBIT(P0_6, 0x80, 6);
SBIT(P0_7, 0x80, 7);
/* TCON 0x88 */
SBIT(IT0, 0x88, 0); /* EXT. INTERRUPT 0 TYPE */
SBIT(IE0, 0x88, 1); /* EXT. INTERRUPT 0 EDGE FLAG */
SBIT(IT1, 0x88, 2); /* EXT. INTERRUPT 1 TYPE */
SBIT(IE1, 0x88, 3); /* EXT. INTERRUPT 1 EDGE FLAG */
SBIT(TR0, 0x88, 4); /* TIMER 0 ON/OFF CONTROL */
SBIT(TF0, 0x88, 5); /* TIMER 0 OVERFLOW FLAG */
SBIT(TR1, 0x88, 6); /* TIMER 1 ON/OFF CONTROL */
SBIT(TF1, 0x88, 7); /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
SBIT(CP0HYN0, 0x88, 0); /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
SBIT(CP0HYN1, 0x88, 1); /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
SBIT(CP0HYP0, 0x88, 2); /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
SBIT(CP0HYP1, 0x88, 3); /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
SBIT(CP0FIF, 0x88, 4); /* COMPARATOR 0 FALLING EDGE INTERRUPT */
SBIT(CP0RIF, 0x88, 5); /* COMPARATOR 0 RISING EDGE INTERRUPT */
SBIT(CP0OUT, 0x88, 6); /* COMPARATOR 0 OUTPUT */
SBIT(CP0EN, 0x88, 7); /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
SBIT(CP1HYN0, 0x88, 0); /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
SBIT(CP1HYN1, 0x88, 1); /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
SBIT(CP1HYP0, 0x88, 2); /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
SBIT(CP1HYP1, 0x88, 3); /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
SBIT(CP1FIF, 0x88, 4); /* COMPARATOR 1 FALLING EDGE INTERRUPT */
SBIT(CP1RIF, 0x88, 5); /* COMPARATOR 1 RISING EDGE INTERRUPT */
SBIT(CP1OUT, 0x88, 6); /* COMPARATOR 1 OUTPUT */
SBIT(CP1EN, 0x88, 7); /* COMPARATOR 1 ENABLE */
/* CPT2CN 0x88 */
SBIT(CP2HYN0, 0x88, 0); /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
SBIT(CP2HYN1, 0x88, 1); /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
SBIT(CP2HYP0, 0x88, 2); /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
SBIT(CP2HYP1, 0x88, 3); /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
SBIT(CP2FIF, 0x88, 4); /* COMPARATOR 2 FALLING EDGE INTERRUPT */
SBIT(CP2RIF, 0x88, 5); /* COMPARATOR 2 RISING EDGE INTERRUPT */
SBIT(CP2OUT, 0x88, 6); /* COMPARATOR 2 OUTPUT */
SBIT(CP2EN, 0x88, 7); /* COMPARATOR 2 ENABLE */
/* P1 0x90 */
SBIT(P1_0, 0x90, 0);
SBIT(P1_1, 0x90, 1);
SBIT(P1_2, 0x90, 2);
SBIT(P1_3, 0x90, 3);
SBIT(P1_4, 0x90, 4);
SBIT(P1_5, 0x90, 5);
SBIT(P1_6, 0x90, 6);
SBIT(P1_7, 0x90, 7);
/* SCON0 0x98 */
SBIT(RI0, 0x98, 0); /* UART 0 RX INTERRUPT FLAG */
SBIT(RI, 0x98, 0); /* UART 0 RX INTERRUPT FLAG */
SBIT(TI0, 0x98, 1); /* UART 0 TX INTERRUPT FLAG */
SBIT(TI, 0x98, 1); /* UART 0 TX INTERRUPT FLAG */
SBIT(RB80, 0x98, 2); /* UART 0 RX BIT 8 */
SBIT(TB80, 0x98, 3); /* UART 0 TX BIT 8 */
SBIT(REN0, 0x98, 4); /* UART 0 RX ENABLE */
SBIT(REN, 0x98, 4); /* UART 0 RX ENABLE */
SBIT(SM20, 0x98, 5); /* UART 0 MULTIPROCESSOR EN */
SBIT(SM10, 0x98, 6); /* UART 0 MODE 1 */
SBIT(SM00, 0x98, 7); /* UART 0 MODE 0 */
/* SCON1 0x98 */
SBIT(RI1, 0x98, 0); /* UART 1 RX INTERRUPT FLAG */
SBIT(TI1, 0x98, 1); /* UART 1 TX INTERRUPT FLAG */
SBIT(RB81, 0x98, 2); /* UART 1 RX BIT 8 */
SBIT(TB81, 0x98, 3); /* UART 1 TX BIT 8 */
SBIT(REN1, 0x98, 4); /* UART 1 RX ENABLE */
SBIT(MCE1, 0x98, 5); /* UART 1 MCE */
SBIT(S1MODE, 0x98, 7); /* UART 1 MODE */
/* P2 0xA0 */
SBIT(P2_0, 0xA0, 0);
SBIT(P2_1, 0xA0, 1);
SBIT(P2_2, 0xA0, 2);
SBIT(P2_3, 0xA0, 3);
SBIT(P2_4, 0xA0, 4);
SBIT(P2_5, 0xA0, 5);
SBIT(P2_6, 0xA0, 6);
SBIT(P2_7, 0xA0, 7);
/* IE 0xA8 */
SBIT(EX0, 0xA8, 0); /* EXTERNAL INTERRUPT 0 ENABLE */
SBIT(ET0, 0xA8, 1); /* TIMER 0 INTERRUPT ENABLE */
SBIT(EX1, 0xA8, 2); /* EXTERNAL INTERRUPT 1 ENABLE */
SBIT(ET1, 0xA8, 3); /* TIMER 1 INTERRUPT ENABLE */
SBIT(ES0, 0xA8, 4); /* UART0 INTERRUPT ENABLE */
SBIT(ES, 0xA8, 4); /* UART0 INTERRUPT ENABLE */
SBIT(ET2, 0xA8, 5); /* TIMER 2 INTERRUPT ENABLE */
SBIT(EA, 0xA8, 7); /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
SBIT(P3_0, 0xB0, 0);
SBIT(P3_1, 0xB0, 1);
SBIT(P3_2, 0xB0, 2);
SBIT(P3_3, 0xB0, 3);
SBIT(P3_4, 0xB0, 4);
SBIT(P3_5, 0xB0, 5);
SBIT(P3_6, 0xB0, 6);
SBIT(P3_7, 0xB0, 7);
/* IP 0xB8 */
SBIT(PX0, 0xB8, 0); /* EXTERNAL INTERRUPT 0 PRIORITY */
SBIT(PT0, 0xB8, 1); /* TIMER 0 PRIORITY */
SBIT(PX1, 0xB8, 2); /* EXTERNAL INTERRUPT 1 PRIORITY */
SBIT(PT1, 0xB8, 3); /* TIMER 1 PRIORITY */
SBIT(PS0, 0xB8, 4); /* SERIAL PORT PRIORITY */
SBIT(PS, 0xB8, 4); /* SERIAL PORT PRIORITY */
SBIT(PT2, 0xB8, 5); /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
SBIT(SMBTOE, 0xC0, 0); /* SMBUS 0 TIMEOUT ENABLE */
SBIT(SMBFTE, 0xC0, 1); /* SMBUS 0 FREE TIMER ENABLE */
SBIT(AA, 0xC0, 2); /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
SBIT(SI, 0xC0, 3); /* SMBUS 0 INTERRUPT PENDING FLAG */
SBIT(STO, 0xC0, 4); /* SMBUS 0 STOP FLAG */
SBIT(STA, 0xC0, 5); /* SMBUS 0 START FLAG */
SBIT(ENSMB, 0xC0, 6); /* SMBUS 0 ENABLE */
SBIT(BUSY, 0xC0, 7); /* SMBUS 0 BUSY */
/* CAN0STA 0xC0 */
SBIT(CANTXOK, 0xC0, 3); /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
SBIT(CANRXOK, 0xC0, 4); /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
SBIT(CANEPASS, 0xC0, 5); /* CAN ERROR PASSIVE */
SBIT(CANEWARN, 0xC0, 6); /* CAN WARNING STATUS */
SBIT(CANBOFF, 0xC0, 7); /* CAN BUSOFF STATUS */
/* TMR2CN 0xC8 */
SBIT(CPRL2, 0xC8, 0); /* TIMER 2 CAPTURE SELECT */
SBIT(CT2, 0xC8, 1); /* TIMER 2 COUNTER SELECT */
SBIT(TR2, 0xC8, 2); /* TIMER 2 ON/OFF CONTROL */
SBIT(EXEN2, 0xC8, 3); /* TIMER 2 EXTERNAL ENABLE FLAG */
SBIT(EXF2, 0xC8, 6); /* TIMER 2 EXTERNAL FLAG */
SBIT(TF2, 0xC8, 7); /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
SBIT(CPRL3, 0xC8, 0); /* TIMER 3 CAPTURE SELECT */
SBIT(CT3, 0xC8, 1); /* TIMER 3 COUNTER SELECT */
SBIT(TR3, 0xC8, 2); /* TIMER 3 ON/OFF CONTROL */
SBIT(EXEN3, 0xC8, 3); /* TIMER 3 EXTERNAL ENABLE FLAG */
SBIT(EXF3, 0xC8, 6); /* TIMER 3 EXTERNAL FLAG */
SBIT(TF3, 0xC8, 7); /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
SBIT(CPRL4, 0xC8, 0); /* TIMER 4 CAPTURE SELECT */
SBIT(CT4, 0xC8, 1); /* TIMER 4 COUNTER SELECT */
SBIT(TR4, 0xC8, 2); /* TIMER 4 ON/OFF CONTROL */
SBIT(EXEN4, 0xC8, 3); /* TIMER 4 EXTERNAL ENABLE FLAG */
SBIT(EXF4, 0xC8, 6); /* TIMER 4 EXTERNAL FLAG */
SBIT(TF4, 0xC8, 7); /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
SBIT(P4_0, 0xC8, 0);
SBIT(P4_1, 0xC8, 1);
SBIT(P4_2, 0xC8, 2);
SBIT(P4_3, 0xC8, 3);
SBIT(P4_4, 0xC8, 4);
SBIT(P4_5, 0xC8, 5);
SBIT(P4_6, 0xC8, 6);
SBIT(P4_7, 0xC8, 7);
/* PSW 0xD0 */
SBIT(P, 0xD0, 0); /* ACCUMULATOR PARITY FLAG */
SBIT(F1, 0xD0, 1); /* USER FLAG 1 */
SBIT(OV, 0xD0, 2); /* OVERFLOW FLAG */
SBIT(RS0, 0xD0, 3); /* REGISTER BANK SELECT 0 */
SBIT(RS1, 0xD0, 4); /* REGISTER BANK SELECT 1 */
SBIT(F0, 0xD0, 5); /* USER FLAG 0 */
SBIT(AC, 0xD0, 6); /* AUXILIARY CARRY FLAG */
SBIT(CY, 0xD0, 7); /* CARRY FLAG */
/* PCA0CN 0xD8 */
SBIT(CCF0, 0xD8, 0); /* PCA 0 MODULE 0 INTERRUPT FLAG */
SBIT(CCF1, 0xD8, 1); /* PCA 0 MODULE 1 INTERRUPT FLAG */
SBIT(CCF2, 0xD8, 2); /* PCA 0 MODULE 2 INTERRUPT FLAG */
SBIT(CCF3, 0xD8, 3); /* PCA 0 MODULE 3 INTERRUPT FLAG */
SBIT(CCF4, 0xD8, 4); /* PCA 0 MODULE 4 INTERRUPT FLAG */
SBIT(CCF5, 0xD8, 5); /* PCA 0 MODULE 5 INTERRUPT FLAG */
SBIT(CR, 0xD8, 6); /* PCA 0 COUNTER RUN CONTROL BIT */
SBIT(CF, 0xD8, 7); /* PCA 0 COUNTER OVERFLOW FLAG */
/* P5 0xD8 */
SBIT(P5_0, 0xD8, 0);
SBIT(P5_1, 0xD8, 1);
SBIT(P5_2, 0xD8, 2);
SBIT(P5_3, 0xD8, 3);
SBIT(P5_4, 0xD8, 4);
SBIT(P5_5, 0xD8, 5);
SBIT(P5_6, 0xD8, 6);
SBIT(P5_7, 0xD8, 7);
/* ADC0CN 0xE8 */
SBIT(AD0LJST, 0xE8, 0); /* ADC 0 RIGHT JUSTIFY DATA BIT */
SBIT(AD0WINT, 0xE8, 1); /* ADC 0 WINDOW INTERRUPT FLAG */
SBIT(AD0CM0, 0xE8, 2); /* ADC 0 CONVERT START MODE BIT 0 */
SBIT(AD0CM1, 0xE8, 3); /* ADC 0 CONVERT START MODE BIT 1 */
SBIT(AD0BUSY, 0xE8, 4); /* ADC 0 BUSY FLAG */
SBIT(AD0INT, 0xE8, 5); /* ADC 0 EOC INTERRUPT FLAG */
SBIT(AD0TM, 0xE8, 6); /* ADC 0 TRACK MODE */
SBIT(AD0EN, 0xE8, 7); /* ADC 0 ENABLE */
/* ADC2CN 0xE8 */
SBIT(AD2WINT, 0xE8, 0); /* ADC 2 WINDOW INTERRUPT FLAG */
SBIT(AD2CM0, 0xE8, 1); /* ADC 2 CONVERT START MODE BIT 0 */
SBIT(AD2CM1, 0xE8, 2); /* ADC 2 CONVERT START MODE BIT 1 */
SBIT(AD2CM2, 0xE8, 3); /* ADC 2 CONVERT START MODE BIT 2 */
SBIT(AD2BUSY, 0xE8, 4); /* ADC 2 BUSY FLAG */
SBIT(AD2INT, 0xE8, 5); /* ADC 2 EOC INTERRUPT FLAG */
SBIT(AD2TM, 0xE8, 6); /* ADC 2 TRACK MODE */
SBIT(AD2EN, 0xE8, 7); /* ADC 2 ENABLE */
/* P6 0xE8 */
SBIT(P6_0, 0xE8, 0);
SBIT(P6_1, 0xE8, 1);
SBIT(P6_2, 0xE8, 2);
SBIT(P6_3, 0xE8, 3);
SBIT(P6_4, 0xE8, 4);
SBIT(P6_5, 0xE8, 5);
SBIT(P6_6, 0xE8, 6);
SBIT(P6_7, 0xE8, 7);
/* SPI0CN 0xF8 */
SBIT(SPIEN, 0xF8, 0); /* SPI 0 SPI ENABLE */
SBIT(TXBMT, 0xF8, 1); /* SPI 0 TX BUFFER EMPTY FLAG */
SBIT(NSSMD0, 0xF8, 2); /* SPI 0 SLAVE SELECT MODE 0 */
SBIT(NSSMD1, 0xF8, 3); /* SPI 0 SLAVE SELECT MODE 1 */
SBIT(RXOVRN, 0xF8, 4); /* SPI 0 RX OVERRUN FLAG */
SBIT(MODF, 0xF8, 5); /* SPI 0 MODE FAULT FLAG */
SBIT(WCOL, 0xF8, 6); /* SPI 0 WRITE COLLISION FLAG */
SBIT(SPIF, 0xF8, 7); /* SPI 0 INTERRUPT FLAG */
/* CAN0CN 0xF8 */
SBIT(CANINIT, 0xF8, 0); /* CAN INITIALIZATION */
SBIT(CANIE, 0xF8, 1); /* CAN MODULE INTERRUPT ENABLE */
SBIT(CANSIE, 0xF8, 2); /* CAN STATUS CHANGE INTERRUPT ENABLE */
SBIT(CANEIE, 0xF8, 3); /* CAN ERROR INTERRUPT ENABLE */
SBIT(CANIF, 0xF8, 4); /* CAN INTERRUPT FLAG */
SBIT(CANDAR, 0xF8, 5); /* CAN DISABLE AUTOMATIC RETRANSMISSION */
SBIT(CANCCE, 0xF8, 6); /* CAN CONFIGURATION CHANGE ENABLE */
SBIT(CANTEST, 0xF8, 7); /* CAN TEST MODE ENABLE */
/* P7 0xF8 */
SBIT(P7_0, 0xF8, 0);
SBIT(P7_1, 0xF8, 1);
SBIT(P7_2, 0xF8, 2);
SBIT(P7_3, 0xF8, 3);
SBIT(P7_4, 0xF8, 4);
SBIT(P7_5, 0xF8, 5);
SBIT(P7_6, 0xF8, 6);
SBIT(P7_7, 0xF8, 7);
/* Predefined SFR Bit Masks */
#define IDLE 0x01 /* PCON */
#define STOP 0x02 /* PCON */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
/* SFR PAGE DEFINITIONS */
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
#define CPT2_PAGE 0x03 /* COMPARATOR 2 */
#define UART0_PAGE 0x00 /* UART 0 */
#define UART1_PAGE 0x01 /* UART 1 */
#define SPI0_PAGE 0x00 /* SPI 0 */
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
#define ADC0_PAGE 0x00 /* ADC 0 */
#define ADC2_PAGE 0x02 /* ADC 2 */
#define SMB0_PAGE 0x00 /* SMBUS 0 */
#define TMR2_PAGE 0x00 /* TIMER 2 */
#define TMR3_PAGE 0x01 /* TIMER 3 */
#define TMR4_PAGE 0x02 /* TIMER 4 */
#define DAC0_PAGE 0x00 /* DAC 0 */
#define DAC1_PAGE 0x01 /* DAC 1 */
#define PCA0_PAGE 0x00 /* PCA 0 */
#define CAN0_PAGE 0x01 /* CAN 0 */
#endif

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OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/C8051F060.h Normal file
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/*-------------------------------------------------------------------------
C8051F060.h - Register Declarations for the Cygnal/SiLabs C8051F06x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F060_H
#define C8051F060_H
#include <compiler.h>
/* BYTE Registers */
/* All Pages */
SFR(P0, 0x80); /* PORT 0 */
SFR(SP, 0x81); /* STACK POINTER */
SFR(DPL, 0x82); /* DATA POINTER - LOW BYTE */
SFR(DPH, 0x83); /* DATA POINTER - HIGH BYTE */
SFR(SFRPAGE, 0x84); /* SFR PAGE SELECT */
SFR(SFRNEXT, 0x85); /* SFR STACK NEXT PAGE */
SFR(SFRLAST, 0x86); /* SFR STACK LAST PAGE */
SFR(PCON, 0x87); /* POWER CONTROL */
SFR(P1, 0x90); /* PORT 1 */
SFR(P2, 0xA0); /* PORT 2 */
SFR(IE, 0xA8); /* INTERRUPT ENABLE */
SFR(P3, 0xB0); /* PORT 3 */
SFR(IP, 0xB8); /* INTERRUPT PRIORITY */
SFR(PSW, 0xD0); /* PROGRAM STATUS WORD */
SFR(ACC, 0xE0); /* ACCUMULATOR */
SFR(EIE1, 0xE6); /* EXTERNAL INTERRUPT ENABLE 1 */
SFR(EIE2, 0xE7); /* EXTERNAL INTERRUPT ENABLE 2 */
SFR(B, 0xF0); /* B REGISTER */
SFR(EIP1, 0xF6); /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
SFR(EIP2, 0xF7); /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
SFR(WDTCN, 0xFF); /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
SFR(TCON, 0x88); /* TIMER CONTROL */
SFR(TMOD, 0x89); /* TIMER MODE */
SFR(TL0, 0x8A); /* TIMER 0 - LOW BYTE */
SFR(TL1, 0x8B); /* TIMER 1 - LOW BYTE */
SFR(TH0, 0x8C); /* TIMER 0 - HIGH BYTE */
SFR(TH1, 0x8D); /* TIMER 1 - HIGH BYTE */
SFR(CKCON, 0x8E); /* TIMER 0/1 CLOCK CONTROL */
SFR(PSCTL, 0x8F); /* FLASH WRITE/ERASE CONTROL */
SFR(SSTA0, 0x91); /* UART 0 STATUS */
SFR(SCON0, 0x98); /* UART 0 CONTROL */
SFR(SCON, 0x98); /* UART 0 CONTROL */
SFR(SBUF0, 0x99); /* UART 0 BUFFER */
SFR(SBUF, 0x99); /* UART 0 BUFFER */
SFR(SPI0CFG, 0x9A); /* SPI 0 CONFIGURATION */
SFR(SPI0DAT, 0x9B); /* SPI 0 DATA */
SFR(SPI0CKR, 0x9D); /* SPI 0 CLOCK RATE CONTROL */
SFR(EMI0TC, 0xA1); /* EMIF TIMING CONTROL */
SFR(EMI0CN, 0xA2); /* EMIF CONTROL */
SFR(_XPAGE, 0xA2); /* XDATA/PDATA PAGE */
SFR(EMI0CF, 0xA3); /* EMIF CONFIGURATION */
SFR(SADDR0, 0xA9); /* UART 0 SLAVE ADDRESS */
SFR(FLSCL, 0xB7); /* FLASH SCALE */
SFR(SADEN0, 0xB9); /* UART 0 SLAVE ADDRESS MASK */
SFR(AMX0SL, 0xBB); /* ADC 0 MUX CHANNEL SELECTION */
SFR(ADC0CF, 0xBC); /* ADC 0 CONFIGURATION */
SFR(ADC0L, 0xBE); /* ADC 0 DATA - LOW BYTE */
SFR(ADC0H, 0xBF); /* ADC 0 DATA - HIGH BYTE */
SFR(SMB0CN, 0xC0); /* SMBUS 0 CONTROL */
SFR(SMB0STA, 0xC1); /* SMBUS 0 STATUS */
SFR(SMB0DAT, 0xC2); /* SMBUS 0 DATA */
SFR(SMB0ADR, 0xC3); /* SMBUS 0 SLAVE ADDRESS */
SFR(ADC0GTL, 0xC4); /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
SFR(ADC0GTH, 0xC5); /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
SFR(ADC0LTL, 0xC6); /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
SFR(ADC0LTH, 0xC7); /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
SFR(TMR2CN, 0xC8); /* TIMER 2 CONTROL */
SFR(TMR2CF, 0xC9); /* TIMER 2 CONFIGURATION */
SFR(RCAP2L, 0xCA); /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR(RCAP2H, 0xCB); /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR(TMR2L, 0xCC); /* TIMER 2 - LOW BYTE */
SFR(TL2, 0xCC); /* TIMER 2 - LOW BYTE */
SFR(TMR2H, 0xCD); /* TIMER 2 - HIGH BYTE */
SFR(TH2, 0xCD); /* TIMER 2 - HIGH BYTE */
SFR(SMB0CR, 0xCF); /* SMBUS 0 CLOCK RATE */
SFR(REF0CN, 0xD1); /* VOLTAGE REFERENCE 0 CONTROL */
SFR(DAC0L, 0xD2); /* DAC 0 REGISTER - LOW BYTE */
SFR(DAC0H, 0xD3); /* DAC 0 REGISTER - HIGH BYTE */
SFR(DAC0CN, 0xD4); /* DAC 0 CONTROL */
SFR(PCA0CN, 0xD8); /* PCA 0 COUNTER CONTROL */
SFR(PCA0MD, 0xD9); /* PCA 0 COUNTER MODE */
SFR(PCA0CPM0, 0xDA); /* PCA 0 MODULE 0 CONTROL */
SFR(PCA0CPM1, 0xDB); /* PCA 0 MODULE 1 CONTROL */
SFR(PCA0CPM2, 0xDC); /* PCA 0 MODULE 2 CONTROL */
SFR(PCA0CPM3, 0xDD); /* PCA 0 MODULE 3 CONTROL */
SFR(PCA0CPM4, 0xDE); /* PCA 0 MODULE 4 CONTROL */
SFR(PCA0CPM5, 0xDF); /* PCA 0 MODULE 5 CONTROL */
SFR(PCA0CPL5, 0xE1); /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH5, 0xE2); /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
SFR(ADC0CN, 0xE8); /* ADC 0 CONTROL */
SFR(PCA0CPL2, 0xE9); /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH2, 0xEA); /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
SFR(PCA0CPL3, 0xEB); /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH3, 0xEC); /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
SFR(PCA0CPL4, 0xED); /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH4, 0xEE); /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
SFR(RSTSRC, 0xEF); /* RESET SOURCE */
SFR(SPI0CN, 0xF8); /* SPI 0 CONTROL */
SFR(PCA0L, 0xF9); /* PCA 0 TIMER - LOW BYTE */
SFR(PCA0H, 0xFA); /* PCA 0 TIMER - HIGH BYTE */
SFR(PCA0CPL0, 0xFB); /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH0, 0xFC); /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
SFR(PCA0CPL1, 0xFD); /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
SFR(PCA0CPH1, 0xFE); /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
SFR(CPT0CN, 0x88); /* COMPARATOR 0 CONTROL */
SFR(CPT0MD, 0x89); /* COMPARATOR 0 CONFIGURATION */
SFR(SCON1, 0x98); /* UART 1 CONTROL */
SFR(SBUF1, 0x99); /* UART 1 BUFFER */
SFR(ADC1CF, 0xBC); /* ADC 1 CONFIGURATION */
SFR(ADC1L, 0xBE); /* ADC 1 DATA - LOW BYTE */
SFR(ADC1H, 0xBF); /* ADC 1 DATA - HIGH BYTE */
SFR(CAN0STA, 0xC0); /* CAN 0 STATUS */
SFR(TMR3CN, 0xC8); /* TIMER 3 CONTROL */
SFR(TMR3CF, 0xC9); /* TIMER 3 CONFIGURATION */
SFR(RCAP3L, 0xCA); /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
SFR(RCAP3H, 0xCB); /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
SFR(TMR3L, 0xCC); /* TIMER 3 - LOW BYTE */
SFR(TMR3H, 0xCD); /* TIMER 3 - HIGH BYTE */
SFR(REF1CN, 0xD1); /* VOLTAGE REFERENCE 1 CONTROL */
SFR(DAC1L, 0xD2); /* DAC 1 REGISTER - LOW BYTE */
SFR(DAC1H, 0xD3); /* DAC 1 REGISTER - HIGH BYTE */
SFR(DAC1CN, 0xD4); /* DAC 1 CONTROL */
SFR(CAN0DATL, 0xD8); /* CAN 0 DATA REGISTER LOW */
SFR(CAN0DATH, 0xD9); /* CAN 0 DATA REGISTER HIGH */
SFR(CAN0ADR, 0xDA); /* CAN 0 ADDRESS */
SFR(CAN0TST, 0xDB); /* CAN 0 TEST REGISTER */
SFR(ADC1CN, 0xE8); /* ADC 1 CONTROL */
SFR(CAN0CN, 0xF8); /* CAN 0 CONTROL */
/* Page 0x02 */
SFR(CPT1CN, 0x88); /* COMPARATOR 1 CONTROL */
SFR(CPT1MD, 0x89); /* COMPARATOR 1 CONFIGURATION */
SFR(AMX2CF, 0xBA); /* ADC 2 MUX CONFIGURATION */
SFR(AMX2SL, 0xBB); /* ADC 2 MUX CHANNEL SELECTION */
SFR(ADC2CF, 0xBC); /* ADC 2 CONFIGURATION */
SFR(ADC2L, 0xBE); /* ADC 2 DATA - LOW BYTE */
SFR(ADC2H, 0xBF); /* ADC 2 DATA - HIGH BYTE */
SFR(ADC2GTL, 0xC4); /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */
SFR(ADC2GTH, 0xC5); /* ADC 2 GREATER-THAN REGISTER - HIGH BYTE */
SFR(ADC2LTL, 0xC6); /* ADC 2 LESS-THAN REGISTER - LOW BYTE */
SFR(ADC2LTH, 0xC7); /* ADC 2 LESS-THAN REGISTER - HIGH BYTE */
SFR(TMR4CN, 0xC8); /* TIMER 4 CONTROL */
SFR(TMR4CF, 0xC9); /* TIMER 4 CONFIGURATION */
SFR(RCAP4L, 0xCA); /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
SFR(RCAP4H, 0xCB); /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
SFR(TMR4L, 0xCC); /* TIMER 4 - LOW BYTE */
SFR(TMR4H, 0xCD); /* TIMER 4 - HIGH BYTE */
SFR(REF2CN, 0xD1); /* VOLTAGE REFERENCE 2 CONTROL */
SFR(ADC2CN, 0xE8); /* ADC 2 CONTROL */
/* Page 0x03 */
SFR(CPT2CN, 0x88); /* COMPARATOR 2 CONTROL */
SFR(CPT2MD, 0x89); /* COMPARATOR 2 CONFIGURATION */
SFR(DMA0CN, 0xD8); /* DMA0 CONTROL */
SFR(DMA0DAL, 0xD9); /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
SFR(DMA0DAH, 0xDA); /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
SFR(DMA0DSL, 0xDB); /* DMA0 DATA ADDRESS POINTER LOW BYTE */
SFR(DMA0DSH, 0xDC); /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
SFR(DMA0IPT, 0xDD); /* DMA0 INSTRUCTION WRITE ADDRESS */
SFR(DMA0IDT, 0xDE); /* DMA0 INSTRUCTION WRITE DATA */
SFR(DMA0CF, 0xF8); /* DMA0 CONFIGURATION */
SFR(DMA0CTL, 0xF9); /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
SFR(DMA0CTH, 0xFA); /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
SFR(DMA0CSL, 0xFB); /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
SFR(DMA0CSH, 0xFC); /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
SFR(DMA0BND, 0xFD); /* DMA0 INSTRUCTION BOUNDARY */
SFR(DMA0ISW, 0xFE); /* DMA0 INSTRUCTION STATUS */
/* Page 0x0F */
SFR(OSCICN, 0x8A); /* INTERNAL OSCILLATOR CONTROL */
SFR(OSCICL, 0x8B); /* INTERNAL OSCILLATOR CALIBRATION */
SFR(OSCXCN, 0x8C); /* EXTERNAL OSCILLATOR CONTROL */
SFR(SFRPGCN, 0x96); /* SFR PAGE CONTROL */
SFR(CLKSEL, 0x97); /* SYSTEM CLOCK SELECT */
SFR(P4MDOUT, 0x9C); /* PORT 4 OUTPUT MODE */
SFR(P5MDOUT, 0x9D); /* PORT 5 OUTPUT MODE */
SFR(P6MDOUT, 0x9E); /* PORT 6 OUTPUT MODE */
SFR(P7MDOUT, 0x9F); /* PORT 7 OUTPUT MODE */
SFR(P0MDOUT, 0xA4); /* PORT 0 OUTPUT MODE */
SFR(P1MDOUT, 0xA5); /* PORT 1 OUTPUT MODE */
SFR(P2MDOUT, 0xA6); /* PORT 2 OUTPUT MODE CONFIGURATION */
SFR(P3MDOUT, 0xA7); /* PORT 3 OUTPUT MODE CONFIGURATION */
SFR(P1MDIN, 0xAD); /* PORT 1 INPUT MODE */
SFR(P2MDIN, 0xAE); /* PORT 2 INPUT MODE */
SFR(FLACL, 0xB7); /* FLASH ACCESS LIMIT */
SFR(ADC0CPT, 0xBA); /* ADC0 CALIBRATION POINTER */
SFR(ADC0CCF, 0xBB); /* ADC0 CALIBRATION COEFFICIENT */
SFR(P4, 0xC8); /* PORT 4 */
SFR(P5, 0xD8); /* PORT 5 */
SFR(XBR0, 0xE1); /* CROSSBAR CONFIGURATION REGISTER 0 */
SFR(XBR1, 0xE2); /* CROSSBAR CONFIGURATION REGISTER 1 */
SFR(XBR2, 0xE3); /* CROSSBAR CONFIGURATION REGISTER 2 */
SFR(XBR3, 0xE4); /* CROSSBAR CONFIGURATION REGISTER 3 */
SFR(P6, 0xE8); /* PORT 6 */
SFR(P7, 0xF8); /* PORT 7 */
/* BIT Registers */
/* P0 0x80 */
SBIT(P0_0, 0x80, 0);
SBIT(P0_1, 0x80, 1);
SBIT(P0_2, 0x80, 2);
SBIT(P0_3, 0x80, 3);
SBIT(P0_4, 0x80, 4);
SBIT(P0_5, 0x80, 5);
SBIT(P0_6, 0x80, 6);
SBIT(P0_7, 0x80, 7);
/* TCON 0x88 */
SBIT(IT0, 0x88, 0); /* EXT. INTERRUPT 0 TYPE */
SBIT(IE0, 0x88, 1); /* EXT. INTERRUPT 0 EDGE FLAG */
SBIT(IT1, 0x88, 2); /* EXT. INTERRUPT 1 TYPE */
SBIT(IE1, 0x88, 3); /* EXT. INTERRUPT 1 EDGE FLAG */
SBIT(TR0, 0x88, 4); /* TIMER 0 ON/OFF CONTROL */
SBIT(TF0, 0x88, 5); /* TIMER 0 OVERFLOW FLAG */
SBIT(TR1, 0x88, 6); /* TIMER 1 ON/OFF CONTROL */
SBIT(TF1, 0x88, 7); /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
SBIT(CP0HYN0, 0x88, 0); /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
SBIT(CP0HYN1, 0x88, 1); /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
SBIT(CP0HYP0, 0x88, 2); /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
SBIT(CP0HYP1, 0x88, 3); /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
SBIT(CP0FIF, 0x88, 4); /* COMPARATOR 0 FALLING EDGE INTERRUPT */
SBIT(CP0RIF, 0x88, 5); /* COMPARATOR 0 RISING EDGE INTERRUPT */
SBIT(CP0OUT, 0x88, 6); /* COMPARATOR 0 OUTPUT */
SBIT(CP0EN, 0x88, 7); /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
SBIT(CP1HYN0, 0x88, 0); /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
SBIT(CP1HYN1, 0x88, 1); /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
SBIT(CP1HYP0, 0x88, 2); /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
SBIT(CP1HYP1, 0x88, 3); /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
SBIT(CP1FIF, 0x88, 4); /* COMPARATOR 1 FALLING EDGE INTERRUPT */
SBIT(CP1RIF, 0x88, 5); /* COMPARATOR 1 RISING EDGE INTERRUPT */
SBIT(CP1OUT, 0x88, 6); /* COMPARATOR 1 OUTPUT */
SBIT(CP1EN, 0x88, 7); /* COMPARATOR 1 ENABLE */
/* CPT2CN 0x88 */
SBIT(CP2HYN0, 0x88, 0); /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
SBIT(CP2HYN1, 0x88, 1); /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
SBIT(CP2HYP0, 0x88, 2); /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
SBIT(CP2HYP1, 0x88, 3); /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
SBIT(CP2FIF, 0x88, 4); /* COMPARATOR 2 FALLING EDGE INTERRUPT */
SBIT(CP2RIF, 0x88, 5); /* COMPARATOR 2 RISING EDGE INTERRUPT */
SBIT(CP2OUT, 0x88, 6); /* COMPARATOR 2 OUTPUT */
SBIT(CP2EN, 0x88, 7); /* COMPARATOR 2 ENABLE */
/* P1 0x90 */
SBIT(P1_0, 0x90, 0);
SBIT(P1_1, 0x90, 1);
SBIT(P1_2, 0x90, 2);
SBIT(P1_3, 0x90, 3);
SBIT(P1_4, 0x90, 4);
SBIT(P1_5, 0x90, 5);
SBIT(P1_6, 0x90, 6);
SBIT(P1_7, 0x90, 7);
/* SCON0 0x98 */
SBIT(RI0, 0x98, 0); /* UART 0 RX INTERRUPT FLAG */
SBIT(RI, 0x98, 0); /* UART 0 RX INTERRUPT FLAG */
SBIT(TI0, 0x98, 1); /* UART 0 TX INTERRUPT FLAG */
SBIT(TI, 0x98, 1); /* UART 0 TX INTERRUPT FLAG */
SBIT(RB80, 0x98, 2); /* UART 0 RX BIT 8 */
SBIT(TB80, 0x98, 3); /* UART 0 TX BIT 8 */
SBIT(REN0, 0x98, 4); /* UART 0 RX ENABLE */
SBIT(REN, 0x98, 4); /* UART 0 RX ENABLE */
SBIT(SM20, 0x98, 5); /* UART 0 MULTIPROCESSOR EN */
SBIT(SM10, 0x98, 6); /* UART 0 MODE 1 */
SBIT(SM00, 0x98, 7); /* UART 0 MODE 0 */
/* SCON1 0x98 */
SBIT(RI1, 0x98, 0); /* UART 1 RX INTERRUPT FLAG */
SBIT(TI1, 0x98, 1); /* UART 1 TX INTERRUPT FLAG */
SBIT(RB81, 0x98, 2); /* UART 1 RX BIT 8 */
SBIT(TB81, 0x98, 3); /* UART 1 TX BIT 8 */
SBIT(REN1, 0x98, 4); /* UART 1 RX ENABLE */
SBIT(MCE1, 0x98, 5); /* UART 1 MCE */
SBIT(S1MODE, 0x98, 7); /* UART 1 MODE */
/* P2 0xA0 */
SBIT(P2_0, 0xA0, 0);
SBIT(P2_1, 0xA0, 1);
SBIT(P2_2, 0xA0, 2);
SBIT(P2_3, 0xA0, 3);
SBIT(P2_4, 0xA0, 4);
SBIT(P2_5, 0xA0, 5);
SBIT(P2_6, 0xA0, 6);
SBIT(P2_7, 0xA0, 7);
/* IE 0xA8 */
SBIT(EX0, 0xA8, 0); /* EXTERNAL INTERRUPT 0 ENABLE */
SBIT(ET0, 0xA8, 1); /* TIMER 0 INTERRUPT ENABLE */
SBIT(EX1, 0xA8, 2); /* EXTERNAL INTERRUPT 1 ENABLE */
SBIT(ET1, 0xA8, 3); /* TIMER 1 INTERRUPT ENABLE */
SBIT(ES0, 0xA8, 4); /* UART0 INTERRUPT ENABLE */
SBIT(ES, 0xA8, 4); /* UART0 INTERRUPT ENABLE */
SBIT(ET2, 0xA8, 5); /* TIMER 2 INTERRUPT ENABLE */
SBIT(EA, 0xA8, 7); /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
SBIT(P3_0, 0xB0, 0);
SBIT(P3_1, 0xB0, 1);
SBIT(P3_2, 0xB0, 2);
SBIT(P3_3, 0xB0, 3);
SBIT(P3_4, 0xB0, 4);
SBIT(P3_5, 0xB0, 5);
SBIT(P3_6, 0xB0, 6);
SBIT(P3_7, 0xB0, 7);
/* IP 0xB8 */
SBIT(PX0, 0xB8, 0); /* EXTERNAL INTERRUPT 0 PRIORITY */
SBIT(PT0, 0xB8, 1); /* TIMER 0 PRIORITY */
SBIT(PX1, 0xB8, 2); /* EXTERNAL INTERRUPT 1 PRIORITY */
SBIT(PT1, 0xB8, 3); /* TIMER 1 PRIORITY */
SBIT(PS0, 0xB8, 4); /* SERIAL PORT PRIORITY */
SBIT(PS, 0xB8, 4); /* SERIAL PORT PRIORITY */
SBIT(PT2, 0xB8, 5); /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
SBIT(SMBTOE, 0xC0, 0); /* SMBUS 0 TIMEOUT ENABLE */
SBIT(SMBFTE, 0xC0, 1); /* SMBUS 0 FREE TIMER ENABLE */
SBIT(AA, 0xC0, 2); /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
SBIT(SI, 0xC0, 3); /* SMBUS 0 INTERRUPT PENDING FLAG */
SBIT(STO, 0xC0, 4); /* SMBUS 0 STOP FLAG */
SBIT(STA, 0xC0, 5); /* SMBUS 0 START FLAG */
SBIT(ENSMB, 0xC0, 6); /* SMBUS 0 ENABLE */
SBIT(BUSY, 0xC0, 7); /* SMBUS 0 BUSY */
/* CAN0STA 0xC0 */
SBIT(CANTXOK, 0xC0, 3); /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
SBIT(CANRXOK, 0xC0, 4); /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
SBIT(CANEPASS, 0xC0, 5); /* CAN ERROR PASSIVE */
SBIT(CANEWARN, 0xC0, 6); /* CAN WARNING STATUS */
SBIT(CANBOFF, 0xC0, 7); /* CAN BUSOFF STATUS */
/* TMR2CN 0xC8 */
SBIT(CPRL2, 0xC8, 0); /* TIMER 2 CAPTURE SELECT */
SBIT(CT2, 0xC8, 1); /* TIMER 2 COUNTER SELECT */
SBIT(TR2, 0xC8, 2); /* TIMER 2 ON/OFF CONTROL */
SBIT(EXEN2, 0xC8, 3); /* TIMER 2 EXTERNAL ENABLE FLAG */
SBIT(EXF2, 0xC8, 6); /* TIMER 2 EXTERNAL FLAG */
SBIT(TF2, 0xC8, 7); /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
SBIT(CPRL3, 0xC8, 0); /* TIMER 3 CAPTURE SELECT */
SBIT(CT3, 0xC8, 1); /* TIMER 3 COUNTER SELECT */
SBIT(TR3, 0xC8, 2); /* TIMER 3 ON/OFF CONTROL */
SBIT(EXEN3, 0xC8, 3); /* TIMER 3 EXTERNAL ENABLE FLAG */
SBIT(EXF3, 0xC8, 6); /* TIMER 3 EXTERNAL FLAG */
SBIT(TF3, 0xC8, 7); /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
SBIT(CPRL4, 0xC8, 0); /* TIMER 4 CAPTURE SELECT */
SBIT(CT4, 0xC8, 1); /* TIMER 4 COUNTER SELECT */
SBIT(TR4, 0xC8, 2); /* TIMER 4 ON/OFF CONTROL */
SBIT(EXEN4, 0xC8, 3); /* TIMER 4 EXTERNAL ENABLE FLAG */
SBIT(EXF4, 0xC8, 6); /* TIMER 4 EXTERNAL FLAG */
SBIT(TF4, 0xC8, 7); /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
SBIT(P4_0, 0xC8, 0);
SBIT(P4_1, 0xC8, 1);
SBIT(P4_2, 0xC8, 2);
SBIT(P4_3, 0xC8, 3);
SBIT(P4_4, 0xC8, 4);
SBIT(P4_5, 0xC8, 5);
SBIT(P4_6, 0xC8, 6);
SBIT(P4_7, 0xC8, 7);
/* PSW 0xD0 */
SBIT(P, 0xD0, 0); /* ACCUMULATOR PARITY FLAG */
SBIT(F1, 0xD0, 1); /* USER FLAG 1 */
SBIT(OV, 0xD0, 2); /* OVERFLOW FLAG */
SBIT(RS0, 0xD0, 3); /* REGISTER BANK SELECT 0 */
SBIT(RS1, 0xD0, 4); /* REGISTER BANK SELECT 1 */
SBIT(F0, 0xD0, 5); /* USER FLAG 0 */
SBIT(AC, 0xD0, 6); /* AUXILIARY CARRY FLAG */
SBIT(CY, 0xD0, 7); /* CARRY FLAG */
/* PCA0CN 0xD8 */
SBIT(CCF0, 0xD8, 0); /* PCA 0 MODULE 0 INTERRUPT FLAG */
SBIT(CCF1, 0xD8, 1); /* PCA 0 MODULE 1 INTERRUPT FLAG */
SBIT(CCF2, 0xD8, 2); /* PCA 0 MODULE 2 INTERRUPT FLAG */
SBIT(CCF3, 0xD8, 3); /* PCA 0 MODULE 3 INTERRUPT FLAG */
SBIT(CCF4, 0xD8, 4); /* PCA 0 MODULE 4 INTERRUPT FLAG */
SBIT(CCF5, 0xD8, 5); /* PCA 0 MODULE 5 INTERRUPT FLAG */
SBIT(CR, 0xD8, 6); /* PCA 0 COUNTER RUN CONTROL BIT */
SBIT(CF, 0xD8, 7); /* PCA 0 COUNTER OVERFLOW FLAG */
/* DMA0CN 0xD8 */
SBIT(DMA0DO0, 0xD8, 0); /* ADC0 Data Overflow Warning Flag */
SBIT(DMA0DO1, 0xD8, 1); /* ADC1 Data Overflow Warning Flag */
SBIT(DMA0DOE, 0xD8, 2); /* Data Overflow Warning Interrupt Enable */
SBIT(DMA0DE0, 0xD8, 3); /* ADC0 Data Overflow Error Flag */
SBIT(DMA0DE1, 0xD8, 4); /* ADC1 Data Overflow Error Flag */
SBIT(DMA0MD, 0xD8, 5); /* DMA0 Mode Select */
SBIT(DMA0INT, 0xD8, 6); /* DMA0 Operations Complete Flag */
SBIT(DMA0EN, 0xD8, 7); /* DMA0 Enable */
/* P5 0xD8 */
SBIT(P5_0, 0xD8, 0);
SBIT(P5_1, 0xD8, 1);
SBIT(P5_2, 0xD8, 2);
SBIT(P5_3, 0xD8, 3);
SBIT(P5_4, 0xD8, 4);
SBIT(P5_5, 0xD8, 5);
SBIT(P5_6, 0xD8, 6);
SBIT(P5_7, 0xD8, 7);
/* ADC0CN 0xE8 */
SBIT(AD0WINT, 0xE8, 1); /* ADC 0 WINDOW INTERRUPT FLAG */
SBIT(AD0CM0, 0xE8, 2); /* ADC 0 CONVERT START MODE BIT 0 */
SBIT(AD0CM1, 0xE8, 3); /* ADC 0 CONVERT START MODE BIT 1 */
SBIT(AD0BUSY, 0xE8, 4); /* ADC 0 BUSY FLAG */
SBIT(AD0INT, 0xE8, 5); /* ADC 0 EOC INTERRUPT FLAG */
SBIT(AD0TM, 0xE8, 6); /* ADC 0 TRACK MODE */
SBIT(AD0EN, 0xE8, 7); /* ADC 0 ENABLE */
/* ADC1CN 0xE8 */
SBIT(AD1CM0, 0xE8, 1); /* ADC 1 CONVERT START MODE BIT 0 */
SBIT(AD1CM1, 0xE8, 2); /* ADC 1 CONVERT START MODE BIT 1 */
SBIT(AD1CM2, 0xE8, 3); /* ADC 1 CONVERT START MODE BIT 1 */
SBIT(AD1BUSY, 0xE8, 4); /* ADC 1 BUSY FLAG */
SBIT(AD1INT, 0xE8, 5); /* ADC 1 EOC INTERRUPT FLAG */
SBIT(AD1TM, 0xE8, 6); /* ADC 1 TRACK MODE */
SBIT(AD1EN, 0xE8, 7); /* ADC 1 ENABLE */
/* ADC2CN 0xE8 */
SBIT(AD2LJST, 0xE8, 0); /* ADC 2 LEFT JUSTIFY SELECT */
SBIT(AD2WINT, 0xE8, 1); /* ADC 2 WINDOW INTERRUPT FLAG */
SBIT(AD2CM0, 0xE8, 2); /* ADC 2 CONVERT START MODE BIT 0 */
SBIT(AD2CM1, 0xE8, 3); /* ADC 2 CONVERT START MODE BIT 1 */
SBIT(AD2BUSY, 0xE8, 4); /* ADC 2 BUSY FLAG */
SBIT(AD2INT, 0xE8, 5); /* ADC 2 EOC INTERRUPT FLAG */
SBIT(AD2TM, 0xE8, 6); /* ADC 2 TRACK MODE */
SBIT(AD2EN, 0xE8, 7); /* ADC 2 ENABLE */
/* P6 0xE8 */
SBIT(P6_0, 0xE8, 0);
SBIT(P6_1, 0xE8, 1);
SBIT(P6_2, 0xE8, 2);
SBIT(P6_3, 0xE8, 3);
SBIT(P6_4, 0xE8, 4);
SBIT(P6_5, 0xE8, 5);
SBIT(P6_6, 0xE8, 6);
SBIT(P6_7, 0xE8, 7);
/* SPI0CN 0xF8 */
SBIT(SPIEN, 0xF8, 0); /* SPI 0 SPI ENABLE */
SBIT(TXBMT, 0xF8, 1); /* SPI 0 TX BUFFER EMPTY FLAG */
SBIT(NSSMD0, 0xF8, 2); /* SPI 0 SLAVE SELECT MODE 0 */
SBIT(NSSMD1, 0xF8, 3); /* SPI 0 SLAVE SELECT MODE 1 */
SBIT(RXOVRN, 0xF8, 4); /* SPI 0 RX OVERRUN FLAG */
SBIT(MODF, 0xF8, 5); /* SPI 0 MODE FAULT FLAG */
SBIT(WCOL, 0xF8, 6); /* SPI 0 WRITE COLLISION FLAG */
SBIT(SPIF, 0xF8, 7); /* SPI 0 INTERRUPT FLAG */
/* CAN0CN 0xF8 */
SBIT(CANINIT, 0xF8, 0); /* CAN INITIALIZATION */
SBIT(CANIE, 0xF8, 1); /* CAN MODULE INTERRUPT ENABLE */
SBIT(CANSIE, 0xF8, 2); /* CAN STATUS CHANGE INTERRUPT ENABLE */
SBIT(CANEIE, 0xF8, 3); /* CAN ERROR INTERRUPT ENABLE */
SBIT(CANIF, 0xF8, 4); /* CAN INTERRUPT FLAG */
SBIT(CANDAR, 0xF8, 5); /* CAN DISABLE AUTOMATIC RETRANSMISSION */
SBIT(CANCCE, 0xF8, 6); /* CAN CONFIGURATION CHANGE ENABLE */
SBIT(CANTEST, 0xF8, 7); /* CAN TEST MODE ENABLE */
/* DMA0CF 0xF8 */
SBIT(DMA0EO, 0xF8, 0); /* END-OF-OPERATION FLAG */
SBIT(DMA0EOE, 0xF8, 1); /* END-OF-OPERATION INTERRUPT ENABLE */
SBIT(DMA0CI, 0xF8, 2); /* REPEAT COUNTER OVERFLOW FLAG */
SBIT(DMA0CIE, 0xF8, 3); /* REPEAT COUNTER OVERFLOW INTERRUPT ENABLE */
SBIT(DMA0XBY, 0xF8, 6); /* OFF-CHIP XRAM BUSY FLAG */
SBIT(DMA0HLT, 0xF8, 7); /* HALT DMA0 OFF-CHIP XRAM ACCESS */
/* P7 0xF8 */
SBIT(P7_0, 0xF8, 0);
SBIT(P7_1, 0xF8, 1);
SBIT(P7_2, 0xF8, 2);
SBIT(P7_3, 0xF8, 3);
SBIT(P7_4, 0xF8, 4);
SBIT(P7_5, 0xF8, 5);
SBIT(P7_6, 0xF8, 6);
SBIT(P7_7, 0xF8, 7);
/* Predefined SFR Bit Masks */
#define IDLE 0x01 /* PCON */
#define STOP 0x02 /* PCON */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
/* SFR PAGE DEFINITIONS */
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
#define CPT2_PAGE 0x03 /* COMPARATOR 2 */
#define UART0_PAGE 0x00 /* UART 0 */
#define UART1_PAGE 0x01 /* UART 1 */
#define SPI0_PAGE 0x00 /* SPI 0 */
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
#define ADC0_PAGE 0x00 /* ADC 0 */
#define ADC1_PAGE 0x01 /* ADC 1 */
#define ADC2_PAGE 0x02 /* ADC 2 */
#define SMB0_PAGE 0x00 /* SMBUS 0 */
#define TMR2_PAGE 0x00 /* TIMER 2 */
#define TMR3_PAGE 0x01 /* TIMER 3 */
#define TMR4_PAGE 0x02 /* TIMER 4 */
#define DAC0_PAGE 0x00 /* DAC 0 */
#define DAC1_PAGE 0x01 /* DAC 1 */
#define PCA0_PAGE 0x00 /* PCA 0 */
#define DMA0_PAGE 0x03 /* DMA 0 */
#define CAN0_PAGE 0x01 /* CAN 0 */
#endif

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/*---------------------------------------------------------------------------
C8051F120.h - Register Declarations for the Cygnal/SiLabs C8051F12x-F13x
Processor Range
Copyright (C) 2003, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F120_H
#define C8051F120_H
/* BYTE Registers */
/* All Pages */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x84) SFRPAGE ; /* SFR PAGE SELECT */
__sfr __at (0x85) SFRNEXT ; /* SFR STACK NEXT PAGE */
__sfr __at (0x86) SFRLAST ; /* SFR STACK LAST PAGE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) PSBANK ; /* FLASH BANK SELECT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
/* Page 0x00 */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* TIMER 0/1 CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* FLASH WRITE/ERASE CONTROL */
__sfr __at (0x91) SSTA0 ; /* UART 0 STATUS */
__sfr __at (0x98) SCON0 ; /* UART 0 CONTROL */
__sfr __at (0x98) SCON ; /* UART 0 CONTROL */
__sfr __at (0x99) SBUF0 ; /* UART 0 BUFFER */
__sfr __at (0x99) SBUF ; /* UART 0 BUFFER */
__sfr __at (0x9A) SPI0CFG ; /* SPI 0 CONFIGURATION */
__sfr __at (0x9B) SPI0DAT ; /* SPI 0 DATA */
__sfr __at (0x9D) SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
__sfr __at (0xA1) EMI0TC ; /* EMIF TIMING CONTROL */
__sfr __at (0xA2) EMI0CN ; /* EMIF CONTROL */
__sfr __at (0xA2) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */
__sfr __at (0xA9) SADDR0 ; /* UART 0 SLAVE ADDRESS */
__sfr __at (0xB7) FLSCL ; /* FLASH SCALE */
__sfr __at (0xB9) SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
__sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
__sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
__sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
__sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
__sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xC9) TMR2CF ; /* TIMER 2 CONFIGURATION */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
__sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
__sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
__sfr __at (0xDD) PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
__sfr __at (0xDE) PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
__sfr __at (0xDF) PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
__sfr __at (0xE1) PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
__sfr __at (0xE2) PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
__sfr __at (0xEA) PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
__sfr __at (0xEB) PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
__sfr __at (0xEC) PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
__sfr __at (0xED) PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
__sfr __at (0xEE) PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF8) SPI0CN ; /* SPI 0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
__sfr __at (0xFA) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
__sfr __at (0xFD) PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
__sfr __at (0xFE) PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
/* Page 0x01 */
__sfr __at (0x88) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x89) CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
__sfr __at (0x98) SCON1 ; /* UART 1 CONTROL */
__sfr __at (0x99) SBUF1 ; /* UART 1 BUFFER */
__sfr __at (0xC8) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0xC9) TMR3CF ; /* TIMER 3 CONFIGURATION */
__sfr __at (0xCA) RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0xCD) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0xD2) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
__sfr __at (0xD3) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
__sfr __at (0xD4) DAC1CN ; /* DAC 1 CONTROL */
/* Page 0x02 */
__sfr __at (0x88) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0x89) CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
__sfr __at (0xBA) AMX2CF ; /* ADC 2 MUX CONFIGURATION */
__sfr __at (0xBB) AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
__sfr __at (0xBC) ADC2CF ; /* ADC 2 CONFIGURATION */
__sfr __at (0xBE) ADC2 ; /* ADC 2 DATA */
__sfr __at (0xC4) ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
__sfr __at (0xC6) ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
__sfr __at (0xC8) TMR4CN ; /* TIMER 4 CONTROL */
__sfr __at (0xC9) TMR4CF ; /* TIMER 4 CONFIGURATION */
__sfr __at (0xCA) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TMR4L ; /* TIMER 4 - LOW BYTE */
__sfr __at (0xCD) TMR4H ; /* TIMER 4 - HIGH BYTE */
__sfr __at (0xE8) ADC2CN ; /* ADC 2 CONTROL */
/* Page 0x03 */
__sfr __at (0x91) MAC0BL ; /* MAC0 B Register Low Byte */
__sfr __at (0x92) MAC0BH ; /* MAC0 B Register High Byte */
__sfr __at (0x93) MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
__sfr __at (0x94) MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
__sfr __at (0x95) MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
__sfr __at (0x96) MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
__sfr __at (0x97) MAC0OVR ; /* MAC0 Accumulator Overflow */
__sfr __at (0xC0) MAC0STA ; /* MAC0 Status Register */
__sfr __at (0xC1) MAC0AL ; /* MAC0 A Register Low Byte */
__sfr __at (0xC2) MAC0AH ; /* MAC0 A Register High Byte */
__sfr __at (0xC3) MAC0CF ; /* MAC0 Configuration */
__sfr __at (0xCE) MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
__sfr __at (0xCF) MAC0RNDH ; /* MAC0 Rounding Register High Byte */
/* Page 0x0F */
__sfr __at (0x88) FLSTAT ; /* FLASH STATUS */
__sfr __at (0x89) PLL0CN ; /* PLL 0 CONTROL */
__sfr __at (0x8A) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0x8B) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0x8C) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0x8D) PLL0DIV ; /* PLL 0 DIVIDER */
__sfr __at (0x8E) PLL0MUL ; /* PLL 0 MULTIPLIER */
__sfr __at (0x8F) PLL0FLT ; /* PLL 0 FILTER */
__sfr __at (0x96) SFRPGCN ; /* SFR PAGE CONTROL */
__sfr __at (0x97) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0x9A) CCH0MA ; /* CACHE MISS ACCUMULATOR */
__sfr __at (0x9C) P4MDOUT ; /* PORT 4 OUTPUT MODE */
__sfr __at (0x9D) P5MDOUT ; /* PORT 5 OUTPUT MODE */
__sfr __at (0x9E) P6MDOUT ; /* PORT 6 OUTPUT MODE */
__sfr __at (0x9F) P7MDOUT ; /* PORT 7 OUTPUT MODE */
__sfr __at (0xA1) CCH0CN ; /* CACHE CONTROL */
__sfr __at (0xA2) CCH0TN ; /* CACHE TUNING REGISTER */
__sfr __at (0xA3) CCH0LC ; /* CACHE LOCK */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xAD) P1MDIN ; /* PORT 1 INPUT MODE */
__sfr __at (0xB7) FLACL ; /* FLASH ACCESS LIMIT */
__sfr __at (0xC8) P4 ; /* PORT 4 */
__sfr __at (0xD8) P5 ; /* PORT 5 */
__sfr __at (0xE1) XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
__sfr __at (0xE8) P6 ; /* PORT 6 */
__sfr __at (0xF8) P7 ; /* PORT 7 */
/* WORD/DWORD Registers */
/* Page 0x00 */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA 0 TIMER COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE WORD */
__sfr16 __at (0xFEFD) PCA0CP1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE WORD */
__sfr16 __at (0xEAE9) PCA0CP2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE WORD */
__sfr16 __at (0xECEB) PCA0CP3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE WORD */
__sfr16 __at (0xEEED) PCA0CP4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE WORD */
__sfr16 __at (0xE2E1) PCA0CP5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE WORD */
/* Page 0x01 */
__sfr16 __at (0xCDCC) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0xCBCA) RCAP3 ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xD3D2) DAC1 ; /* DAC 1 REGISTER WORD */
/* Page 0x02 */
__sfr16 __at (0xCDCC) TMR4 ; /* TIMER 4 COUNTER */
__sfr16 __at (0xCBCA) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD */
/* Page 0x03 */
__sfr16 __at (0xC2C1) MAC0A ; /* MAC0 A Register */
/* No sfr16 definition for MAC0B because MAC0BL must be written last */
__sfr32 __at (0x96959493) MAC0ACC ; /* MAC0 Accumulator */
__sfr16 __at (0xCFCE) MAC0RND ; /* MAC0 Rounding Register */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
/* CPT0CN 0x88 */
__sbit __at (0x88) CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
__sbit __at (0x89) CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
__sbit __at (0x8A) CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
__sbit __at (0x8B) CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
__sbit __at (0x8C) CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
__sbit __at (0x8D) CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
__sbit __at (0x8E) CP0OUT ; /* COMPARATOR 0 OUTPUT */
__sbit __at (0x8F) CP0EN ; /* COMPARATOR 0 ENABLE */
/* CPT1CN 0x88 */
__sbit __at (0x88) CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
__sbit __at (0x89) CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
__sbit __at (0x8A) CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
__sbit __at (0x8B) CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
__sbit __at (0x8C) CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
__sbit __at (0x8D) CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
__sbit __at (0x8E) CP1OUT ; /* COMPARATOR 1 OUTPUT */
__sbit __at (0x8F) CP1EN ; /* COMPARATOR 1 ENABLE */
/* FLSTAT 0x88 */
__sbit __at (0x88) FLHBUSY ; /* FLASH BUSY */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON0 0x98 */
__sbit __at (0x98) RI0 ; /* UART 0 RX INTERRUPT FLAG */
__sbit __at (0x98) RI ; /* UART 0 RX INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* UART 0 TX INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* UART 0 TX INTERRUPT FLAG */
__sbit __at (0x9A) RB80 ; /* UART 0 RX BIT 8 */
__sbit __at (0x9B) TB80 ; /* UART 0 TX BIT 8 */
__sbit __at (0x9C) REN0 ; /* UART 0 RX ENABLE */
__sbit __at (0x9C) REN ; /* UART 0 RX ENABLE */
__sbit __at (0x9D) SM20 ; /* UART 0 MULTIPROCESSOR EN */
__sbit __at (0x9E) SM10 ; /* UART 0 MODE 1 */
__sbit __at (0x9F) SM00 ; /* UART 0 MODE 0 */
/* SCON1 0x98 */
__sbit __at (0x98) RI1 ; /* UART 1 RX INTERRUPT FLAG */
__sbit __at (0x99) TI1 ; /* UART 1 TX INTERRUPT FLAG */
__sbit __at (0x9A) RB81 ; /* UART 1 RX BIT 8 */
__sbit __at (0x9B) TB81 ; /* UART 1 TX BIT 8 */
__sbit __at (0x9C) REN1 ; /* UART 1 RX ENABLE */
__sbit __at (0x9D) MCE1 ; /* UART 1 MCE */
__sbit __at (0x9F) S1MODE ; /* UART 1 MODE */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* UART0 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* UART0 INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
__sbit __at (0xBC) PS0 ; /* SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
__sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
__sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
__sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
__sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
__sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
/* MAC0STA 0xC0 */
__sbit __at (0xC0) MAC0N ; /* MAC 0 NEGATIVE FLAG */
__sbit __at (0xC1) MAC0SO ; /* MAC 0 SOFT OVERFLOW FLAG */
__sbit __at (0xC2) MAC0Z ; /* MAC 0 ZERO FLAG */
__sbit __at (0xC3) MAC0HO ; /* MAC 0 HARD OVERFLOW FLAG */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) CPRL2 ; /* TIMER 2 CAPTURE SELECT */
__sbit __at (0xC9) CT2 ; /* TIMER 2 COUNTER SELECT */
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
__sbit __at (0xCE) EXF2 ; /* TIMER 2 EXTERNAL FLAG */
__sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
/* TMR3CN 0xC8 */
__sbit __at (0xC8) CPRL3 ; /* TIMER 3 CAPTURE SELECT */
__sbit __at (0xC9) CT3 ; /* TIMER 3 COUNTER SELECT */
__sbit __at (0xCA) TR3 ; /* TIMER 3 ON/OFF CONTROL */
__sbit __at (0xCB) EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
__sbit __at (0xCE) EXF3 ; /* TIMER 3 EXTERNAL FLAG */
__sbit __at (0xCF) TF3 ; /* TIMER 3 OVERFLOW FLAG */
/* TMR4CN 0xC8 */
__sbit __at (0xC8) CPRL4 ; /* TIMER 4 CAPTURE SELECT */
__sbit __at (0xC9) CT4 ; /* TIMER 4 COUNTER SELECT */
__sbit __at (0xCA) TR4 ; /* TIMER 4 ON/OFF CONTROL */
__sbit __at (0xCB) EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
__sbit __at (0xCE) EXF4 ; /* TIMER 4 EXTERNAL FLAG */
__sbit __at (0xCF) TF4 ; /* TIMER 4 OVERFLOW FLAG */
/* P4 0xC8 */
__sbit __at (0xC8) P4_0 ;
__sbit __at (0xC9) P4_1 ;
__sbit __at (0xCA) P4_2 ;
__sbit __at (0xCB) P4_3 ;
__sbit __at (0xCC) P4_4 ;
__sbit __at (0xCD) P4_5 ;
__sbit __at (0xCE) P4_6 ;
__sbit __at (0xCF) P4_7 ;
/* PSW 0xD0 */
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
__sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* CARRY FLAG */
/* PCA0CN D8H */
__sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
__sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
__sbit __at (0xDD) CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
__sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
__sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
/* P5 0xD8 */
__sbit __at (0xD8) P5_0 ;
__sbit __at (0xD9) P5_1 ;
__sbit __at (0xDA) P5_2 ;
__sbit __at (0xDB) P5_3 ;
__sbit __at (0xDC) P5_4 ;
__sbit __at (0xDD) P5_5 ;
__sbit __at (0xDE) P5_6 ;
__sbit __at (0xDF) P5_7 ;
/* ADC0CN E8H */
__sbit __at (0xE8) AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
__sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
__sbit __at (0xEA) AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
__sbit __at (0xEB) AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
__sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
__sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
__sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
/* ADC2CN E8H */
__sbit __at (0xE8) AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
__sbit __at (0xE9) AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
__sbit __at (0xEA) AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
__sbit __at (0xEB) AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
__sbit __at (0xEC) AD2BUSY ; /* ADC 2 BUSY FLAG */
__sbit __at (0xED) AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
__sbit __at (0xEE) AD2TM ; /* ADC 2 TRACK MODE */
__sbit __at (0xEF) AD2EN ; /* ADC 2 ENABLE */
/* P6 0xE8 */
__sbit __at (0xE8) P6_0 ;
__sbit __at (0xE9) P6_1 ;
__sbit __at (0xEA) P6_2 ;
__sbit __at (0xEB) P6_3 ;
__sbit __at (0xEC) P6_4 ;
__sbit __at (0xED) P6_5 ;
__sbit __at (0xEE) P6_6 ;
__sbit __at (0xEF) P6_7 ;
/* SPI0CN F8H */
__sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
__sbit __at (0xFA) NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
/* P7 0xF8 */
__sbit __at (0xF8) P7_0 ;
__sbit __at (0xF9) P7_1 ;
__sbit __at (0xFA) P7_2 ;
__sbit __at (0xFB) P7_3 ;
__sbit __at (0xFC) P7_4 ;
__sbit __at (0xFD) P7_5 ;
__sbit __at (0xFE) P7_6 ;
__sbit __at (0xFF) P7_7 ;
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define PINRSF 0x01 /* RSTSRC */
#define PORSF 0x02 /* RSTSRC */
#define MCDRSF 0x04 /* RSTSRC */
#define WDTRSF 0x08 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define C0RSEF 0x20 /* RSTSRC */
#define CNVRSEF 0x40 /* RSTSRC */
/* SFR PAGE DEFINITIONS */
#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
#define CPT0_PAGE 0x01 /* COMPARATOR 0 */
#define CPT1_PAGE 0x02 /* COMPARATOR 1 */
#define UART0_PAGE 0x00 /* UART 0 */
#define UART1_PAGE 0x01 /* UART 1 */
#define SPI0_PAGE 0x00 /* SPI 0 */
#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
#define ADC0_PAGE 0x00 /* ADC 0 */
#define ADC2_PAGE 0x02 /* ADC 2 */
#define SMB0_PAGE 0x00 /* SMBUS 0 */
#define TMR2_PAGE 0x00 /* TIMER 2 */
#define TMR3_PAGE 0x01 /* TIMER 3 */
#define TMR4_PAGE 0x02 /* TIMER 4 */
#define DAC0_PAGE 0x00 /* DAC 0 */
#define DAC1_PAGE 0x01 /* DAC 1 */
#define PCA0_PAGE 0x00 /* PCA 0 */
#define PLL0_PAGE 0x0F /* PLL 0 */
#define MAC0_PAGE 0x03 /* MULTIPLY / ACCUMULATE 0 */
#endif

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/*---------------------------------------------------------------------------
C8051F200.h - Register Declarations for the Cygnal/SiLabs C8051F2xx
Processor Range
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F200_H
#define C8051F200_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER Control */
__sfr __at (0x88) TCON ; /* TIMER Control */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK Control */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W Control */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x98) SCON ; /* SERIAL PORT Control */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 Configuration */
__sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
__sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE Control */
__sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 Control */
__sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 Control */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA4) PRT0CF ; /* PORT 0 OUTPUT MODE Configuration */
__sfr __at (0xA5) PRT1CF ; /* PORT 1 OUTPUT MODE Configuration */
__sfr __at (0xA6) PRT2CF ; /* PORT 2 OUTPUT MODE Configuration */
__sfr __at (0xA7) PRT3CF ; /* PORT 3 OUTPUT MODE Configuration */
__sfr __at (0xA8) IE ; /* Interrupt Enable */
__sfr __at (0xAD) SWCINT ; /* SOFTWARE-Controlled Interrupt FLAGS */
__sfr __at (0xAD) PRT1IF ; /* SOFTWARE-Controlled Interrupt FLAGS (LEGACY NAME) */
__sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE Control (F206/F226/F236)*/
__sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR Control */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR Control */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* Interrupt Priority */
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION (Not on F230/1/6) */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 Configuration (Not on F230/1/6) */
__sfr __at (0xBE) ADC0L ; /* ADC 0 Data LOW ( F206 only ) */
__sfr __at (0xBF) ADC0H ; /* ADC 0 Data High */
__sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN Register LOW( F206 only ) */
__sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN Register (Not on F230/1/6) */
__sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN Register LOW ( F206 only ) */
__sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN Register (Not on F230/1/6) */
__sfr __at (0xC8) T2CON ; /* TIMER 2 Control */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE Register - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE Register - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 Control */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) PRT0MX ; /* PORT MUX Configuration Register 0 */
__sfr __at (0xE2) PRT1MX ; /* PORT MUX Configuration Register 1 */
__sfr __at (0xE3) PRT2MX ; /* PORT MUX Configuration Register 2 */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL Interrupt Enable 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL Interrupt Enable 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 Control (Not on F230/1/6) */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B Register */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE Configuration */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE Configuration */
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE Configuration */
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE Configuration (Not on F221/F231)*/
__sfr __at (0xF6) EIP1 ; /* EXTERNAL Interrupt Priority Register 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL Interrupt Priority Register 2 */
__sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 Control */
__sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER Control */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ; /* Port0 I/O Bits */
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* EXT. Interrupt 0 TYPE */
__sbit __at (0x89) IE0 ; /* EXT. Interrupt 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* EXT. Interrupt 1 TYPE */
__sbit __at (0x8B) IE1 ; /* EXT. Interrupt 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF Control */
__sbit __at (0x8D) TF0 ; /* TIMER 0 Overflow FLAG */
__sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF Control */
__sbit __at (0x8F) TF1 ; /* TIMER 1 Overflow FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ; /* Port1 I/O Bits */
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* RECEIVE Interrupt FLAG */
__sbit __at (0x99) TI ; /* TRANSMIT Interrupt FLAG */
__sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* RECEIVE Enable */
__sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION Enable */
__sbit __at (0x9E) SM1 ; /* SERIAL MODE Control BIT 1 */
__sbit __at (0x9F) SM0 ; /* SERIAL MODE Control BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ; /* Port2 I/O Bits */
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* EXTERNAL Interrupt 0 Enable */
__sbit __at (0xA9) ET0 ; /* TIMER 0 Interrupt Enable */
__sbit __at (0xAA) EX1 ; /* EXTERNAL Interrupt 1 Enable */
__sbit __at (0xAB) ET1 ; /* TIMER 1 Interrupt Enable */
__sbit __at (0xAC) ES ; /* SERIAL PORT Interrupt Enable */
__sbit __at (0xAD) ET2 ; /* TIMER 2 Interrupt Enable */
//------------- /* Bit 6 not used */
__sbit __at (0xAF) EA ; /* GLOBAL Interrupt Enable */
/* P2 0xB0 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ; /* Port3 I/O Bits */
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* EXTERNAL Interrupt 0 Priority */
__sbit __at (0xB9) PT0 ; /* TIMER 0 Priority */
__sbit __at (0xBA) PX1 ; /* EXTERNAL Interrupt 1 Priority */
__sbit __at (0xBB) PT1 ; /* TIMER 1 Priority */
__sbit __at (0xBC) PS ; /* SERIAL PORT Priority */
__sbit __at (0xBD) PT2 ; /* TIMER 2 Priority */
//------------- /* Bit 6 not used */
//------------- /* Bit 7 not used */
/* T2CON 0xC8 */
__sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
__sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
__sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF Control */
__sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL Enable FLAG */
__sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
__sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
__sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
__sbit __at (0xCF) TF2 ; /* TIMER 2 Overflow FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* USER FLAG 1 */
__sbit __at (0xD2) OV ; /* Overflow FLAG */
__sbit __at (0xD3) RS0 ; /* Register BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* Register BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* USER FLAG 0 */
__sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* CARRY FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) ADLJST ; /* Left Justify Data (F206 only) */
__sbit __at (0xE9) ADWINT ; /* WINDOW COMPARE Interrupt FLAG */
__sbit __at (0xEA) ADSTM0 ; /* START OF CONVERSION MODE BIT 0 */
__sbit __at (0xEB) ADSTM1 ; /* START OF CONVERSION MODE BIT 1 */
__sbit __at (0xEC) ADBUSY ; /* BUSY FLAG */
__sbit __at (0xED) ADCINT ; /* CONVERISION COMPLETE Interrupt FLAG */
__sbit __at (0xEE) ADCTM ; /* TRACK MODE */
__sbit __at (0xEF) ADCEN ; /* Enable */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI Enable */
__sbit __at (0xF9) MSTEN ; /* MASTER Enable */
__sbit __at (0xFA) SLVSEL ; /* SLAVE SELECT */
__sbit __at (0xFB) TXBSY ; /* TX BUSY FLAG */
__sbit __at (0xFC) RXOVRN ; /* RX OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* Interrupt FLAG */
#endif

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/*-------------------------------------------------------------------------
C8051F300.h - Register Declarations for the Cygnal/SiLabs C8051F30x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F300_H
#define C8051F300_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBE) ADC0 ; /* ADC 0 DATA */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
__sfr __at (0xC6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
__sfr __at (0xE3) XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF8) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* CPT0CN 0xF8 */
__sbit __at (0xF8) CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
__sbit __at (0xF9) CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
__sbit __at (0xFA) CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
__sbit __at (0xFB) CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
__sbit __at (0xFC) CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
__sbit __at (0xFD) CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
__sbit __at (0xFE) CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
__sbit __at (0xFF) CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x10 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0F 0x10 /* EIE1 */
#define ECP0R 0x20 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR1 */
#define CP0OEN 0x10 /* XBR1 */
#define CP0AE 0x20 /* XBR1 */
#define CP0AOEN 0x20 /* XBR1 */
#endif

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/*-------------------------------------------------------------------------
C8051F310.h - Register Declarations for the Cygnal/SiLabs C8051F31x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F310_H
#define C8051F310_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define ECP1 0x40 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
#define CP1E 0x40 /* XBR0 */
#define CP1AE 0x80 /* XBR0 */
#endif

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OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/C8051F320.h Normal file
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/*-------------------------------------------------------------------------
C8051F320.h - Register Declarations for the Cygnal/SiLabs C8051F32x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F320_H
#define C8051F320_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCC) T2SOF ; /* TMR2CN.4 - TIMER 2 START_OF_FRAME CAPTURE ENA */
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define ECP1 0x40 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
#define CP1E 0x40 /* XBR0 */
#define CP1AE 0x80 /* XBR0 */
#endif

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/*-------------------------------------------------------------------------
C8051F326.h - Register Declarations for the Cygnal/SiLabs C8051F326/7
Processor Range
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F326_H
#define C8051F326_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x91) SBCON0 ; /* BAUDRATE GENERATOR 0 CONTROL */
__sfr __at (0x93) SBRLL0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE - LOW BYTE */
__sfr __at (0x94) SBRLH0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE - HIGH BYTE */
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
__sfr __at (0x98) SCON ; /* UART0 CONTROL */
__sfr __at (0x98) SCON0 ; /* UART0 CONTROL */
__sfr __at (0x99) SBUF ; /* UART0 BUFFER */
__sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */
__sfr __at (0x9A) SMOD0 ; /* UART0 MODE */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE2) GPIOCN ; /* GLOBAL PORT I/O CONTROL */
__sfr __at (0xE3) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0x9493) SBRL0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RBX0 ; /* SCON.2 - EXTRA RECEIVE BIT */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TBX0 ; /* SCON.3 - EXTRA TRANSMIT BIT */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9E) PERR0 ; /* SCON.6 - PARITY ERROR FLAG */
__sbit __at (0x9F) OVR0 ; /* SCON.7 - RECEIVE FIFO OVERRUN FLAG */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
__sbit __at (0xB0) P3_0 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T0M 0x04 /* CKCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define EUSB0 0x02 /* EIE1 */
#define EVBUS 0x01 /* EIE2 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#endif

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/*-------------------------------------------------------------------------
C8051F330.h - Register Declarations for the Cygnal/SiLabs C8051F33x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F330_H
#define C8051F330_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
__sfr __at (0x97) IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0x9796) IDA0 ; /* CURRENT MODE DAC 0 DATA WORD */
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
#endif

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/*-------------------------------------------------------------------------
C8051F336.h - Register Declarations for the SiLabs C8051F336/7/8/9
Processor Range
Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F336_H
#define C8051F336_H
#include <compiler.h>
/* BYTE Registers */
SFR( P0, 0x80 ) ; /* PORT 0 */
SFR( SP, 0x81 ) ; /* STACK POINTER */
SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
SFR( PCON, 0x87 ) ; /* POWER CONTROL */
SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
SFR( TMOD, 0x89 ) ; /* TIMER MODE */
SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
SFR( PSCTL, 0x8F ) ; /* PROGRAM STORE R/W CONTROL */
SFR( P1, 0x90 ) ; /* PORT 1 */
SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
SFR( IDA0L, 0x96 ) ; /* CURRENT MODE DAC 0 - LOW BYTE */
SFR( IDA0H, 0x97 ) ; /* CURRENT MODE DAC 0 - HIGH BYTE */
SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */
SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
SFR( P2, 0xA0 ) ; /* PORT 2 */
SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */
SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */
SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */
SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */
SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
SFR( FLSCL, 0xB6 ) ; /* FLASH MEMORY TIMING PRESCALER */
SFR( FLKEY, 0xB7 ) ; /* FLASH ACESS LIMIT */
SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
SFR( IDA0CN, 0xB9 ) ; /* CURRENT MODE DAC 0 - CONTROL */
SFR( AMX0N, 0xBA ) ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */
SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */
SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */
SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */
SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */
SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */
SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */
SFR( SMB0ADR, 0xD7 ) ; /* SMBUS SLAVE ADDRESS */
SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
SFR( OSCLCN, 0xE3 ) ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
SFR( SMB0ADM, 0xE7 ) ; /* SMBUS SLAVE ADDRESS MASK */
SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
SFR( P1MAT, 0xED ) ; /* PORT 1 MATCH REGISTER */
SFR( P1MASK, 0xEE ) ; /* PORT 1 MASK REGISTER */
SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
SFR( B, 0xF0 ) ; /* B REGISTER */
SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE */
SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
SFR( PCA0PWM, 0xF7 ) ; /* PCA PWM CONFIGURATION */
SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */
SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
SFR( P0MAT, 0xFD ) ; /* PORT 0 MATCH REGISTER */
SFR( P0MASK, 0xFE ) ; /* PORT 0 MASK REGISTER */
SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */
SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */
SFR16E( IDA0, 0x9796 ) ; /* CURRENT MODE DAC 0 DATA WORD */
SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */
SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
/* BIT Registers */
/* P0 0x80 */
SBIT( P0_0, 0x80, 0 ) ;
SBIT( P0_1, 0x80, 1 ) ;
SBIT( P0_2, 0x80, 2 ) ;
SBIT( P0_3, 0x80, 3 ) ;
SBIT( P0_4, 0x80, 4 ) ;
SBIT( P0_5, 0x80, 5 ) ;
SBIT( P0_6, 0x80, 6 ) ;
SBIT( P0_7, 0x80, 7 ) ;
/* TCON 0x88 */
SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
SBIT( P1_0, 0x90, 0 ) ;
SBIT( P1_1, 0x90, 1 ) ;
SBIT( P1_2, 0x90, 2 ) ;
SBIT( P1_3, 0x90, 3 ) ;
SBIT( P1_4, 0x90, 4 ) ;
SBIT( P1_5, 0x90, 5 ) ;
SBIT( P1_6, 0x90, 6 ) ;
SBIT( P1_7, 0x90, 7 ) ;
/* SCON 0x98 */
SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
SBIT( P2_0, 0xA0, 0 ) ;
SBIT( P2_1, 0xA0, 1 ) ;
SBIT( P2_2, 0xA0, 2 ) ;
SBIT( P2_3, 0xA0, 3 ) ;
SBIT( P2_4, 0xA0, 4 ) ;
SBIT( P2_5, 0xA0, 5 ) ;
SBIT( P2_6, 0xA0, 6 ) ;
SBIT( P2_7, 0xA0, 7 ) ;
/* IE 0xA8 */
SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */
SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
SBIT( TF2CEN, 0xC8, 4 ) ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */
SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */
SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */
SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
/* Interrupts */
#define INT_EXT0 0 /* External Interrupt 0 */
#define INT_TIMER0 1 /* Timer0 Overflow */
#define INT_EXT1 2 /* External Interrupt 1 */
#define INT_TIMER1 3 /* Timer1 Overflow */
#define INT_UART0 4 /* Serial Port 0 */
#define INT_TIMER2 5 /* Timer2 Overflow */
#define INT_SPI0 6 /* Serial Peripheral Interface 0 */
#define INT_SMBUS0 7 /* SMBus0 Interface */
#define INT_PMAT 8 /* Port match */
#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
#define INT_PCA0 11 /* PCA0 Peripheral */
#define INT_COMPARATOR0 12 /* Comparator0 */
/* 13 Reserved */
#define INT_TIMER3 14 /* Timer3 Overflow */
#endif

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/*-------------------------------------------------------------------------
C8051F340.h - Register Declarations for the Cygnal/SiLabs C8051F34x
Processor Range
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F340_H
#define C8051F340_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x84) EMI0TC ; /* EXTERNAL MEMORY INTERFACE TIMING */
__sfr __at (0x85) EMI0CF ; /* EXTERNAL MEMORY INTERFACE CONFIGURATION */
__sfr __at (0x86) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xAC) SBCON1 ; /* UART 1 BAUDRATE GENERATOR CONTROL */
__sfr __at (0xAE) P4MDOUT ; /* PORT 4 OUTPUT MODE CONFIGURATION */
__sfr __at (0xAF) PFE0CN ; /* PREFETCH ENGINE CONTROL */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB4) SBRLL1 ; /* UART 1 BAUDRATE GENERATOR - LOW BYTE */
__sfr __at (0xB5) SBRLH1 ; /* UART 1 BAUDRATE GENERATOR - HIGH BYTE */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
__sfr __at (0xC7) P4 ; /* PORT 4 */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD2) SCON1 ; /* UART 1 CONTROL */
__sfr __at (0xD3) SBUF1 ; /* UART 1 DATA BUFFER */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
__sfr __at (0xDF) P3SKIP ; /* PORT 3 SKIP */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE5) SMOD1 ; /* UART 1 MODE */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF5) P4MDIN ; /* PORT 4 INPUT MODE CONFIGURATION */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xB5B4) SBRL1 ; /* UART 1 BAUDRATE GENERATOR WORD */
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
__sbit __at (0xB0) P3_0 ;
__sbit __at (0xB1) P3_1 ;
__sbit __at (0xB2) P3_2 ;
__sbit __at (0xB3) P3_3 ;
__sbit __at (0xB4) P3_4 ;
__sbit __at (0xB5) P3_5 ;
__sbit __at (0xB6) P3_6 ;
__sbit __at (0xB7) P3_7 ;
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xC9) T2CSS ; /* TMR2CN.1 - TIMER 2 CAPTURE SOURCE SELECT */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCC) T2CE ; /* TMR2CN.4 - TIMER 2 CAPTURE ENABLE */
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define ECP1 0x40 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP1E 0x40 /* XBR0 */
#define CP1AE 0x80 /* XBR0 */
#endif

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OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/C8051F350.h Normal file
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/*-------------------------------------------------------------------------
C8051F350.h - Register Declarations for the SiLabs C8051F35x
Processor Range
Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F350_H
#define C8051F350_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) IDA0 ; /* CURRENT MODE DAC 0 */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) ADC0DECL ; /* ADC DECIMATION LOW */
__sfr __at (0x9B) ADC0DECH ; /* ADC DECIMATION HIGH */
__sfr __at (0x9C) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xAB) ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */
__sfr __at (0xAC) ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */
__sfr __at (0xAD) ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
__sfr __at (0xBA) ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */
__sfr __at (0xBB) ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */
__sfr __at (0xBC) ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */
__sfr __at (0xBD) ADC0BUF ; /* ADC 0 BUFFER CONTROL */
__sfr __at (0xBE) CLKMUL ; /* CLOCK MULTIPLIER */
__sfr __at (0xBF) ADC0DAC ; /* ADC 0 OFFSET DAC */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0L ; /* ADC 0 OUTPUT LOW BYTE */
__sfr __at (0xC4) ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */
__sfr __at (0xC5) ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */
__sfr __at (0xC6) ADC0MUX ; /* ADC 0 MULTIPLEXER */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD7) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xDD) IDA1 ; /* CURRENT MODE DAC 1 */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE8) ADC0STA ; /* ADC 0 STATUS */
__sfr __at (0xE9) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xEA) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xEB) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEC) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xED) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEE) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) ADC0MD ; /* ADC 0 MODE */
__sfr __at (0xF4) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) ADC0CLK ; /* ADC 0 CLOCK */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xFC) ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */
__sfr __at (0xFD) ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */
__sfr __at (0xFE) ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0x9B9A) ADC0DEC ; /* ADC 0 DECIMATION RATIO REGISTER WORD */
/* Unfortunately the C8051F350 does not have an sfr that always reads 0x00 and */
/* ignores what is written to it. That could have enabled sfr32 definitions for */
/* the 24 bit ADC0 sfr combinations. */
__sfr16 __at (0xC5C4) ADC0 ; /* 16 bit ADC 0 SINC3 FILTER OUTPUT WORD */
__sfr16 __at (0xFEFD) ADC0F ; /* 16 bit ADC 0 FAST FILTER OUTPUT WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xEAE9) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xECEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xEEED) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0STA 0xE8 */
__sbit __at (0xE8) AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */
__sbit __at (0xE9) AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */
__sbit __at (0xEA) AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */
__sbit __at (0xEB) AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */
__sbit __at (0xEC) AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */
__sbit __at (0xEF) AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
#endif

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/*-------------------------------------------------------------------------
C8051F360.h - Register Declarations for the SiLabs C8051F36x
Processor Range
Copyright (C) 2007, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F360_H
#define C8051F360_H
#include <compiler.h>
/* All Pages */
SFR(P0, 0x80); // Port 0
SBIT(P0_0, 0x80, 0); // Port 0 bit 0
SBIT(P0_1, 0x80, 1); // Port 0 bit 1
SBIT(P0_2, 0x80, 2); // Port 0 bit 2
SBIT(P0_3, 0x80, 3); // Port 0 bit 3
SBIT(P0_4, 0x80, 4); // Port 0 bit 4
SBIT(P0_5, 0x80, 5); // Port 0 bit 5
SBIT(P0_6, 0x80, 6); // Port 0 bit 6
SBIT(P0_7, 0x80, 7); // Port 0 bit 7
SFR(SP, 0x81); // Stack Pointer
SFR(DPL, 0x82); // Data Pointer Low Byte
SFR(DPH, 0x83); // Data Pointer High Byte
SFR(SFRNEXT, 0x85); // SFR Stack Next Page
SFR(SFRLAST, 0x86); // SFR Stack Last Page
SFR(PCON, 0x87); // Power Mode Control
SFR(TCON, 0x88); // Timer Control
SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
SBIT(TR0, 0x88, 4); // Timer 0 Run Control
SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
SBIT(TR1, 0x88, 6); // Timer 1 Run Control
SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
SFR(TMOD, 0x89); // Timer Mode
SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
SFR(CKCON, 0x8E); // Clock Control
SFR(P1, 0x90); // Port 1
SBIT(P1_0, 0x90, 0); // Port 1 bit 0
SBIT(P1_1, 0x90, 1); // Port 1 bit 1
SBIT(P1_2, 0x90, 2); // Port 1 bit 2
SBIT(P1_3, 0x90, 3); // Port 1 bit 3
SBIT(P1_4, 0x90, 4); // Port 1 bit 4
SBIT(P1_5, 0x90, 5); // Port 1 bit 5
SBIT(P1_6, 0x90, 6); // Port 1 bit 6
SBIT(P1_7, 0x90, 7); // Port 1 bit 7
SFR(TMR3CN, 0x91); // Timer 3 Control
SFR16(TMR3RL, 0x92); // Timer 3 Reload Register Word
SFR(TMR3RLL, 0x92); // Timer 3 Reload Register Low Byte
SFR(TMR3RLH, 0x93); // Timer 3 Reload Register High Byte
SFR16(TMR3, 0x94); // Timer 3 Word
SFR(TMR3L, 0x94); // Timer 3 Low Byte
SFR(TMR3H, 0x95); // Timer 3 High Byte
SFR16(IDA0, 0x96); // IDAC 0 Word
SFR(IDA0L, 0x96); // IDAC 0 Low Byte
SFR(IDA0H, 0x97); // IDAC 0 High Byte
SFR(SCON0, 0x98); // Serial Port 0 Control
SBIT(RI0, 0x98, 0); // Receive Interrupt Flag
SBIT(TI0, 0x98, 1); // Transmit Interrupt Flag
SBIT(RB80, 0x98, 2); // Ninth Receive Bit
SBIT(TB80, 0x98, 3); // Ninth Transmission Bit
SBIT(REN0, 0x98, 4); // Receive Enable
SBIT(MCE0, 0x98, 5); // Multiprocessor Communication Enable
SBIT(S0MODE, 0x98, 7); // Serial Port 0 Operation Mode
SFR(SBUF0, 0x99); // Serial Port 0 Data Buffer
SFR(CPT1CN, 0x9A); // Comparator 1 Control
SFR(CPT0CN, 0x9B); // Comparator 0 Control
SFR(CPT1MD, 0x9C); // Comparator 1 Mode Selection
SFR(CPT0MD, 0x9D); // Comparator 0 Mode Selection
SFR(CPT1MX, 0x9E); // Comparator 1 MUX Selection
SFR(CPT0MX, 0x9F); // Comparator 0 MUX Selection
SFR(P2, 0xA0); // Port 2
SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
SFR(SPI0CFG, 0xA1); // SPI Configuration
SFR(SPI0CKR, 0xA2); // SPI Clock Rate Control
SFR(SPI0DAT, 0xA3); // SPI Data
SFR(SFRPAGE, 0xA7); // SFR Page Select
SFR(IE, 0xA8); // Interrupt Enable
SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
SBIT(ES0, 0xA8, 4); // Enable Serial Port Interrupt
SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
SBIT(ESPI0, 0xA8, 6); // Enable SPI0 Interrupt
SBIT(EA, 0xA8, 7); // Global Interrupt Enable
SFR(EMI0CN, 0xAA); // EMIF Control
SFR(_XPAGE, 0xAA); // SDCC: XDATA/PDATA Page
SFR(P3, 0xB0); // Port 3
SBIT(P3_0, 0xB0, 0); // Port 3 bit 0
SBIT(P3_1, 0xB0, 1); // Port 3 bit 1
SBIT(P3_2, 0xB0, 2); // Port 3 bit 2
SBIT(P3_3, 0xB0, 3); // Port 3 bit 3
SBIT(P3_4, 0xB0, 4); // Port 3 bit 4
SBIT(P3_5, 0xB0, 5); // Port 3 bit 5
SBIT(P3_6, 0xB0, 6); // Port 3 bit 6
SBIT(P3_7, 0xB0, 7); // Port 3 bit 7
SFR(P4, 0xB5); // Port 4
SFR(IP, 0xB8); // Interrupt Priority
SBIT(PX0, 0xB8, 0); // External Interrupt 0 Priority
SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt Priority
SBIT(PX1, 0xB8, 2); // External Interrupt 1 Priority
SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt Priority
SBIT(PS0, 0xB8, 4); // Serial Port Interrupt Priority
SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt Priority
SBIT(PSPI0, 0xB8, 6); // SPI0 Interrupt Priority
SFR(IDA0CN, 0xB9); // IDAC 0 Control
SFR(AMX0N, 0xBA); // AMUX 0 Negative Channel Select
SFR(AMX0P, 0xBB); // AMUX 0 Positive Channel Select
SFR(ADC0CF, 0xBC); // ADC0 Configuration
SFR16(ADC0, 0xBD); // ADC0 Word
SFR(ADC0L, 0xBD); // ADC0 Low Byte
SFR(ADC0H, 0xBE); // ADC0 High Byte
SFR(SMB0CN, 0xC0); // SMBus Control
SBIT(SI, 0xC0, 0); // SMBus Interrupt Flag
SBIT(ACK, 0xC0, 1); // SMBus Acknowledge Flag
SBIT(ARBLOST, 0xC0, 2); // SMBus Arbitration Lost Indicator
SBIT(ACKRQ, 0xC0, 3); // SMBus Acknowledge Request
SBIT(STO, 0xC0, 4); // SMBus Stop Flag
SBIT(STA, 0xC0, 5); // SMBus Start Flag
SBIT(TXMODE, 0xC0, 6); // SMBus Transmit Mode Indicator
SBIT(MASTER, 0xC0, 7); // SMBus Master/Slave Indicator
SFR(SMB0CF, 0xC1); // SMBus Configuration
SFR(SMB0DAT, 0xC2); // SMBus Data
SFR16(ADC0GT, 0xC3); // ADC0 Greater-Than Data Word
SFR(ADC0GTL, 0xC3); // ADC0 Greater-Than Data Low Byte
SFR(ADC0GTH, 0xC4); // ADC0 Greater-Than Data High Byte
SFR16(ADC0LT, 0xC5); // ADC0 Less-Than Data Word
SFR(ADC0LTL, 0xC5); // ADC0 Less-Than Data Low Byte
SFR(ADC0LTH, 0xC6); // ADC0 Less-Than Data High Byte
SFR(TMR2CN, 0xC8); // Timer/Counter 2 Control
SBIT(T2XCLK, 0xC8, 0); // Timer 2 External Clock Select
SBIT(TR2, 0xC8, 2); // Timer 2 Run Control
SBIT(T2SPLIT, 0xC8, 3); // Timer 2 Split Mode Enable
SBIT(TF2CEN, 0xC8, 4); // Timer 2 Low-Frequency Oscillator Capture Enable
SBIT(TF2LEN, 0xC8, 5); // Timer 2 Low Byte Interrupt Enable
SBIT(TF2L, 0xC8, 6); // Timer 2 Low Byte Overflow Flag
SBIT(TF2H, 0xC8, 7); // Timer 2 High Byte Overflow Flag
SFR16(TMR2RL, 0xCA); // Timer/Counter 2 Reload Word
SFR(TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low Byte
SFR(TMR2RLH, 0xCB); // Timer/Counter 2 Reload High Byte
SFR16(TMR2, 0xCC); // Timer/Counter 2 Word
SFR(TMR2L, 0xCC); // Timer/Counter 2 Low Byte
SFR(TMR2H, 0xCD); // Timer/Counter 2 High Byte
SFR(PSW, 0xD0); // Program Status Word
SBIT(P, 0xD0, 0); // Parity Flag
SBIT(F1, 0xD0, 1); // User-Defined Flag
SBIT(OV, 0xD0, 2); // Overflow Flag
SBIT(RS0, 0xD0, 3); // Register Bank Select 0
SBIT(RS1, 0xD0, 4); // Register Bank Select 1
SBIT(F0, 0xD0, 5); // User-Defined Flag
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
SBIT(CY, 0xD0, 7); // Carry Flag
SFR(REF0CN, 0xD1); // Voltage Reference Control
SFR(PCA0CN, 0xD8); // PCA Control
SBIT(CCF0, 0xD8, 0); // PCA Module 0 Capture/Compare Flag
SBIT(CCF1, 0xD8, 1); // PCA Module 1 Capture/Compare Flag
SBIT(CCF2, 0xD8, 2); // PCA Module 2 Capture/Compare Flag
SBIT(CCF3, 0xD8, 3); // PCA Module 3 Capture/Compare Flag
SBIT(CCF4, 0xD8, 4); // PCA Module 4 Capture/Compare Flag
SBIT(CCF5, 0xD8, 5); // PCA Module 5 Capture/Compare Flag
SBIT(CR, 0xD8, 6); // PCA Counter/Timer Run Control
SBIT(CF, 0xD8, 7); // PCA Counter/Timer Overflow Flag
SFR(PCA0MD, 0xD9); // PCA Mode
SFR(PCA0CPM0, 0xDA); // PCA Module 0 Mode
SFR(PCA0CPM1, 0xDB); // PCA Module 1 Mode
SFR(PCA0CPM2, 0xDC); // PCA Module 2 Mode
SFR(PCA0CPM3, 0xDD); // PCA Module 3 Mode
SFR(PCA0CPM4, 0xDE); // PCA Module 4 Mode
SFR(PCA0CPM5, 0xDF); // PCA Module 5 Mode
SFR(ACC, 0xE0); // Accumulator
SFR(IT01CF, 0xE4); // INT0/INT1 Configuration
SFR(EIE1, 0xE6); // Extended Interrupt Enable 1
SFR(EIE2, 0xE7); // Extended Interrupt Enable 2
SFR(ADC0CN, 0xE8); // ADC0 Control
SBIT(AD0CM0, 0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
SBIT(AD0CM1, 0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
SBIT(AD0CM2, 0xE8, 2); // ADC0 Conversion Start Mode Select Bit 2
SBIT(AD0WINT, 0xE8, 3); // ADC0 Window Compare Interrupt Flag
SBIT(AD0BUSY, 0xE8, 4); // ADC0 Busy Bit
SBIT(AD0INT, 0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
SBIT(AD0TM, 0xE8, 6); // ADC0 Track Mode Bit
SBIT(AD0EN, 0xE8, 7); // ADC0 Enable Bit
SFR16(PCA0CP1, 0xE9); // PCA Capture 1 Word
SFR(PCA0CPL1, 0xE9); // PCA Capture 1 Low Byte
SFR(PCA0CPH1, 0xEA); // PCA Capture 1 High Byte
SFR16(PCA0CP2, 0xEB); // PCA Capture 2 Word
SFR(PCA0CPL2, 0xEB); // PCA Capture 2 Low Byte
SFR(PCA0CPH2, 0xEC); // PCA Capture 2 High Byte
SFR16(PCA0CP3, 0xED); // PCA Capture 3 Word
SFR(PCA0CPL3, 0xED); // PCA Capture 3 Low Byte
SFR(PCA0CPH3, 0xEE); // PCA Capture 3 High Byte
SFR(RSTSRC, 0xEF); // Reset Source Configuration/Status
SFR(B, 0xF0); // B Register
SFR16(PCA0CP5, 0xF5); // PCA Capture 5 Word
SFR(PCA0CPL5, 0xF5); // PCA Capture 5 Low Byte
SFR(PCA0CPH5, 0xF6); // PCA Capture 5 High Byte
SFR(SPI0CN, 0xF8); // SPI0 Control
SBIT(SPIEN, 0xF8, 0); // SPI0 Enable
SBIT(TXBMT, 0xF8, 1); // SPI0 Transmit Buffer Empty
SBIT(NSSMD0, 0xF8, 2); // SPI0 Slave Select Mode Bit 0
SBIT(NSSMD1, 0xF8, 3); // SPI0 Slave Select Mode Bit 1
SBIT(RXOVRN, 0xF8, 4); // SPI0 Receive Overrun Flag
SBIT(MODF, 0xF8, 5); // SPI0 Mode Fault Flag
SBIT(WCOL, 0xF8, 6); // SPI0 Write Collision Flag
SBIT(SPIF, 0xF8, 7); // SPI0 Interrupt Flag
SFR16(PCA0, 0xF9); // PCA Counter Word
SFR(PCA0L, 0xF9); // PCA Counter Low Byte
SFR(PCA0H, 0xFA); // PCA Counter High Byte
SFR16(PCA0CP0, 0xFB); // PCA Capture 0 Word
SFR(PCA0CPL0, 0xFB); // PCA Capture 0 Low Byte
SFR(PCA0CPH0, 0xFC); // PCA Capture 0 High Byte
SFR16(PCA0CP4, 0xFD); // PCA Capture 4 Word
SFR(PCA0CPL4, 0xFD); // PCA Capture 4 Low Byte
SFR(PCA0CPH4, 0xFE); // PCA Capture 4 High Byte
SFR(VDM0CN, 0xFF); // VDD Monitor Control
/* Page 0x00 */
SFR(PSCTL, 0x8F); // Program Store R/W Control
SFR16(MAC0A, 0xA4); // MAC0 A Register Word
SFR(MAC0AL, 0xA4); // MAC0 A Register Low Byte
SFR(MAC0AH, 0xA5); // MAC0 A Register High Byte
SFR16(MAC0RND, 0xAE); // MAC0 Rounding Register Word
SFR(MAC0RNDL, 0xAE); // MAC0 Rounding Register Low Byte
SFR(MAC0RNDH, 0xAF); // MAC0 Rounding Register High Byte
SFR(P2MAT, 0xB1); // Port 2 Match
SFR(P2MASK, 0xB2); // Port 2 Mask
SFR(FLSCL, 0xB6); // Flash Scale
SFR(FLKEY, 0xB7); // Flash Lock and Key
SFR(MAC0STA, 0xCF); // MAC0 Status Register
SFR32(MAC0ACC, 0xD2); // MAC0 Accumulator Long Word
SFR(MAC0ACC0, 0xD2); // MAC0 Accumulator Byte 0 (LSB)
SFR(MAC0ACC1, 0xD3); // MAC0 Accumulator Byte 1
SFR(MAC0ACC2, 0xD4); // MAC0 Accumulator Byte 2
SFR(MAC0ACC3, 0xD5); // MAC0 Accumulator Byte 3 (MSB)
SFR(MAC0OVR, 0xD6); // MAC0 Accumulator Overflow
SFR(MAC0CF, 0xD7); // MAC0 Configuration
SFR(P1MAT, 0xE1); // Port 1 Match
SFR(P1MASK, 0xE2); // Port 1 Mask
// No sfr16 definition for MAC0B because MAC0BL must be written last
SFR(MAC0BL, 0xF1); // MAC0 B Register Low Byte
SFR(MAC0BH, 0xF2); // MAC0 B Register High Byte
SFR(P0MAT, 0xF3); // Port 0 Match
SFR(P0MASK, 0xF4); // Port 0 Mask
/* Page 0x0F */
SFR(CCH0CN, 0x84); // Cache Control
SFR(CLKSEL, 0x8F); // Clock Select
SFR(P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
SFR(P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
SFR(P2MDOUT, 0xA6); // Port 2 Output Mode Configuration
SFR(PLL0DIV, 0xA9); // PLL Divider
SFR(FLSTAT, 0xAC); // Flash Status
SFR(OSCLCN, 0xAD); // Internal Low-Frequency Oscillator Control
SFR(P4MDOUT, 0xAE); // Port 4 Output Mode Configuration
SFR(P3MDOUT, 0xAF); // Port 3 Output Mode Configuration
SFR(PLL0MUL, 0xB1); // PLL Multiplier
SFR(PLL0FLT, 0xB2); // PLL Filter
SFR(PLL0CN, 0xB3); // PLL Control
SFR(OSCXCN, 0xB6); // External Oscillator Control
SFR(OSCICN, 0xB7); // Internal Oscillator Control
SFR(OSCICL, 0xBF); // Internal Oscillator Calibration
SFR(EMI0CF, 0xC7); // EMIF Configuration
SFR(CCH0TN, 0xC9); // Cache Tuning
SFR(EIP1, 0xCE); // Extended Interrupt Priority 1
SFR(EIP2, 0xCF); // Extended Interrupt Priority 2
SFR(CCH0LC, 0xD2); // Cache Lock
SFR(CCH0MA, 0xD3); // Cache Miss Accumulator
SFR(P0SKIP, 0xD4); // Port 0 Skip
SFR(P1SKIP, 0xD5); // Port 1 Skip
SFR(P2SKIP, 0xD6); // Port 2 Skip
SFR(P3SKIP, 0xD7); // Port 3 Skip
SFR(XBR0, 0xE1); // Port I/O Crossbar Control 0
SFR(XBR1, 0xE2); // Port I/O Crossbar Control 1
SFR(SFR0CN, 0xE5); // SFR Page Control
SFR(P0MDIN, 0xF1); // Port 0 Input Mode Configuration
SFR(P1MDIN, 0xF2); // Port 1 Input Mode Configuration
SFR(P2MDIN, 0xF3); // Port 2 Input Mode Configuration
SFR(P3MDIN, 0xF4); // Port 3 Input Mode Configuration
SFR(EMI0TC, 0xF7); // EMIF Timing Control
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
/* Interrupts */
#define INT_EXT0 0 // External Interrupt 0
#define INT_TIMER0 1 // Timer0 Overflow
#define INT_EXT1 2 // External Interrupt 1
#define INT_TIMER1 3 // Timer1 Overflow
#define INT_UART0 4 // Serial Port 0
#define INT_TIMER2 5 // Timer2 Overflow
#define INT_SPI0 6 // Serial Peripheral Interface 0
#define INT_SMBUS0 7 // SMBus0 Interface
// 8 Reserved
#define INT_ADC0_WINDOW 9 // ADC0 Window Comparison
#define INT_ADC0_EOC 10 // ADC0 End Of Conversion
#define INT_PCA0 11 // PCA0 Peripheral
#define INT_COMPARATOR0 12 // Comparator0
#define INT_COMPARATOR1 13 // Comparator1
#define INT_TIMER3 14 // Timer3 Overflow
// 15 Reserved
#define INT_PORT_MATCH 16 // Port Match
#endif

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/*-------------------------------------------------------------------------
C8051F410.h - Register Declarations for the SiLabs C8051F41x
Processor Range
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F410_H
#define C8051F410_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x84) CRC0CN ; /* CRC 0 CONTROL */
__sfr __at (0x85) CRC0IN ; /* CRC 0 DATA INPUT */
__sfr __at (0x86) CRC0DAT ; /* CRC 0 DATA OUTPUT */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
__sfr __at (0x97) IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xAB) CLKMUL ; /* CLOCK MULTIPLIER */
__sfr __at (0xAC) RTC0ADR ; /* SMARTCLOCK ADDRESS */
__sfr __at (0xAD) RTC0DAT ; /* SMARTCLOCK DATA */
__sfr __at (0xAE) RTC0KEY ; /* SMARTCLOCK LOCK AND KEY */
__sfr __at (0xAF) ONESHOT ; /* FLASH ONESHOT PERIOD */
__sfr __at (0xB0) P0ODEN ; /* PORT 0 OVERDRIVE */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB5) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
__sfr __at (0xBA) ADC0TK ; /* ADC 0 TRACKING MODE SELECT */
__sfr __at (0xBB) ADC0MX ; /* ADC 0 CHANNEL SELECT */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
__sfr __at (0xBF) P1MASK ; /* PORT 1 MASK */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
__sfr __at (0xC7) P0MASK ; /* PORT 0 MASK */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCE) PCA0CPM5 ; /* PCA MODULE 5 MODE REGISTER */
__sfr __at (0xCF) P1MAT ; /* PORT 1 MATCH */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD2) PCA0CPL5 ; /* PCA CAPTURE 5 LOW */
__sfr __at (0xD3) PCA0CPH5 ; /* PCA CAPTURE 5 HIGH */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
__sfr __at (0xD7) P0MAT ; /* PORT 0 MATCH */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
__sfr __at (0xDF) CRC0FLIP ; /* CRC 0 BIT FLIP */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) IDA1L ; /* CURRENT MODE DAC 1 - LOW BYTE */
__sfr __at (0xF5) IDA1H ; /* CURRENT MODE DAC 1 - HIGH BYTE */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0x9796) IDA0 ; /* CURRENT MODE DAC 0 DATA WORD */
__sfr16 __at (0xF5F4) IDA1 ; /* CURRENT MODE DAC 1 DATA WORD */
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
__sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
__sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
__sfr16 __at (0xD3D2) PCA0CP5 ; /* PCA CAPTURE 5 WORD */
/* BIT Registers */
/* P0 0x80 */
__sbit __at (0x80) P0_0 ;
__sbit __at (0x81) P0_1 ;
__sbit __at (0x82) P0_2 ;
__sbit __at (0x83) P0_3 ;
__sbit __at (0x84) P0_4 ;
__sbit __at (0x85) P0_5 ;
__sbit __at (0x86) P0_6 ;
__sbit __at (0x87) P0_7 ;
/* TCON 0x88 */
__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
__sbit __at (0x90) P1_0 ;
__sbit __at (0x91) P1_1 ;
__sbit __at (0x92) P1_2 ;
__sbit __at (0x93) P1_3 ;
__sbit __at (0x94) P1_4 ;
__sbit __at (0x95) P1_5 ;
__sbit __at (0x96) P1_6 ;
__sbit __at (0x97) P1_7 ;
/* SCON 0x98 */
__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
__sbit __at (0xA0) P2_0 ;
__sbit __at (0xA1) P2_1 ;
__sbit __at (0xA2) P2_2 ;
__sbit __at (0xA3) P2_3 ;
__sbit __at (0xA4) P2_4 ;
__sbit __at (0xA5) P2_5 ;
__sbit __at (0xA6) P2_6 ;
__sbit __at (0xA7) P2_7 ;
/* IE 0xA8 */
__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P0ODEN 0xB0 */
__sbit __at (0xB0) P0OD_0 ; /* P0ODEN.0 - PORT0.0 OVERDRIVE ENABLE */
__sbit __at (0xB1) P0OD_1 ; /* P0ODEN.1 - PORT0.1 OVERDRIVE ENABLE */
__sbit __at (0xB2) P0OD_2 ; /* P0ODEN.2 - PORT0.2 OVERDRIVE ENABLE */
__sbit __at (0xB3) P0OD_3 ; /* P0ODEN.3 - PORT0.3 OVERDRIVE ENABLE */
__sbit __at (0xB4) P0OD_4 ; /* P0ODEN.4 - PORT0.4 OVERDRIVE ENABLE */
__sbit __at (0xB5) P0OD_5 ; /* P0ODEN.5 - PORT0.5 OVERDRIVE ENABLE */
__sbit __at (0xB6) P0OD_6 ; /* P0ODEN.6 - PORT0.6 OVERDRIVE ENABLE */
__sbit __at (0xB7) P0OD_7 ; /* P0ODEN.7 - PORT0.7 OVERDRIVE ENABLE */
/* IP 0xB8 */
__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
__sbit __at (0xC9) T2RCLK ; /* TMR2CN.1 - TIMER 2 CAPTURE MODE */
__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
__sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
__sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
__sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
__sbit __at (0xDD) CCF5 ; /* PCA0CN.5 - PCA MODULE 5 CAPTURE/COMPARE FLAG */
__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
__sbit __at (0xEA) AD0LJST ; /* ADC0CN.2 - ADC 0 LEFT JUSTIFY SELECT */
__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
__sbit __at (0xEE) BURSTEN ; /* ADC0CN.6 - ADC 0 BURST MODE ENABLE */
__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
/* Interrupts */
#define INT_EXT0 0 // External Interrupt 0
#define INT_TIMER0 1 // Timer0 Overflow
#define INT_EXT1 2 // External Interrupt 1
#define INT_TIMER1 3 // Timer1 Overflow
#define INT_UART0 4 // Serial Port 0
#define INT_TIMER2 5 // Timer2 Overflow
#define INT_SPI0 6 // Serial Peripheral Interface 0
#define INT_SMBUS0 7 // SMBus0 Interface
#define INT_RTC0 8 // RTC0 Interface
#define INT_ADC0_WINDOW 9 // ADC0 Window Comparison
#define INT_ADC0_EOC 10 // ADC0 End Of Conversion
#define INT_PCA0 11 // PCA0 Peripheral
#define INT_COMPARATOR0 12 // Comparator0
#define INT_COMPARATOR1 13 // Comparator1
#define INT_TIMER3 14 // Timer3 Overflow
#define INT_VREG_DROPOUT 15 // VREG dropout
#define INT_PORT_MATCH 16 // Port Match
#endif

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/*-------------------------------------------------------------------------
C8051F520.h - Register Declarations for the SiLabs C8051F52x-F53x
Processor Range
Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F520_H
#define C8051F520_H
#include <compiler.h>
SFR(P0, 0x80); // Port 0
SBIT(P0_0, 0x80, 0); // Port 0 bit 0
SBIT(P0_1, 0x80, 1); // Port 0 bit 1
SBIT(P0_2, 0x80, 2); // Port 0 bit 2
SBIT(P0_3, 0x80, 3); // Port 0 bit 3
SBIT(P0_4, 0x80, 4); // Port 0 bit 4
SBIT(P0_5, 0x80, 5); // Port 0 bit 5
SBIT(P0_6, 0x80, 6); // Port 0 bit 6
SBIT(P0_7, 0x80, 7); // Port 0 bit 7
SFR(SP, 0x81); // Stack Pointer
SFR(DPL, 0x82); // Data Pointer Low Byte
SFR(DPH, 0x83); // Data Pointer High Byte
SFR(PCON, 0x87); // Power Mode Control
SFR(TCON, 0x88); // Timer Control
SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select
SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag
SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select
SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag
SBIT(TR0, 0x88, 4); // Timer 0 Run Control
SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag
SBIT(TR1, 0x88, 6); // Timer 1 Run Control
SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag
SFR(TMOD, 0x89); // Timer Mode
SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word
SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte
SFR(TH0, 0x8C); // Timer/Counter 0 High Byte
SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word
SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte
SFR(TH1, 0x8D); // Timer/Counter 1 High Byte
SFR(CKCON, 0x8E); // Clock Control
SFR(PSCTL, 0x8F); // Program Store R/W Control
SFR(P1, 0x90); // Port 1
SBIT(P1_0, 0x90, 0); // Port 1 bit 0
SBIT(P1_1, 0x90, 1); // Port 1 bit 1
SBIT(P1_2, 0x90, 2); // Port 1 bit 2
SBIT(P1_3, 0x90, 3); // Port 1 bit 3
SBIT(P1_4, 0x90, 4); // Port 1 bit 4
SBIT(P1_5, 0x90, 5); // Port 1 bit 5
SBIT(P1_6, 0x90, 6); // Port 1 bit 6
SBIT(P1_7, 0x90, 7); // Port 1 bit 7
SFR(LINADDR, 0x92); // LIN Indirect Address Pointer
SFR(LINDATA, 0x93); // LIN Indirect Data Buffer
SFR(LINCF, 0x95); // LIN Control Mode
SFR(SCON0, 0x98); // Serial Port 0 Control
SBIT(RI0, 0x98, 0); // Receive Interrupt Flag
SBIT(TI0, 0x98, 1); // Transmit Interrupt Flag
SBIT(RB80, 0x98, 2); // Ninth Receive Bit
SBIT(TB80, 0x98, 3); // Ninth Transmission Bit
SBIT(REN0, 0x98, 4); // Receive Enable
SBIT(MCE0, 0x98, 5); // Multiprocessor Communication Enable
SBIT(S0MODE, 0x98, 7); // Serial Port 0 Operation Mode
SFR(SBUF0, 0x99); // Serial Port 0 Data Buffer
SFR(CPT0CN, 0x9B); // Comparator 0 Control
SFR(CPT0MD, 0x9D); // Comparator 0 Mode Selection
SFR(CPT0MX, 0x9F); // Comparator 0 MUX Selection
SFR(SPI0CFG, 0xA1); // SPI Configuration
SFR(SPI0CKR, 0xA2); // SPI Clock Rate Control
SFR(SPI0DAT, 0xA3); // SPI Data
SFR(P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
SFR(P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
SFR(IE, 0xA8); // Interrupt Enable
SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0
SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt
SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1
SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt
SBIT(ES0, 0xA8, 4); // Enable Serial Port Interrupt
SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt
SBIT(ESPI0, 0xA8, 6); // Enable SPI0 Interrupt
SBIT(EA, 0xA8, 7); // Global Interrupt Enable
SFR(CLKSEL, 0xA9); // Clock Select
SFR(OSCIFIN, 0xB0); // Internal Oscillator Fine Calibration
SFR(OSCXCN, 0xB1); // External Oscillator Control
SFR(OSCICN, 0xB2); // Internal Oscillator Control
SFR(OSCICL, 0xB3); // Internal Oscillator Calibration
SFR(FLKEY, 0xB7); // Flash Lock and Key
SFR(IP, 0xB8); // Interrupt Priority
SBIT(PX0, 0xB8, 0); // External Interrupt 0 Priority
SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt Priority
SBIT(PX1, 0xB8, 2); // External Interrupt 1 Priority
SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt Priority
SBIT(PS0, 0xB8, 4); // Serial Port Interrupt Priority
SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt Priority
SBIT(PSPI0, 0xB8, 6); // SPI0 Interrupt Priority
SFR(ADC0TK, 0xBA); // ADC0 Tracking Mode Select
SFR(ADC0MX, 0xBB); // ADC0 Channel Select
SFR(ADC0CF, 0xBC); // ADC0 Configuration
SFR16(ADC0, 0xBD); // ADC0 Word
SFR(ADC0L, 0xBD); // ADC0 Low Byte
SFR(ADC0H, 0xBE); // ADC0 High Byte
SFR(P1MASK, 0xBF); // Port 1 Mask
SFR16(ADC0GT, 0xC3); // ADC0 Greater-Than Data Word
SFR(ADC0GTL, 0xC3); // ADC0 Greater-Than Data Low Byte
SFR(ADC0GTH, 0xC4); // ADC0 Greater-Than Data High Byte
SFR16(ADC0LT, 0xC5); // ADC0 Less-Than Data Word
SFR(ADC0LTL, 0xC5); // ADC0 Less-Than Data Low Byte
SFR(ADC0LTH, 0xC6); // ADC0 Less-Than Data High Byte
SFR(P0MASK, 0xC7); // Port 0 Mask
SFR(TMR2CN, 0xC8); // Timer/Counter 2 Control
SFR(REG0CN, 0xC9); // Voltage Regulator Control
SFR16(TMR2RL, 0xCA); // Timer/Counter 2 Reload Word
SFR(TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low Byte
SFR(TMR2RLH, 0xCB); // Timer/Counter 2 Reload High Byte
SFR16(TMR2, 0xCC); // Timer/Counter 2 Word
SFR(TMR2L, 0xCC); // Timer/Counter 2 Low Byte
SFR(TMR2H, 0xCD); // Timer/Counter 2 High Byte
SFR(P1MAT, 0xCF); // Port 1 Match
SFR(PSW, 0xD0); // Program Status Word
SBIT(P, 0xD0, 0); // Parity Flag
SBIT(F1, 0xD0, 1); // User-Defined Flag
SBIT(OV, 0xD0, 2); // Overflow Flag
SBIT(RS0, 0xD0, 3); // Register Bank Select 0
SBIT(RS1, 0xD0, 4); // Register Bank Select 1
SBIT(F0, 0xD0, 5); // User-Defined Flag
SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
SBIT(CY, 0xD0, 7); // Carry Flag
SFR(REF0CN, 0xD1); // Voltage Reference Control
SFR(P0SKIP, 0xD4); // Port 0 Skip
SFR(P1SKIP, 0xD5); // Port 1 Skip
SFR(P0MAT, 0xD7); // Port 0 Match
SFR(PCA0CN, 0xD8); // PCA Control
SBIT(CCF0, 0xD8, 0); // PCA Module 0 Capture/Compare Flag
SBIT(CCF1, 0xD8, 1); // PCA Module 1 Capture/Compare Flag
SBIT(CCF2, 0xD8, 2); // PCA Module 2 Capture/Compare Flag
SBIT(CR, 0xD8, 6); // PCA Counter/Timer Run Control
SBIT(CF, 0xD8, 7); // PCA Counter/Timer Overflow Flag
SFR(PCA0MD, 0xD9); // PCA Mode
SFR(PCA0CPM0, 0xDA); // PCA Module 0 Mode
SFR(PCA0CPM1, 0xDB); // PCA Module 1 Mode
SFR(PCA0CPM2, 0xDC); // PCA Module 2 Mode
SFR(ACC, 0xE0); // Accumulator
SFR(XBR0, 0xE1); // Port I/O Crossbar Control 0
SFR(XBR1, 0xE2); // Port I/O Crossbar Control 1
SFR(IT01CF, 0xE4); // INT0/INT1 Configuration
SFR(EIE1, 0xE6); // Extended Interrupt Enable 1
SFR(ADC0CN, 0xE8); // ADC0 Control
SBIT(AD0CM0, 0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
SBIT(AD0CM1, 0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
SBIT(AD0LJST, 0xE8, 2); // ADC0 Left Justify Select
SBIT(AD0WINT, 0xE8, 3); // ADC0 Window Compare Interrupt Flag
SBIT(AD0BUSY, 0xE8, 4); // ADC0 Busy Bit
SBIT(AD0INT, 0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
SBIT(BURSTEN, 0xE8, 6); // ADC0 Burst Mode Enable Bit
SBIT(AD0EN, 0xE8, 7); // ADC0 Enable Bit
SFR16(PCA0CP1, 0xE9); // PCA Capture 1 Word
SFR(PCA0CPL1, 0xE9); // PCA Capture 1 Low Byte
SFR(PCA0CPH1, 0xEA); // PCA Capture 1 High Byte
SFR16(PCA0CP2, 0xEB); // PCA Capture 2 Word
SFR(PCA0CPL2, 0xEB); // PCA Capture 2 Low Byte
SFR(PCA0CPH2, 0xEC); // PCA Capture 2 High Byte
SFR(RSTSRC, 0xEF); // Reset Source Configuration/Status
SFR(B, 0xF0); // B Register
SFR(P0MDIN, 0xF1); // Port 0 Input Mode Configuration
SFR(P1MDIN, 0xF2); // Port 1 Input Mode Configuration
SFR(EIP1, 0xF6); // Extended Interrupt Priority 1
SFR(SPI0CN, 0xF8); // SPI0 Control
SBIT(SPIEN, 0xF8, 0); // SPI0 Enable
SBIT(TXBMT, 0xF8, 1); // SPI0 Transmit Buffer Empty
SBIT(NSSMD0, 0xF8, 2); // SPI0 Slave Select Mode Bit 0
SBIT(NSSMD1, 0xF8, 3); // SPI0 Slave Select Mode Bit 1
SBIT(RXOVRN, 0xF8, 4); // SPI0 Receive Overrun Flag
SBIT(MODF, 0xF8, 5); // SPI0 Mode Fault Flag
SBIT(WCOL, 0xF8, 6); // SPI0 Write Collision Flag
SBIT(SPIF, 0xF8, 7); // SPI0 Interrupt Flag
SFR16(PCA0, 0xF9); // PCA Counter Word
SFR(PCA0L, 0xF9); // PCA Counter Low Byte
SFR(PCA0H, 0xFA); // PCA Counter High Byte
SFR16(PCA0CP0, 0xFB); // PCA Capture 0 Word
SFR(PCA0CPL0, 0xFB); // PCA Capture 0 Low Byte
SFR(PCA0CPH0, 0xFC); // PCA Capture 0 High Byte
SFR(VDDMON, 0xFF); // VDD Control
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
/* Interrupts */
#define INT_EXT0 0 // External Interrupt 0
#define INT_TIMER0 1 // Timer0 Overflow
#define INT_EXT1 2 // External Interrupt 1
#define INT_TIMER1 3 // Timer1 Overflow
#define INT_UART0 4 // Serial Port 0
#define INT_TIMER2 5 // Timer2 Overflow
#define INT_SPI0 6 // Serial Peripheral Interface 0
#define INT_ADC0_WINDOW 7 // ADC0 Window Comparison
#define INT_ADC0_EOC 8 // ADC0 End Of Conversion
#define INT_PCA0 9 // PCA0 Peripheral
#define INT_COMP_FALLING 10 // Comparator0 Falling
#define INT_COMP_RISING 11 // Comparator0 Rising
#define INT_LIN 12 // LIN
#define INT_VREG_DROPOUT 13 // VREG dropout
#define INT_PORT_MATCH 14 // Port Match
#endif

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/*-------------------------------------------------------------------------
C8051F920.h -Register Declarations for the SiLabs C8051F92x-93x
Processor Range
Copyright (C) 2009, Steven Borley, steven.borley@partnerelectronics.com
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051F920_H
#define C8051F920_H
#include <compiler.h>
/* BYTE Registers */
/* Page 0x00 (and all pages) */
SFR( P0, 0x80 ) ; /* PORT 0 */
SFR( SP, 0x81 ) ; /* STACK POINTER */
SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
SFR( SPI1CFG, 0x84 ) ; /* SPI1 Configuration */
SFR( SPI1CKR, 0x85 ) ; /* SPI1 Clock Rate Control */
SFR( SPI1DAT, 0x86 ) ; /* SPI1 Data */
SFR( PCON, 0x87 ) ; /* POWER CONTROL */
SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
SFR( TMOD, 0x89 ) ; /* TIMER MODE */
SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
SFR( PSCTL, 0x8F ) ; /* Program Store R/W Control */
SFR( P1, 0x90 ) ; /* PORT 1 */
SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
SFR( DC0CF, 0x96 ) ; /* DC0 (DC-DC Converter) Configuration */
SFR( DC0CN, 0x97 ) ; /* DC0 (DC-DC Converter) Control */
SFR( SCON0, 0x98 ) ; /* Serial Port Control */
SFR( SBUF0, 0x99 ) ; /* Serial Port Buffer */
SFR( CPT1CN, 0x9A ) ; /* Comparator 1 Control */
SFR( CPT0CN, 0x9B ) ; /* Comparator 0 Control */
SFR( CPT1MD, 0x9C ) ; /* Comparator 1 Mode Selection */
SFR( CPT0MD, 0x9D ) ; /* Comparator 0 Mode Selection */
SFR( CPT1MX, 0x9E ) ; /* Comparator 1 mux selection */
SFR( CPT0MX, 0x9F ) ; /* Comparator 0 mux selection */
SFR( P2, 0xA0 ) ; /* PORT 2 */
SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
SFR( SPI0CKR, 0xA2 ) ; /* SPI0 Clock Rate Control */
SFR( SPI0DAT, 0xA3 ) ; /* SPI0 Data */
SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
SFR( SFRPAGE, 0xA7 ) ; /* SFR Page */
SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
SFR( EMI0CN, 0xAA ) ; /* EMIF Control */
SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA page alias for SDCC */
SFR( EMI0CF, 0xAB ) ; /* EMIF Configuration */
SFR( RTC0ADR, 0xAC ) ; /* RTC0 Address */
SFR( RTC0DAT, 0xAD ) ; /* RTC0 Data */
SFR( RTC0KEY, 0xAE ) ; /* RTC0 Key */
SFR( EMI0TC, 0xAF ) ; /* EMIF Timing Control */
SFR( SPI1CN, 0xB0 ) ; /* SPI1 Control */
SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
SFR( PMU0CF, 0xB5 ) ; /* PMU0 Configuration */
SFR( FLSCL, 0xB6 ) ; /* IFlash Scale */
SFR( FLKEY, 0xB7 ) ; /* Flash Lock And Key */
SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
SFR( IREF0CN, 0xB9 ) ; /* Current Reference IREF Control */
SFR( ADC0AC, 0xBA ) ; /* ADC0 Accumulator Configuration */
SFR( ADC0MX, 0xBB ) ; /* AMUX0 Channel Select */
SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA - LOW BYTE */
SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA - HIGH BYTE */
SFR( P1MASK, 0xBF ) ; /* Port 1 Mask */
SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
SFR( P0MASK, 0xC7 ) ; /* Port 0 Mask */
SFR( TMR2CN, 0xC8 ) ; /* Timer 2 control */
SFR( REG0CN, 0xC9 ) ; /* Voltage Regulator (VREG0) Control */
SFR( TMR2RLL, 0xCA ) ; /* Timer 2 capture register - low byte */
SFR( TMR2RLH, 0xCB ) ; /* Timer 2 capture register - high byte */
SFR( TMR2L, 0xCC ) ; /* Timer 2 - low byte*/
SFR( TMR2H, 0xCD ) ; /* Timer 2 - high byte */
SFR( PCA0CPM5, 0xCE ) ; /* PCA0 Module 5 Mode Register */
SFR( P1MAT, 0xCF ) ; /* Port 1 Match */
SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
SFR( PCA0CPL5, 0xD2 ) ; /* PCA0 Capture 5 Low */
SFR( PCA0CPH5, 0xD3 ) ; /* PCA0 Capture 5 High */
SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */
SFR( P0MAT, 0xD7 ) ; /* Port 0 Match */
SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
SFR( PCA0CPM0, 0xDA ) ; /* PCA0 Module 0 Mode Register */
SFR( PCA0CPM1, 0xDB ) ; /* PCA0 Module 1 Mode Register */
SFR( PCA0CPM2, 0xDC ) ; /* PCA0 Module 2 Mode Register */
SFR( PCA0CPM3, 0xDD ) ; /* PCA0 Module 3 Mode Register */
SFR( PCA0CPM4, 0xDE ) ; /* PCA0 Module 4 Mode Register */
SFR( PCA0PWM, 0xDF ) ; /* PCA0 PWM Configuration */
SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
SFR( XBR0, 0xE1 ) ; /* Port Mux Configuration Register 0 */
SFR( XBR1, 0xE2 ) ; /* Port Mux Configuration Register 1 */
SFR( XBR2, 0xE3 ) ; /* Port Mux Configuration Register 2 */
SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 Configuration Register */
SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
SFR( EIE2, 0xE7 ) ; /* EXTERNAL INTERRUPT ENABLE 2 */
SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
SFR( PCA0CPL3, 0xED ) ; /* PCA0 Capture 3 Low */
SFR( PCA0CPH3, 0xEE ) ; /* PCA0 Capture 3 High */
SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
SFR( B, 0xF0 ) ; /* B REGISTER */
SFR( P0MDIN, 0xF1 ) ; /* Port 0 Input Mode Configuration */
SFR( P1MDIN, 0xF2 ) ; /* Port 1 Input Mode Configuration */
SFR( P2MDIN, 0xF3 ) ; /* Port 2 Input Mode Configuration */
SFR( SMB0ADR, 0xF4 ) ; /* SMBus Slave Address */
SFR( SMB0ADM, 0xF5 ) ; /* SMBus Slave Address Mask */
SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
SFR( EIP2, 0xF7 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
SFR( SPI0CN, 0xF8 ) ; /* SPI0 Control */
SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
SFR( PCA0CPL4, 0xFD ) ; /* PCA0 Capture 4 Low */
SFR( PCA0CPH4, 0xFE ) ; /* PCA0 Capture 4 High */
SFR( VDM0CN, 0xFF ) ; /* VDD Monitor Control */
/* Page 0x0F only */
SFR( TOFFL, 0x85 ) ; /* Temperature Offset Low */
SFR( TOFFH, 0x86 ) ; /* Temperature Offset High */
SFR( CRC0DAT, 0x91 ) ; /* CRC0 Data */
SFR( CRC0CN, 0x92 ) ; /* CRC0 Control */
SFR( CRC0IN, 0x93 ) ; /* CRC0 Input */
SFR( CRC0FLIP, 0x95 ) ; /* CRC0 Flip */
SFR( CRC0AUTO, 0x96 ) ; /* CRC0 Automatic Control */
SFR( CRC0CNT, 0x97 ) ; /* CRC0 Automatic Flash Sector Count */
SFR( P0DRV, 0xA4 ) ; /* Port 0 Drive Strength */
SFR( P1DRV, 0xA5 ) ; /* Port 1 Drive Strength */
SFR( P2DRV, 0xA6 ) ; /* Port 2 Drive Strength */
SFR( ADC0PWR, 0xBA) ; /* ADC0 Burst Mode Power-Up Time */
SFR( ADC0TK, 0xBD) ; /* ADC0 Tracking Control */
/* WORD/DWORD Registers */
/* page 0x00 */
SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
SFR16E( TMR3RL, 0x9392 ) ; /* Timer 3 reload word */
SFR16E( TMR3, 0x9594 ) ; /* Timer 3 counter word */
SFR16E( ADC0, 0xBEBD ) ; /* ADC0 word */
SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
SFR16E( TMR2RL, 0xCBCA ) ; /* Timer 2 reload word */
SFR16E( TMR2, 0xCDCC ) ; /* Timer 2 counter word */
SFR16E( TMR2RL, 0xCBCA ) ; /* Timer 2 Reload word */
SFR16E( PCA0, 0xFAF9 ) ; /* PCA0 counter word */
SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA0 Capture 0 word */
SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA0 Capture 1 word */
SFR16E( PCA0CP2, 0xECEB ) ; /* PCA0 Capture 2 word */
SFR16E( PCA0CP3, 0xEEED ) ; /* PCA0 Capture 3 word */
SFR16E( PCA0CP4, 0xFEFD ) ; /* PCA0 Capture 4 word */
SFR16E( PCA0CP5, 0xD3D4 ) ; /* PCA0 Capture 5 word */
/* Page 0x0F */
SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
/* BIT Registers */
/* P0 0x80 */
SBIT( P0_0, 0x80, 0 ) ;
SBIT( P0_1, 0x80, 1 ) ;
SBIT( P0_2, 0x80, 2 ) ;
SBIT( P0_3, 0x80, 3 ) ;
SBIT( P0_4, 0x80, 4 ) ;
SBIT( P0_5, 0x80, 5 ) ;
SBIT( P0_6, 0x80, 6 ) ;
SBIT( P0_7, 0x80, 7 ) ;
/* TCON 0x88 */
SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
SBIT( P1_0, 0x90, 0 ) ;
SBIT( P1_1, 0x90, 1 ) ;
SBIT( P1_2, 0x90, 2 ) ;
SBIT( P1_3, 0x90, 3 ) ;
SBIT( P1_4, 0x90, 4 ) ;
SBIT( P1_5, 0x90, 5 ) ;
SBIT( P1_6, 0x90, 6 ) ;
SBIT( P1_7, 0x90, 7 ) ;
/* SCON0 0x98 */
SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
SBIT( P2_0, 0xA0, 0 ) ;
SBIT( P2_1, 0xA0, 1 ) ;
SBIT( P2_2, 0xA0, 2 ) ;
SBIT( P2_3, 0xA0, 3 ) ;
SBIT( P2_4, 0xA0, 4 ) ;
SBIT( P2_5, 0xA0, 5 ) ;
SBIT( P2_6, 0xA0, 6 ) ;
SBIT( P2_7, 0xA0, 7 ) ;
/* IE 0xA8 */
SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
SBIT( IEGF0, 0xA8, 6 ) ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* SPI1CN 0xB0 */
SBIT( SPI1EN, 0xB0, 0 ) ; /* SPI1 Enable */
SBIT( TXBMT1, 0xB0, 1 ) ; /* SPI1 Transmit Buffer Empty */
SBIT( NSS1MD0, 0xB0, 2 ) ; /* SPI1 Slave Select Mode bit-0 */
SBIT( NSS1MD1, 0xB0, 3 ) ; /* SPI1 Slave Select Mode bit-1 */
SBIT( RXOVRN1, 0xB0, 4 ) ; /* SPI1 Receive Overrun Flag */
SBIT( MODF1, 0xB0, 5 ) ; /* SPI1 Mode Fault Flag */
SBIT( WCOL1, 0xB0, 6 ) ; /* SPI1 Write Collision Flag */
SBIT( SPIF1, 0xB0, 7 ) ; /* SPI1 Interrupt Flag */
/* IP 0xB8 */
SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
SBIT( SPI0EN, 0xF8, 0 ) ; /* SPI0 Enable */
SBIT( TXBMT0, 0xF8, 1 ) ; /* SPI0 Transmit Buffer Empty */
SBIT( NSS0MD0, 0xF8, 2 ) ; /* SPI0 Slave Select Mode bit-0 */
SBIT( NSS0MD1, 0xF8, 3 ) ; /* SPI0 Slave Select Mode bit-1 */
SBIT( RXOVRN0, 0xF8, 4 ) ; /* SPI0 Receive Overrun Flag */
SBIT( MODF0, 0xF8, 5 ) ; /* SPI0 Mode Fault Flag */
SBIT( WCOL0, 0xF8, 6 ) ; /* SPI0 Write Collision Flag */
SBIT( SPIF0, 0xF8, 7 ) ; /* SPI0 Interrupt Flag */
/* Indirectly accessed registers */
/* smaRTClock Internal Registers */
#define CAPTURE0 0x00 /* smaRTClock Capture register 0 */
#define CAPTURE1 0x01 /* smaRTClock Capture register 1 */
#define CAPTURE2 0x02 /* smaRTClock Capture register 2 */
#define CAPTURE3 0x03 /* smaRTClock Capture register 3 */
#define RTC0CN 0x04 /* smaRTClock Control */
#define RTC0XCN 0x05 /* smaRTClock Oscillator Control */
#define RTC0XCF 0x06 /* smaRTClock Oscillator Configuration */
#define RTC0PIN 0x07 /* smaRTClock Pin Configuration */
#define ALARM0 0x08 /* smaRTClock Alarm Register 0 */
#define ALARM1 0x09 /* smaRTClock Alarm Register 1 */
#define ALARM2 0x0A /* smaRTClock Alarm Register 2 */
#define ALARM3 0x0B /* smaRTClock Alarm Register 3 */
/* Predefined SFR Bit Masks */
/* PCON 0x87 */
#define PCON_IDLE (1<<0) /* PCON */
#define PCON_STOP (1<<1) /* PCON */
/* CKON 0x8E */
#define T0M (1<<2) /* CKCON Timer 0 Clock Select */
#define T1M (1<<3) /* CKCON Timer 1 Clock Select */
/* PSCTL 0x8F */
#define PSWE (1<<0) /* Program Store Write Enable */
#define PSEE (1<<1) /* Program Store Erase Enable */
#define SFLE (1<<2) /* Scratchpad Flash Access Enable */
/* EIE1 0xE6 */
#define ESMB0 (1<<0) /* Enable SMBus (SMB0) Interrupt */
#define ERTC0A (1<<1) /* Enable smaRTClock Alarm Interrupts */
#define EWADC0 (1<<2) /* Enable Window Comparison ADC0 Int. */
#define EADC0 (1<<3) /* Enable ADC0 Convert Complete Int. */
#define EPCA0 (1<<4) /* Enable PCA0 Interrupt */
#define ECP0 (1<<5) /* Enable Comparator0 (CP0) Interrupt */
#define ECP1 (1<<6) /* Enable Comparator1 (CP1) Interrupt */
#define ET3 (1<<7) /* Enable Timer 3 Interrupt */
/* RSTSRC */
#define PINRSF (1<<0) /* HW Pin Reset Flag */
#define PORSF (1<<1) /* Power-on/fail Reset Rlag */
#define MCDRSF (1<<2) /* Missing Clock Detector Reset Rlag */
#define WDTRSF (1<<3) /* Watchdog Timer Reset Rlag */
#define SWRSF (1<<4) /* Software Force/Reset Rlag */
#define C0RSEF (1<<5) /* Comparator0 Reset Rlag */
#define FERROR (1<<6) /* Flash Error Reset Rlag */
#define RTC0RE (1<<7) /* smaRTClock Reset Rlag */
/* PCA0CPMn */
#define ECCF (1<<0) /* Capture/Compare Flag Interrupt En. */
#define PWM (1<<1) /* Pulse Width Modulation Mode Enable */
#define TOG (1<<2) /* Toggle Function Enable */
#define MAT (1<<3) /* Match Function Enable */
#define CAPN (1<<4) /* Capture Negative Function Enable */
#define CAPP (1<<5) /* Capture Positive Function Enable. */
#define ECOM (1<<6) /* Comparator Function Enable. */
#define PWM16 (1<<7) /* 16-bit Pulse Width Modulation Enable*/
/* XBR0 0xE1 */
#define URT0E (1<<0) /* UART0 I/O enable */
#define SPI0E (1<<1) /* SPI0 I/O Enable */
#define SMB0E (1<<2) /* SMBus I/O Enable */
#define SYSCKE (1<<3) /* SYSCLK Output Enable. */
#define CP0E (1<<4) /* Comparator0 Output Enable */
#define CP0AE (1<<5) /* Comparator0 Asynchronous Output En. */
#define CP1E (1<<6) /* Comparator1 Output Enable */
#define CP1AE (1<<7) /* Comparator1 Asynchronous Output En. */
/* XBR1 0xE2 */
#define PCA0ME0 (1<<0) /* PCA0 Module I/O Enable bit-0 */
#define PCA0ME1 (1<<1) /* PCA0 Module I/O Enable bit-1 */
#define PCA0ME2 (1<<2) /* PCA0 Module I/O Enable bit-2 */
#define ECIE (1<<3) /* PCA0 Ext. Counter Input Enable */
#define T0E (1<<4) /* Timer0 Input Enable */
#define T1E (1<<5) /* Timer1 Input Enable */
#define SPI1E (1<<6) /* SPI1 I/O Enable */
/* XBR2 0xE3 */
#define XBARE (1<<6) /* Crossbar Enable */
#define WEAKPUD (1<<7) /* Port I/O Weak Pullup Disable */
/* Interrupts */
#define INT_EXT0 0 /* External Interrupt 0*/
#define INT_TIMER0 1 /* Timer0 Overflow */
#define INT_EXT1 2 /* External Interrupt 1 */
#define INT_TIMER1 3 /* Timer1 Overflow */
#define INT_UART0 4 /* Serial Port 0 */
#define INT_TIMER2 5 /* Timer2 Overflow */
#define INT_SPI0 6 /* SPI0 */
#define INT_SMBUS0 7 /* SMBus0 Interface */
#define INT_ALARM 8 /* smaRTClock Alarm */
#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
#define INT_PCA0 11 /* PCA0 Peripheral */
#define INT_CP0 12 /* Comparator 0 */
#define INT_CP1 13 /* Comparator 1 */
#define INT_TIMER3 14 /* Timer3 Overflow */
#define INT_VWARN 15 /* VDD/DC+ Supply Monitor early warning */
#define INT_MATCH 16 /* Port Match */
#define INT_OSCFAIL 17 /* smaRTClock Oscillator Fail */
#define INT_SPI1 18 /* SPI1 */
/* aliases - these map alternative names to names use in the datasheet */
#define SCON SCON0 /* Serial Port Control */
#define SBUF SBUF0 /* Serial Port Buffer */
#define T2CON TMR2CN /* Timer 2 control */
#define RCAP2 TMR2RL /* Timer 2 capture register word */
#define RCAP2L TMR2RLL /* Timer 2 capture register - low byte */
#define RCAP2H TMR2RLH /* Timer 2 capture register - high byte */
#define T2 TMR2 /* Timer 2 - word */
#define TL2 TMR2L /* Timer 2 - low byte */
#define TH2 TMR2H /* Timer 2 - high byte */
#define PRT0MX XBR0 /* Port Mux Configuration Register 0 */
#define PRT1MX XBR1 /* Port Mux Configuration Register 1 */
#define PRT2MX XBR2 /* Port Mux Configuration Register 2 */
#define IT01CF INT01CF /* INT0/INT1 Configuration Register */
#define P0MODE P0MDIN /* Port 0 Input Mode Configuration */
#define P1MODE P1MDIN /* Port 1 Input Mode Configuration */
#define P2MODE P2MDIN /* Port 2 Input Mode Configuration */
#define CP0OEN CP0E /* Comparator 0 Output Enable bit */
#define CP0AOEN CP0AE /* Comparator 0 Asynchronous Output En. bit */
#endif /* C8051F920_H */

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/*-------------------------------------------------------------------------
C8051T600.h - Register Declarations for the SiLabs C8051T60x Processor
Range
Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051T600_H
#define C8051T600_H
#include <compiler.h>
/* BYTE Registers */
SFR( P0, 0x80 ) ; /* PORT 0 */
SFR( SP, 0x81 ) ; /* STACK POINTER */
SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
SFR( PCON, 0x87 ) ; /* POWER CONTROL */
SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
SFR( TMOD, 0x89 ) ; /* TIMER MODE */
SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
SFR( TOFFL, 0xA2 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */
SFR( TOFFH, 0xA3 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */
SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
SFR( AMX0SL, 0xBB ) ; /* ADC 0 MUX CHANNEL SELECTION */
SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA - LOW BYTE */
SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA - HIGH BYTE */
SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */
SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
SFR( PRT0MX, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
SFR( PRT1MX, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
SFR( PRT2MX, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */
SFR( XBR2, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */
SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
SFR( B, 0xF0 ) ; /* B REGISTER */
SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
SFR( CPT0CN, 0xF8 ) ; /* COMPARATOR 0 CONTROL */
SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
/* WORD/DWORD Registers */
SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
SFR16E( TOFF, 0xA3A2 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
SFR16E( ADC0, 0xAEAD ) ; /* ADC0 DATA WORD */
SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
/* BIT Registers */
/* P0 0x80 */
SBIT( P0_0, 0x80, 0 ) ;
SBIT( P0_1, 0x80, 1 ) ;
SBIT( P0_2, 0x80, 2 ) ;
SBIT( P0_3, 0x80, 3 ) ;
SBIT( P0_4, 0x80, 4 ) ;
SBIT( P0_5, 0x80, 5 ) ;
SBIT( P0_6, 0x80, 6 ) ;
SBIT( P0_7, 0x80, 7 ) ;
/* TCON 0x88 */
SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* SCON 0x98 */
SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* IE 0xA8 */
SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
SBIT( IEGF0, 0xA8, 6 ) ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* IP 0xB8 */
SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
/* SMB0CN 0xC0 */
SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
/* CPT0CN 0xF8 */
SBIT( CP0HYN0, 0xF8, 0 ) ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
SBIT( CP0HYN1, 0xF8, 1 ) ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
SBIT( CP0HYP0, 0xF8, 2 ) ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
SBIT( CP0HYP1, 0xF8, 3 ) ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
SBIT( CP0FIF, 0xF8, 4 ) ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
SBIT( CP0RIF, 0xF8, 5 ) ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
SBIT( CP0OUT, 0xF8, 6 ) ; /* CPT0CN.6 - Comparator0 Output State Flag */
SBIT( CP0EN, 0xF8, 7 ) ; /* CPT0CN.7 - Comparator0 Enable Bit */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x10 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0F 0x10 /* EIE1 */
#define ECP0R 0x20 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR1 */
#define CP0OEN 0x10 /* XBR1 */
#define CP0AE 0x20 /* XBR1 */
#define CP0AOEN 0x20 /* XBR1 */
/* Interrupts */
#define INT_EXT0 0 /* External Interrupt 0 */
#define INT_TIMER0 1 /* Timer0 Overflow */
#define INT_EXT1 2 /* External Interrupt 1 */
#define INT_TIMER1 3 /* Timer1 Overflow */
#define INT_UART0 4 /* Serial Port 0 */
#define INT_TIMER2 5 /* Timer2 Overflow */
#define INT_SMBUS0 6 /* SMBus0 Interface */
#define INT_ADC0_WINDOW 7 /* ADC0 Window Comparison */
#define INT_ADC0_EOC 8 /* ADC0 End Of Conversion */
#define INT_PCA0 9 /* PCA0 Peripheral */
#define INT_CP0F 10 /* Comparator0 falling edge */
#define INT_CP0R 11 /* Comparator1 rising edge */
#endif

364
OperatingSystem/.unused/cmon/sdcc/share/sdcc/include/mcs51/C8051T610.h Normal file
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@@ -0,0 +1,364 @@
/*-------------------------------------------------------------------------
C8051T610.h - Register Declarations for the SiLabs C8051T61x Processor
Range
Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com
This library is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any
later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this library; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA.
As a special exception, if you link this library with other files,
some of which are compiled with SDCC, to produce an executable,
this library does not by itself cause the resulting executable to
be covered by the GNU General Public License. This exception does
not however invalidate any other reasons why the executable file
might be covered by the GNU General Public License.
-------------------------------------------------------------------------*/
#ifndef C8051T610_H
#define C8051T610_H
#include <compiler.h>
/* BYTE Registers */
SFR( P0, 0x80 ) ; /* PORT 0 */
SFR( SP, 0x81 ) ; /* STACK POINTER */
SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
SFR( TOFFL, 0x85 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */
SFR( TOFFH, 0x86 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */
SFR( PCON, 0x87 ) ; /* POWER CONTROL */
SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
SFR( TMOD, 0x89 ) ; /* TIMER MODE */
SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
SFR( P1, 0x90 ) ; /* PORT 1 */
SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
SFR( CPT1CN, 0x9A ) ; /* COMPARATOR 1 CONTROL */
SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */
SFR( CPT1MD, 0x9C ) ; /* COMPARATOR 1 MODE SELECTION */
SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
SFR( CPT1MX, 0x9E ) ; /* COMPARATOR 1 MUX SELECTION */
SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
SFR( P2, 0xA0 ) ; /* PORT 2 */
SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */
SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */
SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
SFR( P3MDOUT, 0xA7 ) ; /* PORT 3 OUTPUT MODE CONFIGURATION */
SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */
SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */
SFR( P3, 0xB0 ) ; /* PORT 3 */
SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */
SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */
SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */
SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */
SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */
SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */
SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */
SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */
SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
SFR( PCA0CPM3, 0xDD ) ; /* PCA MODULE 3 MODE REGISTER */
SFR( PCA0CPM4, 0xDE ) ; /* PCA MODULE 4 MODE REGISTER */
SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
SFR( PCA0CPL3, 0xED ) ; /* PCA CAPTURE 3 LOW */
SFR( PCA0CPH3, 0xEE ) ; /* PCA CAPTURE 3 HIGH */
SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
SFR( B, 0xF0 ) ; /* B REGISTER */
SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
SFR( P2MODE, 0xF3 ) ; /* PORT 2 INPUT MODE CONFIGURATION */
SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE CONFIGURATION */
SFR( P3MODE, 0xF4 ) ; /* PORT 3 INPUT MODE CONFIGURATION */
SFR( P3MDIN, 0xF4 ) ; /* PORT 3 INPUT MODE CONFIGURATION */
SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */
SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
SFR( PCA0CPL4, 0xFD ) ; /* PCA CAPTURE 4 LOW */
SFR( PCA0CPH4, 0xFE ) ; /* PCA CAPTURE 4 HIGH */
SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */
SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */
SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */
SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
SFR16E( PCA0CP3, 0xEEED ) ; /* PCA CAPTURE 3 WORD */
SFR16E( PCA0CP4, 0xFEFD ) ; /* PCA CAPTURE 4 WORD */
/* BIT Registers */
/* P0 0x80 */
SBIT( P0_0, 0x80, 0 ) ;
SBIT( P0_1, 0x80, 1 ) ;
SBIT( P0_2, 0x80, 2 ) ;
SBIT( P0_3, 0x80, 3 ) ;
SBIT( P0_4, 0x80, 4 ) ;
SBIT( P0_5, 0x80, 5 ) ;
SBIT( P0_6, 0x80, 6 ) ;
SBIT( P0_7, 0x80, 7 ) ;
/* TCON 0x88 */
SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
/* P1 0x90 */
SBIT( P1_0, 0x90, 0 ) ;
SBIT( P1_1, 0x90, 1 ) ;
SBIT( P1_2, 0x90, 2 ) ;
SBIT( P1_3, 0x90, 3 ) ;
SBIT( P1_4, 0x90, 4 ) ;
SBIT( P1_5, 0x90, 5 ) ;
SBIT( P1_6, 0x90, 6 ) ;
SBIT( P1_7, 0x90, 7 ) ;
/* SCON 0x98 */
SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
/* P2 0xA0 */
SBIT( P2_0, 0xA0, 0 ) ;
SBIT( P2_1, 0xA0, 1 ) ;
SBIT( P2_2, 0xA0, 2 ) ;
SBIT( P2_3, 0xA0, 3 ) ;
SBIT( P2_4, 0xA0, 4 ) ;
SBIT( P2_5, 0xA0, 5 ) ;
SBIT( P2_6, 0xA0, 6 ) ;
SBIT( P2_7, 0xA0, 7 ) ;
/* IE 0xA8 */
SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */
SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
/* P3 0xB0 */
SBIT( P3_0, 0xB0, 0 ) ;
SBIT( P3_1, 0xB0, 1 ) ;
SBIT( P3_2, 0xB0, 2 ) ;
SBIT( P3_3, 0xB0, 3 ) ;
SBIT( P3_4, 0xB0, 4 ) ;
SBIT( P3_5, 0xB0, 5 ) ;
SBIT( P3_6, 0xB0, 6 ) ;
SBIT( P3_7, 0xB0, 7 ) ;
/* IP 0xB8 */
SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */
/* SMB0CN 0xC0 */
SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
/* TMR2CN 0xC8 */
SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
/* PSW 0xD0 */
SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
/* PCA0CN 0xD8 */
SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
SBIT( CCF3, 0xD8, 3 ) ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
SBIT( CCF4, 0xD8, 4 ) ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
/* ADC0CN 0xE8 */
SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
/* SPI0CN 0xF8 */
SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */
SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */
SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */
SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
/* Predefined SFR Bit Masks */
#define PCON_IDLE 0x01 /* PCON */
#define PCON_STOP 0x02 /* PCON */
#define T1M 0x08 /* CKCON */
#define PSWE 0x01 /* PSCTL */
#define PSEE 0x02 /* PSCTL */
#define ECP0 0x20 /* EIE1 */
#define ECP1 0x40 /* EIE1 */
#define PORSF 0x02 /* RSTSRC */
#define SWRSF 0x10 /* RSTSRC */
#define ECCF 0x01 /* PCA0CPMn */
#define PWM 0x02 /* PCA0CPMn */
#define TOG 0x04 /* PCA0CPMn */
#define MAT 0x08 /* PCA0CPMn */
#define CAPN 0x10 /* PCA0CPMn */
#define CAPP 0x20 /* PCA0CPMn */
#define ECOM 0x40 /* PCA0CPMn */
#define PWM16 0x80 /* PCA0CPMn */
#define CP0E 0x10 /* XBR0 */
#define CP0OEN 0x10 /* XBR0 */
#define CP0AE 0x20 /* XBR0 */
#define CP0AOEN 0x20 /* XBR0 */
#define CP1E 0x40 /* XBR0 */
#define CP1AE 0x80 /* XBR0 */
/* Interrupts */
#define INT_EXT0 0 /* External Interrupt 0 */
#define INT_TIMER0 1 /* Timer0 Overflow */
#define INT_EXT1 2 /* External Interrupt 1 */
#define INT_TIMER1 3 /* Timer1 Overflow */
#define INT_UART0 4 /* Serial Port 0 */
#define INT_TIMER2 5 /* Timer2 Overflow */
#define INT_SPI0 6 /* Serial Peripheral Interface 0 */
#define INT_SMBUS0 7 /* SMBus0 Interface */
/* 8 Reserved */
#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
#define INT_PCA0 11 /* PCA0 Peripheral */
#define INT_COMPARATOR0 12 /* Comparator0 */
#define INT_COMPARATOR1 13 /* Comparator1 */
#define INT_TIMER3 14 /* Timer3 Overflow */
#endif

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