New features

PLDs/Z8C-GPU-Board-U/XXXXX.jed

@@ -0,0 +1,26 @@
+
+CUPL(WM)        5.0a  Serial# 60008009
+Device          g16v8as  Library DLIB-h-40-2
+Created         Tue Nov 08 17:28:30 2022
+Name            XXXXX
+Partno          XXXXX
+Revision        XX
+Date            XX/XX/XX
+Designer        XXXXX
+Company         XXXXX
+Assembly        XXXXX
+Location        XXXXX
+*QP20 
+*QF2194 
+*G0 
+*F0 
+*L00000 11101111111111111111111101111111
+*L00256 11110111111111111111111111111111
+*L00512 11101111111111111111111111111111
+*L02048 01100000010110000101100001011000
+*L02080 01011000010110000000000000000000
+*L02112 00000000000111111111111111111111
+*L02144 11111111111111111111111111111111
+*L02176 111111111111111110
+*C154C
+*8CB5

PLDs/Z8C-GPU-Board-U/Z8C-MAINBOARD.pdf

@@ -0,0 +1,151 @@
+{COMPONENT C:\USERS\DG\DOCUMENTS\Z80-GIT\PLDS\Z8C-GPU-BOARD-U\Z8C-MAINBOARD.SYM
+
+ {ENVIRONMENT
+  {PDIFvrev 3.00}
+  {Program "CUPL(WM) Version 5.0a"}
+  {DBtype "Schematic"}
+  {DBvrev 1.01}
+  {DBtime "Tue Nov 08 17:28:30 2022 "}
+  {DBunit "MIL"}
+  {DBgrid 10}
+  {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1 
+          "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1 
+          "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4 
+          "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+  {VIEW
+   {Mode SYMB}
+   {Nlst OPEN}
+   {Vw 0 0 2}
+   {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+   {Gs 10 10}
+  }
+ }
+
+ {DISPLAY
+  [Ly "PINNUM"]
+  [Ls "SOLID"][Wd 0]
+  [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+  {PIN_DEF
+   [Ly "PINCON"]
+   {P IOREQ {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+   {P RD {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+   {P WR {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+   {P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+   {P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+   {P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+   {P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+   {P A7 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+   {P CRTC_E {Pt "I/O"}{Lq 0}{Ploc 320 20}}
+   {P CRTC_RW {Pt "I/O"}{Lq 0}{Ploc 320 40}}
+   {P CRTC_CS {Pt "I/O"}{Lq 0}{Ploc 320 60}}
+  }
+
+  {PKG
+   [Ly "REFDES"]
+   [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+   {Rdl 210 190}
+
+   [Ly "PINNUM"]
+   [Ts 15][Tj "RC"]
+   {Pnl 120 170}
+   {Pnl 120 150}
+   {Pnl 120 130}
+   {Pnl 120 110}
+   {Pnl 120 90}
+   {Pnl 120 70}
+   {Pnl 120 50}
+   {Pnl 120 30}
+   [Ts 15][Tj "LC"]
+   {Pnl 300 30}
+   {Pnl 300 50}
+   {Pnl 300 70}
+
+   {Sd A 1 2 3 4 5 6 7 8 17 18 19}
+  }
+
+  {PIC
+   [Ly "GATE"]
+   [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+   {R 130 180 290 0}
+   {L 130 160 100 160}
+   {L 130 140 100 140}
+   {L 130 120 100 120}
+   {L 130 100 100 100}
+   {L 130 80 100 80}
+   {L 130 60 100 60}
+   {L 130 40 100 40}
+   {L 130 20 100 20}
+   {L 290 20 320 20}
+   {L 290 40 320 40}
+   {L 290 60 320 60}
+   [Ly "PINNAM"]
+   [Tj "LC"]
+   {T "IOREQ" 140 160}
+   {T "RD" 140 140}
+   {T "WR" 140 120}
+   {T "A0" 140 100}
+   {T "A1" 140 80}
+   {T "A2" 140 60}
+   {T "A3" 140 40}
+   {T "A7" 140 20}
+   [Tj "RC"]
+   {T "CRTC_E" 280 20}
+   {T "CRTC_RW" 280 40}
+   {T "CRTC_CS" 280 60}
+   [Ly "DEVICE"]
+   [Tj "CT"]
+   {T "G16V8AS" 210 -10}
+  }
+
+  {ATR
+   {IN
+    {Org 100 20}
+    {Ty 255}
+   }
+   {EX
+    [Ly "ATTR2"]
+    [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+    {At PLD C:\USERS\DG\DOCUMENTS\Z80-GIT\PLDS\Z8C-GPU-BOARD-U\Z8C-MAINBOARD 210 180}
+   }
+  }
+ }
+
+ {DETAIL
+  {ANNOTATE
+  }
+
+  {NET_DEF
+   {N IOREQ
+   }
+   {N RD
+   }
+   {N WR
+   }
+   {N A0
+   }
+   {N A1
+   }
+   {N A2
+   }
+   {N A3
+   }
+   {N A7
+   }
+   {N CRTC_E
+   }
+   {N CRTC_RW
+   }
+   {N CRTC_CS
+   }
+  }
+
+  {SUBCOMP
+  }
+ }
+}

PLDs/Z8C-GPU-Board-U/Z8C-MAINBOARD.pla

@@ -0,0 +1,25 @@
+# Berkeley PLA format generated using
+#
+# CUPL(WM)        5.0a Serial# 60008009
+# Device          g16v8as  Library DLIB-h-40-2
+# Created         Tue Nov 08 17:28:30 2022
+# Name            XXXXX
+# Partno          XXXXX
+# Revision        XX
+# Date            XX/XX/XX
+# Designer        XXXXX
+# Company         XXXXX
+# Assembly        XXXXX
+# Location        XXXXX
+#
+# Inputs  A0 A1 A2 A3 
+#         A7 CRTC_CS CRTC_E CRTC_RW 
+#         IOREQ RD WR 
+# Outputs !CRTC_CS CRTC_E CRTC_RW 
+.i 11
+.o 3
+.p 3
+----1---0-- 1~~
+--------0-- ~1~
+----------1 ~~1
+.end

PLDs/Z8C-GPU-Board-U/Z8C-MAINBOARD.sim

@@ -0,0 +1,28 @@
+%SIGNAL
+PIN   4 =  A0 
+PIN   5 =  A1 
+PIN   6 =  A2 
+PIN   7 =  A3 
+PIN   8 =  A7 
+PIN  19 =  CRTC_CS 
+PIN  17 =  CRTC_E 
+PIN  18 =  CRTC_RW 
+PIN   1 =  IOREQ 
+PIN   2 =  RD 
+PIN   3 =  WR 
+%END
+
+%FIELD
+%END
+
+%EQUATION
+CRTC_CS =>
+    A7 & !IOREQ
+
+CRTC_E =>
+    !IOREQ
+
+CRTC_RW =>
+    WR
+
+%END

PLDs/Z8C-GPU-Board-U/Z8C-Mainboard.pld

@@ -0,0 +1,28 @@
+Name       XXXXX;
+Partno     XXXXX;
+Date       XX/XX/XX;
+Revision   XX;
+Designer   XXXXX;
+Company    XXXXX;
+Assembly   XXXXX;
+Location   XXXXX;
+DEVICE g16v8a;
+
+Pin 1 = IOREQ;
+Pin 2 = RD;
+Pin 3 = WR;
+
+Pin 4 = A0;
+Pin 5 = A1;
+Pin 6 = A2;
+Pin 7 = A3;
+Pin 8 = A7;
+
+Pin 19 = CRTC_CS;
+Pin 18 = CRTC_RW;
+Pin 17 = CRTC_E;
+
+CRTC_CS = !(A7 & !IOREQ );
+CRTC_RW = WR;
+CRTC_E = !IOREQ;
+

PLDs/Z8C-GPU-Board-U/tmpcsim.im

@@ -0,0 +1,28 @@
+
+CUPL(WM)        5.0a  Serial# 60008009
+Device          g16v8as  Library DLIB-h-40-2
+Created         Thu Oct 20 08:10:08 2022
+Name            XXXXX
+Partno          XXXXX
+Revision        XX
+Date            XX/XX/XX
+Designer        XXXXX
+Company         XXXXX
+Assembly        XXXXX
+Location        XXXXX
+*QP20 
+*QF2194 
+*G0 
+*F0 
+*L00000 10011011101110111011101110111010
+*L00512 11110111101110111011101110111011
+*L00768 11111011011110111011101110111011
+*L01024 10101011101110111011101110101011
+*L02048 00000000010110000101100001011000
+*L02080 01011000010110000000000000000000
+*L02112 00000000010001111111111111111111
+*L02144 11111111111111111111111111111111
+*L02176 111111111111111110
+*C16AE
+*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+*